Unicore

UnicoreDesigner| Microprocessor Research and Development Center

|

Bits| 32-bit
Introduced| 1999
Design| RISC
Encoding| Fixed
Branching| Condition code
Endianness| Little
Page size| 4 KiB
Registers
General purpose| 31
Floating point| 32

Unicore is the name of a computer instruction set architecture designed by the Microprocessor Research and Development Center (MPRC) of Peking University in the PRC. The computer built on this architecture is called the Unity-863.[1] The CPU is integrated into a fully functional SoC to make a PC-like system.[2]

The processor is very similar to the ARM architecture, but uses a different instruction set.[3][better source needed]

It is supported by the Linux kernel as of version 2.6.39.[4] Support will be removed in Linux kernel version 5.9 as nobody seems to maintain it and the code is falling behind the rest of the kernel code and compiler requirements.[5]

## Instruction set

The instructions are almost identical to the standard ARM formats, except that conditional execution has been removed, and the bits reassigned to expand all the register specifiers to 5 bits.[6][7] Likewise, the immediate format is 9 bits rotated by a 5-bit amount (rather than 8 bit rotated by 4), the load/store offset sizes are 14 bits for byte/word and 10 bits for signed byte or half-word. Conditional moves are provided by encoding the condition in the (unused by ARM) second source register field Rn for MOV and MVN instructions.

Unicore32 instruction set overview[8] Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Script error: No such module "Vertical header". | Description

|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|

0 | 0 | 0 | opcode | S | Rn | Rd | shift | 0 | Sh | 0 | Rm | ALU operation, Rd = Rn op Rm shift #shift
0 | 0 | 0 | opcode | S | Rn | Rd | Rs | 0 | Sh | 1 | Rm | ALU operation, Rd = Rn op Rm shift Rs
0 | 0 | 1 | opcode | S | Rn | Rd | shift | imm9 | ALU operation, Rd = Rn op #imm9 ROTL #shift
0 | 1 | 0 | P | U | B | W | L | Rn | Rd | shift | 0 | Sh | 0 | Rm | Load/store Rd to address Rn ± Rm shift #shift
0 | 1 | 1 | P | U | B | W | L | Rn | Rd | offset14 | Load/store Rd to address Rn ± offset14
1 | 0 | 0 | P | U | S | W | L | Rn | Bitmap high | 0 | 0 | H | Bitmap low | Load/store multiple registers
1 | 0 | 1 | cond | L | offset24 | Branch (and link) if condition true
1 | 1 | 0 |  | Coprocessor (FPU) instructions
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | Trap number | Software interrupt
0 | 0 | 0 | 0 | 0 | 0 | A | S | Rn | Rd | Rs | 1 | 0 | 0 | 1 | Rm | Multiply, Rd = Rm * Rs (+ Rn)
0 | 0 | 0 | 1 | 0 | 0 | 0 | L | 11111 | 11111 | 00000 | 1 | 0 | 0 | 1 | Rm | Branch and exchange (BX, BLX)
0 | 1 | 0 | P | U | 0 | W | L | Rn | Rd | 00000 | 1 | S | H | 1 | Rm | Load/store Rd to address Rn ± Rm (16-bit)
0 | 1 | 0 | P | U | 1 | W | L | Rn | Rd | imm_hi | 1 | S | H | 1 | imm_lo | Load/store Rd to address Rn ± #imm10 (16-bit)

The meaning of various flag bits (such as S=1 enables setting the condition codes) is identical to the ARM instruction set. The load/store multiple instruction can only access half of the register set, depending on the H bit. If H=0, the 16 bits indicate R0–R15; if H=1, R16–R31.

## References

1. ↑ "Introduction to MPRC". Microprocessor Research and Develop Center, Peking University. http://mprc.pku.cn/eng/intro.html.
2. ↑ Xu Cheng; Xiaoyin Wang; Junlin Lu; Jiangfang Yi; Dong Tong; Xuetao Guan; Feng Liu; Xianhua Liu et al. (March 2010), "Research Progress of UniCore CPUs and PKUnity SoCs", Journal of Computer Science and Technology (JCST) 25 (2): 200–213, doi:10.1007/s11390-010-9317-1, http://mprc.pku.edu.cn/~guanxuetao/publications/2010-JCST-CX.pdf, retrieved 2012-07-11
3. ↑ Bergmann, Arnd (2012-07-09). "Re: [PATCH 00/36] AArch64 Linux kernel port". linux-kernel (Mailing list). Retrieved 2012-07-11. "Another interesting example is unicore32, which actually shares more code with arch/arm than the proposed arch/aarch64 does. I think the unicore32 code base would benefit from being merged back into arch/arm as a third instruction set, but the additional maintenance cost for everyone working on ARM makes that unrealistic."
4. ↑ "Merge window closed - 2.6.39-rc1 out". Linus Torvalds. https://lkml.org/lkml/2011/3/29/351.
5. ↑ "remove unicore32 support". Mike Rapoport. https://lkml.org/lkml/2020/8/3/232.
6. ↑ Hsu-Hung Chiang; Huang-Jia Cheng; Yuan-Shin Hwan (2012-02-25), "Doubling the Number of Registers on ARM Processors", 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT), pp. 1–8, doi:10.1109/INTERACT.2012.6339620, ISBN 978-1-4673-2613-1, http://aces.snu.ac.kr/interact-16/papers/interact-16-paper-1.pdf
7. ↑ Unicore processor simulator source code. Instruction formats are in decode.c, disassembly in interpret.c, and emulation in instEx.c.
8. ↑ QEMU Unicore32 emulator source code

* v
* t
* e

Reduced instruction set computer (RISC) architectures

* IBM 801
* Berkeley RISC
* Stanford MIPS

Active|

* Analog Devices Blackfin
* ARC
* ARM
* AVR
* eSi-RISC
* LatticeMico8
* LatticeMico32
* MIPS
* OpenRISC
* Power ISA
* Renesas M32R
* Renesas SuperH
* Renesas V850
* RISC-V
* Sunway
* SPARC
* Unicore
* Xilinx MicroBlaze
* Xilinx PicoBlaze
* POWER
* PowerPC
* XMOS XCore XS1

Historic|

* Alpha
* AMD Am29000
* Apollo PRISM
* Atmel AVR32
* Clipper
* CRISP
* DEC Prism
* Intel i860
* Intel i960
* Meta
* MIPS-X
* Motorola 88000
* Motorola M·CORE
* PA-RISC
* ROMP

* v
* t
* e

Processor technologies

Models|

* Turing machine
* Universal
* Post–Turing
* Quantum
* Belt machine
* Stack machine
* Finite-state machine
* with datapath
* Hierarchical
* Queue automaton
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load/store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* comparison
* addressing modes

|

* x86
* ARM
* MIPS
* Power ISA
* SPARC
* Itanium
* Unicore
* MicroBlaze
* RISC-V
* others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Tomasulo algorithm
* Reservation station
* Re-order buffer
* Register renaming

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* SWAR
* SIMT
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Coprocessor
* ASIC
* FPGA
* CPLD
* Multi-chip module (MCM)
* System in package (SiP)

| By application|

* Microprocessor
* Microcontroller
* Mobile
* Notebook
* Ultra-low-voltage
* ASIP

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Programmable (PSoC)
* Network on a chip (NoC)

Hardware
accelerators|

* AI accelerator
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor processing unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 2-bit
* 4-bit
* 8-bit
* 16-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Integrated memory controller (IMC)

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Program counter

Control unit|

* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)
* Race to sleep

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model

0.00

(0 votes)

Original source: https://en.wikipedia.org/wiki/Unicore. Read more

|

Retrieved from "https://handwiki.org/wiki/index.php?title=Unicore&oldid=233050"
*[v]: View this template
*[t]: Discuss this template
*[e]: Edit this template