Hardware watermarking

Hardware watermarking, also known as IP core watermarking is the process of embedding covert marks as design attributes inside a hardware or IP core design itself. Hardware Watermarking can represent watermarking of either DSP Cores (widely used in consumer electronics devices) or combinational/sequential circuits. Both forms of Hardware Watermarking are very popular. In DSP Core Watermarking a secret mark is embedded within the logic elements of the DSP Core itself. DSP Core Watermark usually implants this secret mark in the form of a robust signature either in the RTL design or during High Level Synthesis (HLS) design. The watermarking process of a DSP Core leverages on the High Level Synthesis framework and implants a secret mark in one (or more) of the high level synthesis phases such as scheduling, allocation and binding. DSP Core Watermarking is performed to protect a DSP core from hardware threats such as IP piracy, forgery and false claim of ownership.[1][2][3][4] Some examples of DSP cores are FIR filter, IIR filter, FFT, DFT, JPEG, HWT etc. Few of the most important properties of a DSP core watermarking process are as follows: (a) Low embedding cost (b) Secret mark (c) Low creation time (d) Strong tamper tolerance (e) Fault tolerance.[5][6]

## Contents

* 1 Process of hardware watermarking
* 1.1 Single-phase watermarking process
* 1.2 Multi-phase watermarking process
* 2 See also
* 3 References

## Process of hardware watermarking

Hardware or IP core watermarking in the context of DSP/Multimedia Cores are significantly different from watermarking of images/digital content. IP Cores are usually complex in size and nature and thus require highly sophisticated mechanisms to implant signatures within their design without disturbing the functionality. Any small change in the functionality of the IP core renders the hardware watermarking process futile. Such is the sensitivity of this process. Hardware Watermarking[7][8][9] can be performed in two ways: (a) Single-phase watermarking, (b) Multi-phase watermarking.

### Single-phase watermarking process

As the name suggests, in single-phase watermarking process the secret marks in the form of additional constraints are inserted in a particular phase of design abstraction level. Among the all design abstraction level of Electronic design automation process inserting watermarking constraints at High-level synthesis is always beneficial, especially where the applications have complex algorithms (such as Digital signal processor, Media processor). The register allocation phase of High-level synthesis is one of the popular locations where single-phase watermarking constraints are inserted. Mostly the secret marks are inserted in the register allocation phase using the concept of Graph coloring, where each additional constraint is added as an additional edge of the graph. Moreover, the additional constraints are mapped with an encoded variable for providing another layer of security. In binary encoding process[2] the signature is provided in the form of 0 and 1; where each digit indicates a decoded constraints. In multi-variable encoding process [3][7] the signature is provided in the form of four different variables viz. 'i', 'T', 'I', '!'.

### Multi-phase watermarking process

As the name suggests, in the multi-phase watermarking process the additional constraints are inserted in multiple phases of a particular design abstraction level. For example, in High-level synthesis scheduling, hardware allocation and register allocation are used to insert a watermark. The main challenge of the multi-phase watermarking process is the dependence between additional constraints of multiple phases. In an ideal scenario, the watermarking constraints of each phase should not depend on each other. In other words, if somehow the watermarking constraints of a particular phase are tampered or removed, it should not impact the constraints of other phases. In multi-phase encoding process [1][4] the signature is provided in the form of seven different variables viz. 'α', 'β', 'γ' 'i', 'T', 'I', '!'; where γ inserts watermark in scheduling phase, α and β insert watermark in hardware allocation phase, i, T, I, and ! insert watermark in the register allocation phase.

## See also

* Hardware obfuscation
* Semiconductor intellectual property core
* High-level synthesis
* Electronic design automation
* Graph coloring

## References

1. ↑ 1.0 1.1 Anirban Sengupta, Dipanjan Roy, Saraju P Mohanty, "Triple-Phase Watermarking for Reusable IP Core Protection during Architecture Synthesis", IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems (TCAD), Volume: 37, Issue: 4, April 2018, pp. 742 - 755
2. ↑ 2.0 2.1 F. Koushanfar, I. Hong, and M. Potkonjak, “Behavioral synthesis techniques for intellectual property protection”, ACM Trans. Des. Autom. Electron. Syst., Vol. 10, No. 3, 2005, pp. 523-545
3. ↑ 3.0 3.1 Anirban Sengupta, Dipanjan Roy "Anti-Piracy aware IP Chipset Design for CE Devices: Robust Watermarking Approach", IEEE Consumer Electronics, Volume: 6, Issue: 2, April 2017, pp. 118 - 124
4. ↑ 4.0 4.1 Anirban Sengupta, Saumya Bhadauria, "Exploring Low Cost Optimal Watermark for Reusable IP Cores during High Level Synthesis", IEEE Access Journal, Volume:4, Issue: 99, pp. 2198 - 2215, May 2016
5. ↑ Anirban Sengupta, Saumya Bhadauria "IP core Protection of CDFGs using Robust Watermarking during Behavioral Synthesis Based on User Resource Constraint and Loop Unrolling Factor", IET Electronics Letters, Vol. 52 No. 6 pp. 439-441, March 2016
6. ↑ Anirban Sengupta, Dipanjan Roy "Automated Low Cost Scheduling Driven Watermarking Methodology for Modern CAD High-Level Synthesis Tools" Elsevier Journal of Advances in Engineering Software, Volume 110, August 2017, pp 26-33
7. ↑ 7.0 7.1 Dipanjan Roy, Anirban Sengupta "Low Overhead Symmetrical Protection of Reusable IP Core using Robust Fingerprinting and Watermarking during High Level Synthesis", Elsevier Journal on Future Generation Computer Systems, Volume 71, June 2017, pp. 89–101
8. ↑ Anirban Sengupta, Saumya Bhadauria, Saraju Mohanty "Embedding Low Cost Optimal Watermark During High Level Synthesis for Reusable IP Core Protection", Proc. of 48th IEEE Int'l Symposium on Circuits & Systems (ISCAS), Montreal, May 2016, pp. 974 - 977
9. ↑ S. P. Mohanty, A. Sengupta, P. Guturu, and E. Kougianos, "Everything You Want to Know About Watermarking: From Paper Marks to Hardware Protection", IEEE Consumer Electronics, Volume 7, Issue 3, July 2017, pp. 83--91

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