Monolayer doping

Short description: Technique used in semiconductor production

Monolayer doping (MLD) in semiconductor production is a well controlled, wafer-scale surface doping technique first developed at the University of California, Berkeley, in 2007.[1] This work is aimed for attaining controlled doping of semiconductor materials with atomic accuracy, especially at nanoscale, which is not easily obtained by other existing technologies. This technique is currently used for fabricating ultrashallow junctions (USJs) as the heavily doped source/drain (S/D) contacts of metal–oxide–semiconductor field effect transistors (MOSFETs) as well as enabling dopant profiling of nanostructures.

This MLD technique utilizes the crystalline nature of semiconductors and its self-limiting surface reaction properties to form highly uniform, self-assembled, covalently bonded dopant-containing monolayers followed by a subsequent annealing step for the incorporation and diffusion of dopants.[1] The monolayer formation reaction is self-limiting, thereby resulting in the deterministic coverage of dopant atoms on the surface. MLD differs from other conventional doping techniques such as spin-on-dopants (SODs) and gas phase doping techniques in the way of dopant dose control. Such control in MLD is much more precise due to the self-limiting formation of covalently attached dopants on the surface while the SODs just rely on the thickness control of the spin-on oxide and the gas phase technique depends on the control of dopant gas flow rate; therefore, the excellent dose control in MLD can yield the exact tuning of the resulting dopant profile. Compared to ion-implantation, MLD does not involve the energetic introduction of dopant species into the semiconductor lattice where crystal damages are induced. In the case of implantation, defects such as interstitials and vacancies are inevitably generated, which interact with the dopants to further broaden the junction profile. This is known as the transient-enhanced diffusion (TED), which limits the formation of good quality of USJs. Also, stochastic variation in the dopant positioning and severe stoichiometric imbalance are thus induced for binary and tertiary compound semiconductors by the implantation techniques. In contrast, all MLD dopant atoms are thermally diffused from the crystal surface to the bulk and the dopant profile can be easily controlled by the thermal budget. Since the MLD system can be classified as a limited source model, this is desirable for controlled USJ fabrication with high uniformity and low stochastic variation. Combined with the excellent dopant dose uniformity and coverage in MLD, it is especially attractive for doping nonplanar devices such as fin-FETs and nanowires. As a result, high quality sub-5 nm ultra-shallow junction has been demonstrated in silicon via the use of this MLD technique.[2] Compared to low-energy ion-implantation into a screening film followed by in-diffusion,[3][4] the MLD technique requires a lower thermal budget and allows conformal doping on topographic features.

## Applications in various structures

The MLD process is applicable for both p- and n-doping of various nanostructured materials, including conventional planar substrates, nanobelts and nanowires, which are fabricated by either the ‘bottom-up’ or ‘top-down’ approaches, making it highly versatile for various applications. In p-type doping of silicon, a covalently anchored monolayer of allylboronic acid pinacol ester is formed on the surface as the boron precursor while a monolayer of diethyl 1-propylphosphonate is used as the phosphorus precursor in n-type doping.[1] For example, in the case of USJ formation, combining the phosphorus-MLD and conventional spike annealing, the record 5 nm junction (down to 2 nm - the SIMS resolution limit) with the noncontact Rs measurements (~5000 Ω/□) is reported and being consistent with the predicted values from the dopant profile.[2] Notably, ~70 % of the dopants are electrically active as the MLD process utilizes an equilibrium based diffusion mechanism.[2]

In addition to silicon, MLD has also been applied to compound semiconductors such as indium arsenide (InAs) to obtain high quality ultra-shallow junctions. For the past years, controlling the post-growth dopant profiles in compound semiconductors such as III-V materials deterministically has not been well achieved due to the challenges in controlling the recovered stoichiometry after the implantation and sequential annealing. These residual damages can lead to higher junction leakage and lower dopant activation in compound semiconductors. Utilizing the MLD technique with sulfur dopants, a dopant profile abruptness of ~ 3.5 nm/decade with high electrically active sulfur concentrations of ~ 8–1018 cm−3 is observed in InAs without significant defect density.[5] The MLD capping layer serves as i) preventing group V elements to desorb and ii) avoiding the dopant atoms to be lost to the ambient in order to result in the good quality junctions.

## Control of area dose and junction profile

An important characteristic of the use of the substrate surface chemistry is the ability to readily control the areal dose of the dopants by forming a mixed monolayer of ‘blank’ and dopant-containing molecules. For instance, a mixture of boron precursor molecules and dodecene (all-carbon ‘blank’ precursor) in different ratios is utilized to manipulate the areal dose of boron.[1] Besides the mixed monolayer formation, the areal dose can be readily tuned by using the molecular structure details of the dopant precursor. In specific, the molecular footprint of the precursor directly governs the surface concentration of the dopants, with larger molecules resulting in a lower dose. In this regard, using trioctylphosphine oxide (TOP) as the phosphorus precursor with an approximately six-fold larger molecular footprint than DPP, the dopant dose can be modulated in the reduction of six times accordingly.[1] Moreover, the doping profiles can be readily tuned through optimization of the annealing conditions. In this case, the high surface doping density with sharp spatial decay can be obtained by using this MLD method with low anneal temperatures and short times for the formation of USJs.[2] The ability to controllably tune the dopant dose through the structural design of the precursor and to control the dopant profile by the annealing conditions present a unique aspect of the MLD process for attaining the desired dopant dose and profile.

This technology is currently being examined by industry for the USJ S/D contacts of future nanoscale transistors based on Si and III-V compound semiconductors.[6]

## References

1. ↑ 1.0 1.1 1.2 1.3 1.4 Ho, Johnny C.; Yerushalmi, Roie; Jacobson, Zachery A.; Fan, Zhiyong; Alley, Robert L.; Javey, Ali (2007-11-11). "Controlled nanoscale doping of semiconductors via molecular monolayers". Nature Materials (Springer Science and Business Media LLC) 7 (1): 62–67. doi:10.1038/nmat2058. ISSN 1476-1122. PMID 17994026.
2. ↑ 2.0 2.1 2.2 2.3 Ho, Johnny C.; Yerushalmi, Roie; Smith, Gregory; Majhi, Prashant; Bennett, Joseph; Halim, Jeffri; Faifer, Vladimir N.; Javey, Ali (2009-02-11). "Wafer-Scale, Sub-5 nm Junction Formation by Monolayer Doping and Conventional Spike Annealing". Nano Letters (American Chemical Society (ACS)) 9 (2): 725–730. doi:10.1021/nl8032526. ISSN 1530-6984. PMID 19161334.
3. ↑ Schmitz, J.; van Gestel, M.; Stolk, P.A.; Ponomarev, Y.V.; Roozeboom, F.; van Berkum, J.G.M.; Zalm, P.C.; Woerlee, P.H.. "Ultra-shallow junction formation by outdiffusion from implanted oxide". International Electron Devices Meeting 1998. San Francisco, CA, USA: IEEE. p. 1009. doi:10.1109/iedm.1998.746525. ISBN 0-7803-4774-9.
4. ↑ P. A. Stolk, J. Schmitz, F. N. Cubaynes, A. C. M. C. van Brandenburg, J. G. M. van Berkum and W. G. van der Wijgert, "The effect of thin oxide layers on shallow junction formation," ESSDERC proceedings, page 428, 1999.
5. ↑ Ho, Johnny C.; Ford, Alexandra C.; Chueh, Yu-Lun; Leu, Paul W.; Ergen, Onur et al. (2009-08-17). "Nanoscale doping of InAs via sulfur monolayers". Applied Physics Letters (AIP Publishing) 95 (7): 072108. doi:10.1063/1.3205113. ISSN 0003-6951.
6. ↑ Barnett, Joel; Hill, Richard; Loh, Wei-Yip; Hobbs, Chris; Majhi, Prashant; Jammy, Raj (2010). "Advanced techniques for achieving ultra-shallow junctions in future CMOS devices". International Workshop Junction Technology. IEEE. pp. 1–4. doi:10.1109/iwjt.2010.5474968. ISBN 978-1-4244-5866-0.

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