Block floating point

Short description: Method in computer arithmetic

Floating-point formats

IEEE 754

* 16-bit: Half (binary16)
* 32-bit: Single (binary32), decimal32
* 64-bit: Double (binary64), decimal64
* 128-bit: Quadruple (binary128), decimal128
* 256-bit: Octuple (binary256)
* Extended-precision formats (40-bit or 80-bit)

Other

* Minifloat
* bfloat16
* Microsoft Binary Format
* IBM floating-point architecture
* Posit
* G.711 8-bit floats
* Arbitrary precision

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Block floating point (BFP) is a method used to provide an arithmetic approaching floating point while using a fixed-point processor. BFP assigns a group of significands (the non-exponent part of the floating-point number) to a single exponent, rather than single significand being assigned its own exponent. BFP can be advantageous to limit space use in hardware to perform the same functions as floating-point algorithms, by reusing the exponent; some operations over multiple values between blocks can also be done with a reduced amount of computation.[1]

The common exponent is found by data with the largest amplitude in the block. To find the value of the exponent, the number of leading zeros must be found (count leading zeros). For this to be done, the number of left shifts needed for the data must be normalized to the dynamic range of the processor used. Some processors have means to find this out themselves, such as exponent detection and normalization instructions.[2][3]

Block floating-point algorithms were extensively studied by James Hardy Wilkinson.[4][5][6]

BFP can be recreated in software for smaller performance gains.

## Contents

* 1 Microscaling (MX) formats
* 1.1 Further development
* 2 Hardware support
* 2.1 BFP with fixed-point elements
* 2.2 BFP with minifloat elements
* 2.3 Other types of BFP
* 3 See also
* 4 References
* 5 Further reading

## Microscaling (MX) formats

Microscaling (MX) formats are a type of Block Floating Point (BFP) data format specifically designed for AI and machine learning workloads. Very small floating-point numbers (minifloats) are used in machine learning for performance, but like fixed-point numbers they suffer from reduced representable ranges. Using a shared exponent allows for increasing the range of representable values at very little space and performance overhead.[7][8] The MX format, endorsed and standardized by major industry players such as AMD, Arm, Intel, Meta, Microsoft, NVIDIA, and Qualcomm, represents a significant advancement in narrow precision data formats for AI.[9]

The MX format contains a block of k (usually set to 32) elements, each being d bits long. These elements share a scaling factor of w bits, so that the entire block is w \+ kd bits in size. Standard MX data types include:[10]

Name | Element data type | d | k | Scale data type | w | Bits per block

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|
|
|
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MXFP8 (E5M2) | FP8 (E5M2) | 8 | 32 | E8M0 | 8 | 264
MXFP8 (E4M3) | FP8 (E4M3) | 8 | 32 | E8M0 | 8 | 264
MXFP6 (E6M2) | FP6 (E3M2) | 6 | 32 | E8M0 | 8 | 200
MXFP6 (E2M3) | FP6 (E2M3) | 6 | 32 | E8M0 | 8 | 200
MXFP4 | FP4 (E2M1) | 4 | 32 | E8M0 | 8 | 136
MXINT8 | INT8 | 8 | 32 | E8M0 | 8 | 264

Here E8M0 is effectively the exponent part of a single-precision floating number, being able to represent powers of 2 between 2−127 and 2127. A single value is reserved for NaN. For descriptions of data types such as FP8-E5M2, see Minifloat § Machine learning.

MX formats have been demonstrated to be effective in a variety of AI tasks, including large language models (LLMs), image classification, speech recognition and recommendation systems.[11] For instance, MXFP6 closely matches FP32 for inference tasks after quantization-aware fine-tuning, and MXFP4 can be used for training generative language models with only a minor accuracy penalty.

The MX format has been standardized through the Open Compute Project (OCP) as Microscaling Formats (MX) Specification v1.0.[9][10] An emulation libraries also has been published to provide details on the data science approach and select results of MX in action.[12]

### Further development

The MXFP4 format groups 32 4-bit minifloats with very low dynamic range together. In an effort to reduce quantization artifacts, Nvidia has introduced NVFP4, which instead only groups 16 FP4-E2M1 numbers in a block and changes the scaling factor to E4M3 for more precision. To regain dynamic range, the many blocks in a tensor is then subject to a shared fp32 (E8M23) scaling factor for a two-layer setup. No M0 numbers are used for scaling; as a result, all scaling requires an actual multiplication instead of bit shifting or simple manipulation of the exponent part of a floating-point value.[13]

Comparison of MXFP4 and NVFP4, each being 4 bits long (d), contains a block of k elements and sharing a scaling factor of 8 bits (w), so that the entire block is d·k \+ w bits in size:

Name | Element data type | d | k | Scale data type | w | Bits per block

|
|
|
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MXFP4 | FP4 (E2M1) | 4 | 32 | E8M0 | 8 | 136
NVFP4 | FP4 (E2M1) | 4 | 16 | E4M3 | 8 | 72

## Hardware support

Hardware support for BFP exists in two layers: support for the underlying data type of the members (integer fixed-point or minifloats) and faster implementation of the scaling operation.

### BFP with fixed-point elements

* d-Matrix Jayhawk II handles BFP12, BFP16, and SBFP12.[14] These data types are fixed-point-based BFP: BFP12 refers to having a shared 8-bit exponent with a group of UINT4 elements, BFP16 refers to having a shared 8-bit exponent with a group of UINT8 elements, and SBFP12 refers to having a shared 8-bit exponent with a group of signed INT4 elements.[15]
* Tenstorrent Grayskull e75 and e150 as well as Wormhole n150 and n300 support what the manufacturer calls BFP8, BFP4 and BFP2.[16] The members have no exponent of their own; in other words, they are scaled fixed-point.[17]
* AMD Strix Point APU (branded as Ryzen AI 300 series) supports Block FP16 in the XDNA2 neural processing unit (NPU).[18][19] Again, the elements do not have exponents of their own.[20]

### BFP with minifloat elements

The parallel handling of minifloat numbers is more complex to emulate in software compared to handling of packed integers. As a result, hardware support for the underlying minifloat goes a long way in offering BFP-with-minifloat support.

* x86 processors implementing the AVX10.2 extension set support the OCP-FP8 formats E5M2 and E4M3 in packed format. The extension does not add accelerated block scaling, which can be done using singular existing operations.[21]
* AMD Instinct GPUs support OCP-FP8 and packed MXFP8 (E5M2, E4M3) since CDNA 3. CDNA 4 adds support for MXFP4 and MXFP6. CDNA4 also supports MXINT8, a format with fixed-point elements.
* The tensor cores of Nvidia GPUs support FP8 since Hopper (microarchitecture). FP4 and FP6 are added in Blackwell (microarchitecture).[22] The 32-wide size of MX formats is well-suited to the structure of tensor cores which also provide accelerated hardware scaling.[23] Blackwell also provides accelerated scaling for NVFP4.[13]
* Intel Gaudi 2 and later accelerators also support FP8.[24]

### Other types of BFP

* AMD Versal AI Edge Series Gen 2 supports MX6 and MX9 data types. These data types have two-tiered sharing of exponents, a compromise between standard MX and fixed-point-based BFP.[25] The hardware also supports fast INT8 operations for use in traditional BFP.[26]

## See also

* Binary scaling
* Fast Fourier transform (FFT)
* Digital signal processor (DSP)

## References

1. ↑ "Block floating point". BDTI DSP Dictionary. Berkeley Design Technology, Inc. (BDTI). http://www.bdti.com/Resources/DSPDictionary.
2. ↑ "TMS320C55x A Block Floating Point Implementation on the TMS320C54x DSP". Texas Instruments. December 1999. http://www.eeng.dcu.ie/~ee206/pdf/block_flt_pt.pdf.
3. ↑ "A Block Floating Point Implementation for an N-Point FFT on the TMS320C55x DSP". Texas Instruments. September 2003. http://www.ti.com/lit/an/spra948/spra948.pdf.
4. ↑ Rounding Errors in Algebraic Processes (1 ed.). Englewood Cliffs, NJ, USA: Prentice-Hall, Inc.. 1994. ISBN 978-0-486-67999-0. https://books.google.com/books?id=yFogU9Ot-qsC.
5. ↑ Handbook of Floating-Point Arithmetic (1 ed.). Birkhäuser. 2010. doi:10.1007/978-0-8176-4705-6. ISBN 978-0-8176-4704-9.
6. ↑ Numerical Computing with IEEE Floating Point Arithmetic - Including One Theorem, One Rule of Thumb and One Hundred and One Exercises (1 ed.). Society for Industrial and Applied Mathematics (SIAM). 2001. 9-780898-714821-90000. ISBN 0-89871-482-6.
7. ↑ Rouhani, Bita Darvish; Zhao, Ritchie; More, Ankit; Hall, Mathew; Khodamoradi, Alireza; Deng, Summer; Choudhary, Dhruv; Cornea, Marius; Dellinger, Eric (2023-10-19). "Microscaling Data Formats for Deep Learning". arXiv:2310.10537 [cs.LG].
8. ↑ D'Sa, Reynold; Borkar, Rani (2023-10-17). "Fostering AI infrastructure advancements through standardization" (in en-US). https://azure.microsoft.com/en-us/blog/fostering-ai-infrastructure-advancements-through-standardization/.
9. ↑ 9.0 9.1 "AMD, Arm, Intel, Meta, Microsoft, NVIDIA, and Qualcomm Standardize Next-Generation Narrow Precision Data Formats for AI" (in en). https://www.opencompute.org/blog/amd-arm-intel-meta-microsoft-nvidia-and-qualcomm-standardize-next-generation-narrow-precision-data-formats-for-ai.
10. ↑ 10.0 10.1 "OCP Microscaling Formats (MX) Specification Version 1.0". https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf.
11. ↑ Rouhani, Bita; Zhao, Ritchie; Elango, Venmugil; Shafipour, Rasoul; Hall, Mathew; Mesmakhosroshahi, Maral; More, Ankit; Melnick, Levi; Golub, Maximilian (2023-04-12). "With Shared Microexponents, A Little Shifting Goes a Long Way". arXiv:2302.08007 [cs.LG].
12. ↑ microsoft/microxcaling, Microsoft, 2024-05-29, https://github.com/microsoft/microxcaling, retrieved 2024-06-03
13. ↑ 13.0 13.1 "Introducing NVFP4 for Efficient and Accurate Low-Precision Inference". 24 June 2025. https://developer.nvidia.com/blog/introducing-nvfp4-for-efficient-and-accurate-low-precision-inference/.
14. ↑ Shilov, Anton (19 September 2023). "D-Matrix's Jayhawk II Addresses Edge and Cloud AI Workloads". https://www.eetimes.com/d-matrixs-jayhawk-ii-addresses-edge-and-cloud-ai-workloads/.
15. ↑ Trukhanov, Nikita; Soloveychik, Ilya (2024). "Accurate Block Quantization in LLMS with Outliers". arXiv:2403.20137v1 [cs.AI].
16. ↑ "Tenstorrent AI Accelerators". https://tenstorrent.com/wp-content/uploads/2024/03/20231219_AIB_One_Pager_gv.pdf.
17. ↑ "Data Formats and Math Fidelity — TT Buda documentation". https://docs.tenstorrent.com/pybuda/latest/dataformats.html.
18. ↑ Bonshor, Gavin. "AMD Announces The Ryzen AI 300 Series For Mobile: Zen 5 With RDNA 3.5, and XDNA2 NPU With 50 TOPS". https://www.anandtech.com/show/21419/amd-announces-the-ryzen-ai-300-series-for-mobile-zen-5-with-rdna-35-and-xdna2-npu-with-50-tops.
19. ↑ "AMD Extends AI and High-Performance Leadership in Data Center and PCs with New AMD Instinct, Ryzen and EPYC Processors at Computex 2024" (in en). 2024-06-02. https://ir.amd.com/news-events/press-releases/detail/1200/amd-extends-ai-and-high-performance-leadership-in-data.
20. ↑ "BFP16 (Block floating point) Quantization — AMD Quark 0.10 documentation". https://quark.docs.amd.com/latest/pytorch/tutorial_bfp16.html.
21. ↑ "Intel Advanced Vector Extensions 10.2 (Intel AVX10.2) Architecture Specification". 16 Oct 2024. p. 39. https://www.intel.com/content/www/us/en/content-details/836199/intel-advanced-vector-extensions-10-2-intel-avx10-2-architecture-specification.html.
22. ↑ Hao, Zhiwei; Guo, Jianyuan; Shen, Li; Luo, Yong; Hu, Han; Wang, Guoxia; Yu, Dianhai; Wen, Yonggang; Tao, Dacheng (2025). "Low-Precision Training of Large Language Models: Methods, Challenges, and Opportunities". arXiv:2505.01043v1 [cs.LG].
23. ↑ "Per-Tensor and Per-Block Scaling Strategies for Effective FP8 Training". 1 July 2025. https://developer.nvidia.com/blog/per-tensor-and-per-block-scaling-strategies-for-effective-fp8-training/.
24. ↑ Kim, Jiwoo; Lee, Joonhyung; Park, Gunho; Kim, Byeongwook; Se Jung Kwon; Lee, Dongsoo; Lee, Youngjoo (2025). "An Investigation of FP8 Across Accelerators for LLM Inference". arXiv:2502.01070v1 [cs.LG].
25. ↑ "Two Level Quantization Formats (MX4, MX6, MX9: shared Microexponents) — AMD Quark 0.10 documentation". https://quark.docs.amd.com/latest/pytorch/adv_two_level.html.
26. ↑ "AMD Versal™ AI Edge Series Gen 2". https://www.amd.com/en/products/adaptive-socs-and-fpgas/versal/gen2/ai-edge-series.html#product-table.

## Further reading

* "FFT/IFFT Block Floating Point Scaling". San Jose, CA, USA: Altera Corporation. October 2005. https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an404.pdf.

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