General-purpose computing on graphics processing units

Short description: Use of a GPU for computations typically assigned to CPUs

General-purpose computing on graphics processing units (GPGPU, or less often GPGP) is the use of a graphics processing unit (GPU), which typically handles computation only for computer graphics, to perform computation in applications traditionally handled by the central processing unit (CPU).[1][2][3][4] The use of multiple video cards in one computer, or large numbers of graphics chips, further parallelizes the already parallel nature of graphics processing.[5]

Essentially, a GPGPU pipeline is a kind of parallel processing between one or more GPUs and CPUs that analyzes data as if it were in image or other graphic form. While GPUs operate at lower frequencies, they typically have many times the number of cores. Thus, GPUs can process far more pictures and graphical data per second than a traditional CPU. Migrating data into graphical form and then using the GPU to scan and analyze it can create a large speedup.

GPGPU pipelines were developed at the beginning of the 21st century for graphics processing (e.g. for better shaders). These pipelines were found to fit scientific computing needs well, and have since been developed in this direction.

## Contents

* 1 History
* 2 Implementations
* 2.1 Mobile computers
* 3 Hardware support
* 3.1 Integer numbers
* 3.2 Floating-point numbers
* 3.3 Vectorization
* 4 GPU vs. CPU
* 4.1 Caches
* 4.2 Register file
* 4.3 Energy efficiency
* 5 Stream processing
* 5.1 GPU programming concepts
* 5.1.1 Computational resources
* 5.1.2 Textures as stream
* 5.1.3 Kernels
* 5.1.4 Flow control
* 5.2 GPU methods
* 5.2.1 Map
* 5.2.2 Reduce
* 5.2.3 Stream filtering
* 5.2.4 Scan
* 5.2.5 Scatter
* 5.2.6 Gather
* 5.2.7 Sort
* 5.2.8 Search
* 5.2.9 Data structures
* 6 Applications
* 6.1 Bioinformatics
* 6.1.1 Molecular dynamics
* 7 See also
* 8 References

## History

In principle, any arbitrary boolean function, including addition, multiplication, and other mathematical functions, can be built up from a functionally complete set of logic operators. In 1987, Conway's Game of Life became one of the first examples of general-purpose computing using an early stream processor called a blitter to invoke a special sequence of logical operations on bit vectors.[6]

General-purpose computing on GPUs became more practical and popular after about 2001, with the advent of both programmable shaders and floating point support on graphics processors. Notably, problems involving matrices and/or vectors - especially two-, three-, or four-dimensional vectors - were easy to translate to a GPU, which acts with native speed and support on those types. A significant milestone for GPGPU was the year 2003 when two research groups independently discovered GPU-based approaches for the solution of general linear algebra problems on GPUs that ran faster than on CPUs.[7][8] These early efforts to use GPUs as general-purpose processors required reformulating computational problems in terms of graphics primitives, as supported by the two major APIs for graphics processors, OpenGL and DirectX. This cumbersome translation was obviated by the advent of general-purpose programming languages and APIs such as Sh/RapidMind, Brook and Accelerator.[9][10][11]

These were followed by Nvidia's CUDA, which allowed programmers to ignore the underlying graphical concepts in favor of more common high-performance computing concepts.[12] Newer, hardware-vendor-independent offerings include Microsoft's DirectCompute and Apple/Khronos Group's OpenCL.[12] This means that modern GPGPU pipelines can leverage the speed of a GPU without requiring full and explicit conversion of the data to a graphical form.

Mark Harris, the founder of GPGPU.org, coined the term GPGPU.

## Implementations

Any language that allows the code running on the CPU to poll a GPU shader for return values, can create a GPGPU framework.
Programming standards for parallel computing include OpenCL (vendor-independent), OpenACC, OpenMP and OpenHMPP.

(As of 2016), OpenCL is the dominant open general-purpose GPU computing language, and is an open standard defined by the Khronos Group. OpenCL provides a cross-platform GPGPU platform that additionally supports data parallel compute on CPUs. OpenCL is actively supported on Intel, AMD, Nvidia, and ARM platforms. The Khronos Group has also standardised and implemented SYCL, a higher-level programming model for OpenCL as a single-source domain specific embedded language based on pure C++11.

The dominant proprietary framework is Nvidia CUDA.[13] Nvidia launched CUDA in 2006, a software development kit (SDK) and application programming interface (API) that allows using the programming language C to code algorithms for execution on GeForce 8 series and later GPUs.

ROCm, launched in 2016, is AMD's open-source response to CUDA. It is, as of 2022, on par with CUDA with regards to features, and still lacking in consumer support.

The Xcelerit SDK,[14] created by Xcelerit,[15] is designed to accelerate large existing C++ or C# code-bases on GPUs with minimal effort. It provides a simplified programming model, automates parallelisation, manages devices and memory, and compiles to CUDA binaries. Additionally, multi-core CPUs and other accelerators can be targeted from the same source code.

OpenVIDIA was developed at University of Toronto between 2003–2005,[16] in collaboration with Nvidia.

Altimesh Hybridizer created by Altimesh compiles Common Intermediate Language to CUDA binaries.[17][18] It supports generics and virtual functions.[19] Debugging and profiling is integrated with Visual Studio and Nsight.[20] It is available as a Visual Studio extension on Visual Studio Marketplace.

Microsoft introduced the DirectCompute GPU computing API, released with the DirectX 11 API.

Alea GPU[21] created by QuantAlea[22] introduces native GPU computing capabilities for the Microsoft .NET language F#[23] and C#. Alea GPU also provides a simplified GPU programming model based on GPU parallel-for and parallel aggregate using delegates and automatic memory management.[24]

MATLAB supports GPGPU acceleration using the Parallel Computing Toolbox and MATLAB Distributed Computing Server,[25] and third-party packages like Jacket.

GPGPU processing is also used to simulate Newtonian physics by physics engines,[26] and commercial implementations include Havok Physics, FX and PhysX, both of which are typically used for computer and video games.

C++ Accelerated Massive Parallelism (C++ AMP) is a library that accelerates execution of C++ code by exploiting the data-parallel hardware on GPUs.

### Mobile computers

Due to a trend of increasing power of mobile GPUs, general-purpose programming became available also on the mobile devices running major mobile operating systems.

Google Android 4.2 enabled running RenderScript code on the mobile device GPU.[27] Apple introduced the proprietary Metal API for iOS applications, able to execute arbitrary code through Apple's GPU compute shaders.

## Hardware support

Computer video cards are produced by various vendors, such as Nvidia, AMD. Cards from such vendors differ on implementing data-format support, such as integer and floating-point formats (32-bit and 64-bit). Microsoft introduced a Shader Model standard, to help rank the various features of graphic cards into a simple Shader Model version number (1.0, 2.0, 3.0, etc.).

### Integer numbers

Pre-DirectX 9 video cards only supported paletted or integer color types. Various formats are available, each containing a red element, a green element, and a blue element. Sometimes another alpha value is added, to be used for transparency. Common formats are:

* 8 bits per pixel – Sometimes palette mode, where each value is an index in a table with the real color value specified in one of the other formats. Sometimes three bits for red, three bits for green, and two bits for blue.
* 16 bits per pixel – Usually the bits are allocated as five bits for red, six bits for green, and five bits for blue.
* 24 bits per pixel – There are eight bits for each of red, green, and blue.
* 32 bits per pixel – There are eight bits for each of red, green, blue, and alpha.

### Floating-point numbers

For early fixed-function or limited programmability graphics (i.e., up to and including DirectX 8.1-compliant GPUs) this was sufficient because this is also the representation used in displays. It is important to note that this representation does have certain limitations. Given sufficient graphics processing power even graphics programmers would like to use better formats, such as floating point data formats, to obtain effects such as high-dynamic-range imaging. Many GPGPU applications require floating point accuracy, which came with video cards conforming to the DirectX 9 specification.

DirectX 9 Shader Model 2.x suggested the support of two precision types: full and partial precision. Full precision support could either be FP32 or FP24 (floating point 32- or 24-bit per component) or greater, while partial precision was FP16. ATI's Radeon R300 series of GPUs supported FP24 precision only in the programmable fragment pipeline (although FP32 was supported in the vertex processors) while Nvidia's NV30 series supported both FP16 and FP32; other vendors such as S3 Graphics and XGI supported a mixture of formats up to FP24.

The implementations of floating point on Nvidia GPUs are mostly IEEE compliant; however, this is not true across all vendors.[28] This has implications for correctness which are considered important to some scientific applications. While 64-bit floating point values (double precision float) are commonly available on CPUs, these are not universally supported on GPUs. Some GPU architectures sacrifice IEEE compliance, while others lack double-precision. Efforts have occurred to emulate double-precision floating point values on GPUs; however, the speed tradeoff negates any benefit to offloading the computing onto the GPU in the first place.[29]

### Vectorization

Most operations on the GPU operate in a vectorized fashion: one operation can be performed on up to four values at once. For example, if one color ⟨R1, G1, B1⟩ is to be modulated by another color ⟨R2, G2, B2⟩, the GPU can produce the resulting color ⟨R1*R2, G1*G2, B1*B2⟩ in one operation. This functionality is useful in graphics because almost every basic data type is a vector (either 2-, 3-, or 4-dimensional). Examples include vertices, colors, normal vectors, and texture coordinates. Many other applications can put this to good use, and because of their higher performance, vector instructions, termed single instruction, multiple data (SIMD), have long been available on CPUs.

## GPU vs. CPU

Originally, data was simply passed one-way from a central processing unit (CPU) to a graphics processing unit (GPU), then to a display device. As time progressed, however, it became valuable for GPUs to store at first simple, then complex structures of data to be passed back to the CPU that analyzed an image, or a set of scientific-data represented as a 2D or 3D format that a video card can understand. Because the GPU has access to every draw operation, it can analyze data in these forms quickly, whereas a CPU must poll every pixel or data element much more slowly, as the speed of access between a CPU and its larger pool of random-access memory (or in an even worse case, a hard drive) is slower than GPUs and video cards, which typically contain smaller amounts of more expensive memory that is much faster to access. Transferring the portion of the data set to be actively analyzed to that GPU memory in the form of textures or other easily readable GPU forms results in speed increase. The distinguishing feature of a GPGPU design is the ability to transfer information bidirectionally back from the GPU to the CPU; generally the data throughput in both directions is ideally high, resulting in a multiplier effect on the speed of a specific high-use algorithm. GPGPU pipelines may improve efficiency on especially large data sets and/or data containing 2D or 3D imagery. It is used in complex graphics pipelines as well as scientific computing; more so in fields with large data sets like genome mapping, or where two- or three-dimensional analysis is useful - especially at present biomolecule analysis, protein study, and other complex organic chemistry. Such pipelines can also vastly improve efficiency in image processing and computer vision, among other fields; as well as parallel processing generally. Some very heavily optimized pipelines have yielded speed increases of several hundred times the original CPU-based pipeline on one high-use task.

A simple example would be a GPU program that collects data about average lighting values as it renders some view from either a camera or a computer graphics program back to the main program on the CPU, so that the CPU can then make adjustments to the overall screen view. A more advanced example might use edge detection to return both numerical information and a processed image representing outlines to a computer vision program controlling, say, a mobile robot. Because the GPU has fast and local hardware access to every pixel or other picture element in an image, it can analyze and average it (for the first example) or apply a Sobel edge filter or other convolution filter (for the second) with much greater speed than a CPU, which typically must access slower random-access memory copies of the graphic in question.

GPGPU is fundamentally a software concept, not a hardware concept; it is a type of algorithm, not a piece of equipment. Specialized equipment designs may, however, even further enhance the efficiency of GPGPU pipelines, which traditionally perform relatively few algorithms on very large amounts of data. Massively parallelized, gigantic-data-level tasks thus may be parallelized even further via specialized setups such as rack computing (many similar, highly tailored machines built into a rack), which adds a third layer - many computing units each using many CPUs to correspond to many GPUs. Some Bitcoin "miners" used such setups for high-quantity processing.

### Caches

Historically, CPUs have used hardware-managed caches, but the earlier GPUs only provided software-managed local memories. However, as GPUs are being increasingly used for general-purpose applications, state-of-the-art GPUs are being designed with hardware-managed multi-level caches which have helped the GPUs to move towards mainstream computing. For example, GeForce 200 series GT200 architecture GPUs did not feature an L2 cache, the Fermi GPU has 768 KiB last-level cache, the Kepler GPU has 1.5 MiB last-level cache,[30] the Maxwell GPU has 2 MiB last-level cache, and the Pascal GPU has 4 MiB last-level cache.

### Register file

GPUs have very large register files, which allow them to reduce context-switching latency. Register file size is also increasing over different GPU generations, e.g., the total register file size on Maxwell (GM200), Pascal and Volta GPUs are 6 MiB, 14 MiB and 20 MiB, respectively.[31][32] By comparison, the size of a register file on CPUs is small, typically tens or hundreds of kilobytes.

### Energy efficiency

The high performance of GPUs comes at the cost of high power consumption, which under full load is in fact as much power as the rest of the PC system combined.[33] The maximum power consumption of the Pascal series GPU (Tesla P100) was specified to be 250W.[34]

## Stream processing

Main page: Stream processing

GPUs are designed specifically for graphics and thus are very restrictive in operations and programming. Due to their design, GPUs are only effective for problems that can be solved using stream processing and the hardware can only be used in certain ways.

The following discussion referring to vertices, fragments and textures concerns mainly the legacy model of GPGPU programming, where graphics APIs (OpenGL or DirectX) were used to perform general-purpose computation. With the introduction of the CUDA (Nvidia, 2007) and OpenCL (vendor-independent, 2008) general-purpose computing APIs, in new GPGPU codes it is no longer necessary to map the computation to graphics primitives. The stream processing nature of GPUs remains valid regardless of the APIs used. (See e.g.,[35])

GPUs can only process independent vertices and fragments, but can process many of them in parallel. This is especially effective when the programmer wants to process many vertices or fragments in the same way. In this sense, GPUs are stream processors - processors that can operate in parallel by running one kernel on many records in a stream at once.

A stream is simply a set of records that require similar computation. Streams provide data parallelism. Kernels are the functions that are applied to each element in the stream. In the GPUs, vertices and fragments are the elements in streams and vertex and fragment shaders are the kernels to be run on them. For each element we can only read from the input, perform operations on it, and write to the output. It is permissible to have multiple inputs and multiple outputs, but never a piece of memory that is both readable and writable.

Arithmetic intensity is defined as the number of operations performed per word of memory transferred. It is important for GPGPU applications to have high arithmetic intensity else the memory access latency will limit computational speedup.[36]

Ideal GPGPU applications have large data sets, high parallelism, and minimal dependency between data elements.

### GPU programming concepts

#### Computational resources

There are a variety of computational resources available on the GPU:

* Programmable processors – vertex, primitive, fragment and mainly compute pipelines allow programmer to perform kernel on streams of data
* Rasterizer – creates fragments and interpolates per-vertex constants such as texture coordinates and color
* Texture unit – read-only memory interface
* Framebuffer – write-only memory interface

In fact, a program can substitute a write only texture for output instead of the framebuffer. This is done either through Render to Texture (RTT), Render-To-Backbuffer-Copy-To-Texture (RTBCTT), or the more recent stream-out.

#### Textures as stream

The most common form for a stream to take in GPGPU is a 2D grid because this fits naturally with the rendering model built into GPUs. Many computations naturally map into grids: matrix algebra, image processing, physically based simulation, and so on.

Since textures are used as memory, texture lookups are then used as memory reads. Certain operations can be done automatically by the GPU because of this.

#### Kernels

Compute kernels can be thought of as the body of loops. For example, a programmer operating on a grid on the CPU might have code that looks like this:

// Input and output grids have 10000 x 10000 or 100 million elements.

void transform_10k_by_10k_grid(float in[10000][10000], float out[10000][10000])

for (int x = 0; x < 10000; x++) {
for (int y = 0; y < 10000; y++) {
// The next line is executed 100 million times
out[x][y] = do_some_hard_work(in[x][y]);

On the GPU, the programmer only specifies the body of the loop as the kernel and what data to loop over by invoking geometry processing.

#### Flow control

In sequential code it is possible to control the flow of the program using if-then-else statements and various forms of loops. Such flow control structures have only recently been added to GPUs.[37] Conditional writes could be performed using a properly crafted series of arithmetic/bit operations, but looping and conditional branching were not possible.

Recent GPUs allow branching, but usually with a performance penalty. Branching should generally be avoided in inner loops, whether in CPU or GPU code, and various methods, such as static branch resolution, pre-computation, predication, loop splitting,[38] and Z-cull[39] can be used to achieve branching when hardware support does not exist.

### GPU methods

#### Map

Main page: Map (parallel pattern)

The map operation simply applies the given function (the kernel) to every element in the stream. A simple example is multiplying each value in the stream by a constant (increasing the brightness of an image). The map operation is simple to implement on the GPU. The programmer generates a fragment for each pixel on screen and applies a fragment program to each one. The result stream of the same size is stored in the output buffer.

#### Reduce

Main page: Fold (higher-order function)

Some computations require calculating a smaller stream (possibly a stream of only one element) from a larger stream. This is called a reduction of the stream. Generally, a reduction can be performed in multiple steps. The results from the prior step are used as the input for the current step and the range over which the operation is applied is reduced until only one stream element remains.

#### Stream filtering

Stream filtering is essentially a non-uniform reduction. Filtering involves removing items from the stream based on some criteria.

#### Scan

The scan operation, also termed parallel prefix sum, takes in a vector (stream) of data elements and an (arbitrary) associative binary function '+' with an identity element 'i'. If the input is [a0, a1, a2, a3, ...], an exclusive scan produces the output [i, a0, a0 + a1, a0 + a1 + a2, ...], while an inclusive scan produces the output [a0, a0 + a1, a0 + a1 + a2, a0 + a1 + a2 + a3, ...] and does not require an identity to exist. While at first glance the operation may seem inherently serial, efficient parallel scan algorithms are possible and have been implemented on graphics processing units. The scan operation has uses in e.g., quicksort and sparse matrix-vector multiplication.[35][40][41][42]

#### Scatter

The scatter operation is most naturally defined on the vertex processor. The vertex processor is able to adjust the position of the vertex, which allows the programmer to control where information is deposited on the grid. Other extensions are also possible, such as controlling how large an area the vertex affects.

The fragment processor cannot perform a direct scatter operation because the location of each fragment on the grid is fixed at the time of the fragment's creation and cannot be altered by the programmer. However, a logical scatter operation may sometimes be recast or implemented with another gather step. A scatter implementation would first emit both an output value and an output address. An immediately following gather operation uses address comparisons to see whether the output value maps to the current output slot.

In dedicated compute kernels, scatter can be performed by indexed writes.

#### Gather

Gather is the reverse of scatter. After scatter reorders elements according to a map, gather can restore the order of the elements according to the map scatter used. In dedicated compute kernels, gather may be performed by indexed reads. In other shaders, it is performed with texture-lookups.

#### Sort

The sort operation transforms an unordered set of elements into an ordered set of elements. The most common implementation on GPUs is using radix sort for integer and floating point data and coarse-grained merge sort and fine-grained sorting networks for general comparable data.[43][44]

#### Search

The search operation allows the programmer to find a given element within the stream, or possibly find neighbors of a specified element. The GPU is not used to speed up the search for an individual element, but instead is used to run multiple searches in parallel. Mostly the search method used is binary search on sorted elements.

#### Data structures

A variety of data structures can be represented on the GPU:

* Dense arrays
* Sparse matrices (sparse array)  - static or dynamic
* Adaptive structures (union type)

## Applications

The following are some of the areas where GPUs have been used for general purpose computing:

* Automatic parallelization[45][46][47]
* Physical based simulation and physics engines[26] (usually based on Newtonian physics models)
* Conway's Game of Life, cloth simulation, fluid incompressible flow by solution of Euler equations (fluid dynamics)[48] or Navier–Stokes equations[49]
* Statistical physics
* Ising model[50]
* Lattice gauge theory
* Segmentation - 2D and 3D[51]
* Level set methods
* CT reconstruction[52]
* Fast Fourier transform[53]
* GPU learning - machine learning and data mining computations, e.g., with software BIDMach
* k-nearest neighbor algorithm[54]
* Fuzzy logic[55]
* Tone mapping
* Audio signal processing[56]
* Audio and sound effects processing, to use a GPU for digital signal processing (DSP)
* Analog signal processing
* Speech processing
* Digital image processing
* Video processing[57]
* Hardware accelerated video decoding and post-processing
* Motion compensation (mo comp)
* Inverse discrete cosine transform (iDCT)
* Variable-length decoding (VLD), Huffman coding
* Inverse quantization (IQ (not to be confused by Intelligence Quotient))
* In-loop deblocking
* Bitstream processing (CAVLC/CABAC) using special purpose hardware for this task because this is a serial task not suitable for regular GPGPU computation
* Deinterlacing
* Spatial-temporal deinterlacing
* Noise reduction
* Edge enhancement
* Color correction
* Hardware accelerated video encoding and pre-processing
* Global illumination - ray tracing, photon mapping, radiosity among others, subsurface scattering
* Geometric computing - constructive solid geometry, distance fields, collision detection, transparency computation, shadow generation
* Scientific computing
* Monte Carlo simulation of light propagation[58]
* Weather forecasting
* Climate research
* Molecular modeling on GPU[59]
* Quantum mechanical physics
* Astrophysics[60]
* Bioinformatics[61][62]
* Computational finance
* Medical imaging
* Clinical decision support system (CDSS)[63]
* Computer vision[64]
* Digital signal processing / signal processing
* Control engineering
* Operations research[65][66][67]
* Implementations of: the GPU Tabu Search algorithm solving the Resource Constrained Project Scheduling problem is freely available on GitHub;[68] the GPU algorithm solving the Nurse Rerostering problem is freely available on GitHub.[69]
* Neural networks
* Database operations[70]
* Computational Fluid Dynamics especially using Lattice Boltzmann methods
* Cryptography[71] and cryptanalysis
* Performance modeling: computationally intensive tasks on GPU[59]
* Implementations of: MD6, Advanced Encryption Standard (AES),[72][73] Data Encryption Standard (DES), RSA,[74] elliptic curve cryptography (ECC)
* Password cracking[75][76]
* Cryptocurrency transactions processing ("mining") (Bitcoin mining)
* Electronic design automation[77][78]
* Antivirus software[79][80]
* Intrusion detection[81][82]
* Increase computing power for distributed computing projects like SETI@home, Einstein@home

### Bioinformatics

GPGPU usage in Bioinformatics:[59][83]

Application  | Description  | Supported features  | Expected speed-up†  | GPU‡  | Multi-GPU support  | Release status

|
|
|
|
|
|

BarraCUDA | DNA, including epigenetics, sequence mapping software[84] | Alignment of short sequencing reads | 6–10x | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 0.7.107f
CUDASW++ | Open source software for Smith-Waterman protein database searches on GPUs | Parallel search of Smith-Waterman database | 10–50x | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 2.0.8
CUSHAW | Parallelized short read aligner | Parallel, accurate long read aligner - gapped alignments to large genomes | 10x | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 1.0.40
GPU-BLAST | Local search with fast k-tuple heuristic | Protein alignment according to blastp, multi CPU threads | 3–4x | T 2075, 2090, K10, K20, K20X | Single only | Available now, version 2.2.26
GPU-HMMER | Parallelized local and global search with profile hidden Markov models | Parallel local and global search of hidden Markov models | 60–100x | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 2.3.2
mCUDA-MEME | Ultrafast scalable motif discovery algorithm based on MEME | Scalable motif discovery algorithm based on MEME | 4–10x | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 3.0.12
SeqNFind | A GPU accelerated sequence analysis toolset | Reference assembly, blast, Smith–Waterman, hmm, de novo assembly | 400x | T 2075, 2090, K10, K20, K20X | Yes | Available now
UGENE | Opensource Smith–Waterman for SSE/CUDA, suffix array based repeats finder and dotplot | Fast short read alignment | 6–8x | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 1.11
WideLM | Fits numerous linear models to a fixed design and response | Parallel linear regression on multiple similarly-shaped models | 150x | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 0.1-1

#### Molecular dynamics

Further information: Physics:Molecular modeling on GPUs and Physics:Comparison of software for molecular mechanics modeling

Application  | Description  | Supported features  | Expected speed-up†  | GPU‡  | Multi-GPU support  | Release status

|
|
|
|
|
|

Abalone | Models molecular dynamics of biopolymers for simulations of proteins, DNA and ligands | Explicit and implicit solvent, hybrid Monte Carlo | 4–120x | T 2075, 2090, K10, K20, K20X | Single only | Available now, version 1.8.88
ACEMD | GPU simulation of molecular mechanics force fields, implicit and explicit solvent | Written for use on GPUs | 160 ns/day GPU version only | T 2075, 2090, K10, K20, K20X | Yes | Available now
AMBER | Suite of programs to simulate molecular dynamics on biomolecule | PMEMD: explicit and implicit solvent | 89.44 ns/day JAC NVE | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 12 + bugfix9
DL-POLY | Simulate macromolecules, polymers, ionic systems, etc. on a distributed memory parallel computer | Two-body forces, link-cell pairs, Ewald SPME forces, Shake VV | 4x | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 4.0 source only
CHARMM | MD package to simulate molecular dynamics on biomolecule. | Implicit (5x), explicit (2x) solvent via OpenMM | TBD | T 2075, 2090, K10, K20, K20X | Yes | In development Q4/12
GROMACS | Simulate biochemical molecules with complex bond interactions | Implicit (5x), explicit (2x) solvent | 165 ns/Day DHFR | T 2075, 2090, K10, K20, K20X | Single only | Available now, version 4.6 in Q4/12
HOOMD-Blue | Particle dynamics package written grounds up for GPUs | Written for GPUs | 2x | T 2075, 2090, K10, K20, K20X | Yes | Available now
LAMMPS | Classical molecular dynamics package | Lennard-Jones, Morse, Buckingham, CHARMM, tabulated, course grain SDK, anisotropic Gay-Bern, RE-squared, "hybrid" combinations | 3–18x | T 2075, 2090, K10, K20, K20X | Yes | Available now
NAMD | Designed for high-performance simulation of large molecular systems | 100M atom capable | 6.44 ns/days STMV 585x 2050s | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 2.9
OpenMM | Library and application for molecular dynamics for HPC with GPUs | Implicit and explicit solvent, custom forces | Implicit: 127–213 ns/day; Explicit: 18–55 ns/day DHFR | T 2075, 2090, K10, K20, K20X | Yes | Available now, version 4.1.1

† Expected speedups are highly dependent on system configuration. GPU performance compared against multi-core x86 CPU socket. GPU performance benchmarked on GPU supported features and may be a kernel to kernel performance comparison. For details on configuration used, view application website. Speedups as per Nvidia in-house testing or ISV's documentation.

‡ Q=Quadro GPU, T=Tesla GPU. Nvidia recommended GPUs for this application. Check with developer or ISV to obtain certification information.

## See also

* Fastra II
* Physics engine
* Advanced Simulation Library
* Physics processing unit (PPU)
* Close to Metal
* Audio processing unit
* Larrabee (microarchitecture)
* AI accelerator
* Deep learning processor (DLP)

## References

1. ↑ Fung, et al., "Mediated Reality Using Computer Graphics Hardware for Computer Vision" , Proceedings of the International Symposium on Wearable Computing 2002 (ISWC2002), Seattle, Washington, USA, 7–10 October 2002, pp. 83–89.
2. ↑ An EyeTap video-based featureless projective motion estimation assisted by gyroscopic tracking for wearable computer mediated reality, ACM Personal and Ubiquitous Computing published by Springer Verlag, Vol.7, Iss. 3, 2003.
3. ↑ "Computer Vision Signal Processing on Graphics Processing Units", Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004) : Montreal, Quebec, Canada, 17–21 May 2004, pp. V-93 – V-96
4. ↑ Chitty, D. M. (2007, July). A data parallel approach to genetic programming using programmable graphics hardware . In Proceedings of the 9th annual conference on Genetic and evolutionary computation (pp. 1566-1573). ACM.
5. ↑ "Using Multiple Graphics Cards as a General Purpose Parallel Computer: Applications to Computer Vision", Proceedings of the 17th International Conference on Pattern Recognition (ICPR2004) , Cambridge, United Kingdom, 23–26 August 2004, volume 1, pages 805–808.
6. ↑ Hull, Gerald (December 1987). "LIFE". Amazing Computing 2 (12): 81–84. https://archive.org/stream/amazing-computing-magazine-1987-12/Amazing_Computing_Vol_02_12_1987_Dec#page/n81/mode/2up.
7. ↑ Krüger, Jens; Westermann, Rüdiger (July 2003). "Linear algebra operators for GPU implementation of numerical algorithms" (in en). ACM Transactions on Graphics 22 (3): 908–916. doi:10.1145/882262.882363. ISSN 0730-0301. https://dl.acm.org/doi/10.1145/882262.882363.
8. ↑ Bolz, Jeff; Farmer, Ian; Grinspun, Eitan; Schröder, Peter (July 2003). "Sparse matrix solvers on the GPU: conjugate gradients and multigrid" (in en). ACM Transactions on Graphics 22 (3): 917–924. doi:10.1145/882262.882364. ISSN 0730-0301. https://dl.acm.org/doi/10.1145/882262.882364.
9. ↑ Tarditi, David; Puri, Sidd; Oglesby, Jose (2006). "Accelerator: using data parallelism to program GPUs for general-purpose uses". ACM SIGARCH Computer Architecture News 34 (5). doi:10.1145/1168919.1168898. https://www.cs.cmu.edu/afs/cs/academic/class/15740-f07/public/discussion-papers/26-tarditi-asplos06.pdf.
10. ↑ Che, Shuai; Boyer, Michael; Meng, Jiayuan; Tarjan, D.; Sheaffer, Jeremy W.; Skadron, Kevin (2008). "A performance study of general-purpose applications on graphics processors using CUDA". J. Parallel and Distributed Computing 68 (10): 1370–1380. doi:10.1016/j.jpdc.2008.05.014.
11. ↑ Glaser, J.; Nguyen, T. D.; Anderson, J. A.; Lui, P.; Spiga, F.; Millan, J. A.; Morse, D. C.; Glotzer, S. C. (2015). "Strong scaling of general-purpose molecular dynamics simulations on GPUs". Computer Physics Communications 192: 97–107. doi:10.1016/j.cpc.2015.02.028. Bibcode: 2015CoPhC.192...97G.
12. ↑ 12.0 12.1 Du, Peng; Weber, Rick; Luszczek, Piotr; Tomov, Stanimire; Peterson, Gregory; Dongarra, Jack (2012). "From CUDA to OpenCL: Towards a performance-portable solution for multi-platform GPU programming". Parallel Computing 38 (8): 391–407. doi:10.1016/j.parco.2011.10.002.
13. ↑ "OpenCL Gains Ground on CUDA". 2012-02-28. http://www.hpcwire.com/hpcwire/2012-02-28/opencl_gains_ground_on_cuda.html. "As the two major programming frameworks for GPU computing, OpenCL and CUDA have been competing for mindshare in the developer community for the past few years."
14. ↑ "Xcelerit SDK". 2015-10-26. https://www.xcelerit.com/products/xcelerit-sdk/.
15. ↑ "Home page". https://www.xcelerit.com/.
16. ↑ James Fung, Steve Mann, Chris Aimone, "OpenVIDIA: Parallel GPU Computer Vision", Proceedings of the ACM Multimedia 2005, Singapore, 6–11 November 2005, pages 849–852
17. ↑ "Hybridizer". http://www.altimesh.com/hybridizer-essentials/.
18. ↑ "Home page". http://www.altimesh.com/.
19. ↑ "Hybridizer generics and inheritance". 2017-07-27. http://www.altimesh.com/generics-and-inheritance/.
20. ↑ "Debugging and Profiling with Hybridizer". 2017-06-05. http://www.altimesh.com/debugging-and-profiling/.
21. ↑ "Introduction". http://www.aleagpu.com/release/3_0_2/doc/.
22. ↑ "Home page". http://www.quantalea.com/.
23. ↑ "Use F# for GPU Programming". F# Software Foundation. http://fsharp.org/use/gpu/.
24. ↑ "Alea GPU Features". http://www.quantalea.com/features.
25. ↑ "MATLAB Adds GPGPU Support". 20 September 2010. http://www.hpcwire.com/features/MATLAB-Adds-GPGPU-Support-103307084.html.
26. ↑ 26.0 26.1 Joselli, Mark, et al. "A new physics engine with automatic process distribution between CPU-GPU." Proceedings of the 2008 ACM SIGGRAPH symposium on Video games. ACM, 2008.
27. ↑ "Android 4.2 APIs - Android Developers". http://developer.android.com/about/versions/android-4.2.html.
28. ↑ Mapping computational concepts to GPUs: Mark Harris. Mapping computational concepts to GPUs. In ACM SIGGRAPH 2005 Courses (Los Angeles, California, 31 July - 4 August 2005). J. Fujii, Ed. SIGGRAPH '05. ACM Press, New York, NY, 50.
29. ↑ Double precision on GPUs (Proceedings of ASIM 2005) : Dominik Goddeke, Robert Strzodka, and Stefan Turek. Accelerating Double Precision (FEM) Simulations with (GPUs). Proceedings of ASIM 2005 - 18th Symposium on Simulation Technique, 2005.
30. ↑ "Nvidia-Kepler-GK110-Architecture-Whitepaper". http://www.nvidia.com/content/PDF/kepler/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf.
31. ↑ "Inside Pascal: Nvidia’s Newest Computing Platform "
32. ↑ "Inside Volta: The World’s Most Advanced Data Center GPU "
33. ↑ "https://www.tomshardware.com/reviews/geforce-radeon-power,2122.html How Much Power Does Your Graphics Card Need?"
34. ↑ "https://images.nvidia.com/content/tesla/pdf/nvidia-tesla-p100-PCIe-datasheet.pdf Nvidia Tesla P100 GPU Accelerator "
35. ↑ 35.0 35.1 "D. Göddeke, 2010. Fast and Accurate Finite-Element Multigrid Solvers for PDE Simulations on GPU Clusters. Ph.D. dissertation, Technischen Universität Dortmund.". http://d-nb.info/100545535X/34.
36. ↑ Asanovic, K.; Bodik, R.; Demmel, J.; Keaveny, T.; Keutzer, K.; Kubiatowicz, J.; Morgan, N.; Patterson, D. et al. (2009). "A view of the parallel computing landscape". Commun. ACM 52 (10): 56–67. doi:10.1145/1562764.1562783.
37. ↑ "GPU Gems – Chapter 34, GPU Flow-Control Idioms". https://developer.nvidia.com/gpugems/GPUGems2/gpugems2_chapter34.html.
38. ↑ Future Chips. "Tutorial on removing branches", 2011
39. ↑ GPGPU survey paper : John D. Owens, David Luebke, Naga Govindaraju, Mark Harris, Jens Krüger, Aaron E. Lefohn, and Tim Purcell. "A Survey of General-Purpose Computation on Graphics Hardware". Computer Graphics Forum, volume 26, number 1, 2007, pp. 80–113.
40. ↑ "S. Sengupta, M. Harris, Y. Zhang, J. D. Owens, 2007. Scan primitives for GPU computing. In T. Aila and M. Segal (eds.): Graphics Hardware (2007).". http://www.idav.ucdavis.edu/func/return_pdf?pub_id=915.
41. ↑ Blelloch, G. E. (1989). "Scans as primitive parallel operations". IEEE Transactions on Computers 38 (11): 1526–1538. doi:10.1109/12.42122. http://www.cs.berkeley.edu/~knight/cs267/papers/scan_primitive.pdf. Retrieved 16 December 2014.
42. ↑ "M. Harris, S. Sengupta, J. D. Owens. Parallel Prefix Sum (Scan) with CUDA. In Nvidia: GPU Gems 3, Chapter 39.". http://developer.nvidia.com/GPUGems3/gpugems3_ch39.html.
43. ↑ Merrill, Duane. Allocation-oriented Algorithm Design with Application to GPU Computing. Ph.D. dissertation, Department of Computer Science, University of Virginia. Dec. 2011.
44. ↑ Sean Baxter. Modern gpu , 2013.
45. ↑ Leung, Alan, Ondřej Lhoták, and Ghulam Lashari. "Automatic parallelization for graphics processing units." Proceedings of the 7th International Conference on Principles and Practice of Programming in Java. ACM, 2009.
46. ↑ Henriksen, Troels, Martin Elsman, and Cosmin E. Oancea. "Size slicing: a hybrid approach to size inference in futhark." Proceedings of the 3rd ACM SIGPLAN workshop on Functional high-performance computing. ACM, 2014.
47. ↑ Baskaran, Muthu Manikandan, et al. "A compiler framework for optimization of affine loop nests for GPGPUs." Proceedings of the 22nd annual international conference on Supercomputing. ACM, 2008.
48. ↑ "K. Crane, I. Llamas, S. Tariq, 2008. Real-Time Simulation and Rendering of 3D Fluids. In Nvidia: GPU Gems 3, Chapter 30.". http://developer.nvidia.com/GPUGems3/gpugems3_ch30.html.
49. ↑ "M. Harris, 2004. Fast Fluid Dynamics Simulation on the GPU. In Nvidia: GPU Gems, Chapter 38.". http://developer.nvidia.com/GPUGems/gpugems_ch38.html.
50. ↑ Block, Benjamin, Peter Virnau, and Tobias Preis. "Multi-GPU accelerated multi-spin Monte Carlo simulations of the 2D Ising model." Computer Physics Communications 181.9 (2010): 1549-1556.
51. ↑ Sun, Shanhui, Christian Bauer, and Reinhard Beichel. "Automated 3-D segmentation of lungs with lung cancer in CT data using a novel robust active shape model approach." IEEE transactions on medical imaging 31.2 (2011): 449-460.
52. ↑ Jimenez, Edward S., and Laurel J. Orr. "Rethinking the union of computed tomography reconstruction and GPGPU computing." Penetrating Radiation Systems and Applications XIV. Vol. 8854. International Society for Optics and Photonics, 2013.
53. ↑ Sørensen, Thomas Sangild, et al. "Accelerating the nonequispaced fast Fourier transform on commodity graphics hardware." IEEE Transactions on Medical Imaging 27.4 (2008): 538-547.
54. ↑ Fast k-nearest neighbor search using GPU. In Proceedings of the CVPR Workshop on Computer Vision on GPU, Anchorage, Alaska, USA, June 2008. V. Garcia and E. Debreuve and M. Barlaud.
55. ↑ M. Cococcioni, R. Grasso, M. Rixen, Rapid prototyping of high performance fuzzy computing applications using high level GPU programming for maritime operations support, in Proceedings of the 2011 IEEE Symposium on Computational Intelligence for Security and Defense Applications (CISDA), Paris, 11–15 April 2011
56. ↑ Whalen, Sean. "Audio and the graphics processing unit." Author report, University of California Davis 47 (2005): 51.
57. ↑ Wilson, Ron (3 September 2009). "DSP brings you a high-definition moon walk". EDN. http://www.edn.com/article/CA6685974.html. "Lowry is reportedly using Nvidia Tesla GPUs (graphics-processing units) programmed in the company's CUDA (Compute Unified Device Architecture) to implement the algorithms. Nvidia claims that the GPUs are approximately two orders of magnitude faster than CPU computations, reducing the processing time to less than one minute per frame."
58. ↑ Alerstam, E.; Svensson, T.; Andersson-Engels, S. (2008). "Parallel computing with graphics processing units for high speed Monte Carlo simulation of photon migration". Journal of Biomedical Optics 13 (6): 060504. doi:10.1117/1.3041496. PMID 19123645. Bibcode: 2008JBO....13f0504A. http://www.atomic.physics.lu.se/fileadmin/atomfysik/Biophotonics/Publications/Alerstam2008_JBOLetters.pdf.
59. ↑ 59.0 59.1 59.2 Hasan, Khondker S.; Chatterjee, Amlan; Radhakrishnan, Sridhar; Antonio, John K. (2014). "Performance Prediction Model and Analysis for Compute-Intensive Tasks on GPUs". Advanced Information Systems Engineering. Lecture Notes in Computer Science. 7908. pp. 612–617. doi:10.1007/978-3-662-44917-2_65. ISBN 978-3-642-38708-1. https://link.springer.com/content/pdf/10.1007/978-3-662-44917-2_65.pdf.
60. ↑ "Computational Physics with GPUs: Lund Observatory". http://www.astro.lu.se/compugpu2010/.
61. ↑ Schatz, Michael C; Trapnell, Cole; Delcher, Arthur L; Varshney, Amitabh (2007). "High-throughput sequence alignment using Graphics Processing Units". BMC Bioinformatics 8: 474. doi:10.1186/1471-2105-8-474. PMID 18070356.
62. ↑ Svetlin A. Manavski; Giorgio Valle (2008). "CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment". BMC Bioinformatics 9 (Suppl. 2): S10. doi:10.1186/1471-2105-9-s2-s10. PMID 18387198.
63. ↑ Olejnik, M; Steuwer, M; Gorlatch, S; Heider, D (15 November 2014). "gCUP: rapid GPU-based HIV-1 co-receptor usage prediction for next-generation sequencing.". Bioinformatics 30 (22): 3272–3. doi:10.1093/bioinformatics/btu535. PMID 25123901.
64. ↑ Wang, Guohui, et al. "Accelerating computer vision algorithms using OpenCL framework on the mobile GPU-a case study." 2013 IEEE International Conference on Acoustics, Speech and Signal Processing. IEEE, 2013.
65. ↑ GPU computing in OR Vincent Boyer, Didier El Baz. "Recent Advances on GPU Computing in Operations Research". Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International, on pages: 1778–1787
66. ↑ Bukata, Libor; Sucha, Premysl; Hanzalek, Zdenek (2014). "Solving the Resource Constrained Project Scheduling Problem using the parallel Tabu Search designed for the CUDA platform". Journal of Parallel and Distributed Computing 77: 58–68. doi:10.1016/j.jpdc.2014.11.005.
67. ↑ Bäumelt, Zdeněk; Dvořák, Jan; Šůcha, Přemysl; Hanzálek, Zdeněk (2016). "A Novel Approach for Nurse Rerostering based on a Parallel Algorithm". European Journal of Operational Research 251 (2): 624–639. doi:10.1016/j.ejor.2015.11.022.
68. ↑ CTU-IIG Czech Technical University in Prague, Industrial Informatics Group (2015).
69. ↑ NRRPGpu Czech Technical University in Prague, Industrial Informatics Group (2015).
70. ↑ Naju Mancheril. "GPU-based Sorting in PostgreSQL". School of Computer Science – Carnegie Mellon University. http://www.cs.cmu.edu/afs/cs.cmu.edu/Web/People/ngm/15-823/project/Final.pdf.
71. ↑ Manavski, Svetlin A. "CUDA compatible GPU as an efficient hardware accelerator for AES cryptography." 2007 IEEE International Conference on Signal Processing and Communications. IEEE, 2007.
72. ↑ Harrison, Owen; Waldron, John (2007). "AES Encryption Implementation and Analysis on Commodity Graphics Processing Units". Cryptographic Hardware and Embedded Systems - CHES 2007. Lecture Notes in Computer Science. 4727. pp. 209. doi:10.1007/978-3-540-74735-2_15. ISBN 978-3-540-74734-5.
73. ↑ AES and modes of operations on SM4.0 compliant GPUs. Owen Harrison, John Waldron, Practical Symmetric Key Cryptography on Modern Graphics Hardware. In proceedings of USENIX Security 2008.
74. ↑ Harrison, Owen; Waldron, John (2009). "Efficient Acceleration of Asymmetric Cryptography on Graphics Hardware". Progress in Cryptology – AFRICACRYPT 2009. Lecture Notes in Computer Science. 5580. pp. 350. doi:10.1007/978-3-642-02384-2_22. ISBN 978-3-642-02383-5.
75. ↑ "Teraflop Troubles: The Power of Graphics Processing Units May Threaten the World's Password Security System". Georgia Tech Research Institute. http://www.gtri.gatech.edu/casestudy/Teraflop-Troubles-Power-Graphics-Processing-Units-GPUs-Password-Security-System.
76. ↑ "Want to deter hackers? Make your password longer". NBC News. 19 August 2010. http://www.nbcnews.com/id/38771772.
77. ↑ Lerner, Larry (9 April 2009). "Viewpoint: Mass GPUs, not CPUs for EDA simulations". EE Times. http://www.eetimes.com/news/design/showArticle.jhtml?articleID=216500149.
78. ↑ "W2500 ADS Transient Convolution GT". http://www.keysight.com/en/pd-1582838-pn-W2500EP/ads-transient-convolution-gt. "accelerates signal integrity simulations on workstations that have Nvidia Compute Unified Device Architecture (CUDA)-based Graphics Processing Units (GPU)"
79. ↑ GrAVity: A Massively Parallel Antivirus Engine . Giorgos Vasiliadis and Sotiris Ioannidis, GrAVity: A Massively Parallel Antivirus Engine. In proceedings of RAID 2010.
80. ↑ "Kaspersky Lab utilizes Nvidia technologies to enhance protection". Kaspersky Lab. 14 December 2009. http://www.kaspersky.com/news?id=207575979. "During internal testing, the Tesla S1070 demonstrated a 360-fold increase in the speed of the similarity-defining algorithm when compared to the popular Intel Core 2 Duo central processor running at a clock speed of 2.6 GHz."
81. ↑ Gnort: High Performance Network Intrusion Detection Using Graphics Processors . Giorgos Vasiliadis et al., Gnort: High Performance Network Intrusion Detection Using Graphics Processors. In proceedings of RAID 2008.
82. ↑ Regular Expression Matching on Graphics Hardware for Intrusion Detection . Giorgos Vasiliadis et al., Regular Expression Matching on Graphics Hardware for Intrusion Detection. In proceedings of RAID 2009.
83. ↑ "Archived copy". http://www.nvidia.com/docs/IO/123576/nv-applications-catalog-lowres.pdf.
84. ↑ Langdon, William B; Lam, Brian Yee Hong; Petke, Justyna; Harman, Mark (2015). "Improving CUDA DNA Analysis Software with Genetic Programming". Proceedings of the 2015 on Genetic and Evolutionary Computation Conference - GECCO '15. pp. 1063–1070. doi:10.1145/2739480.2754652. ISBN 9781450334723.

* v
* t
* e

Graphics processing unit

GPU|

| Desktop|

* Intel
* GT
* Nvidia
* GeForce
* Quadro
* Tesla
* AMD
* Radeon
* Pro
* Instinct
* Matrox
* InfiniteReality
* µPD7220
* Voodoo

|

Mobile|

* Adreno
* Apple
* Mali
* PowerVR
* VideoCore

Architecture|

* Compute kernel
* Fabrication
* CMOS
* FinFET
* MOSFET
* Graphics pipeline
* Geometry
* Vertex
* HDR rendering
* MAC
* Rasterisation
* Shading
* Ray-tracing
* SIMD
* SIMT
* Tessellation
* T&L
* Tiled rendering
* Unified shader model

Components|

* Blitter
* Geometry processor
* Input–output memory management unit
* Render output unit
* Shader unit
* Stream processor
* Tensor unit
* Texture mapping unit
* Video display controller
* Video processing unit

Memory|

* DMA
* Framebuffer
* SGRAM
* GDDR
* GDDR3
* GDDR4
* GDDR5
* GDDR6
* HBM
* Memory bandwidth
* Memory controller
* Shared graphics memory
* Texture memory
* VRAM

Form factor|

* IP core
* Discrete graphics
* Clustering
* Switching
* External graphics
* Integrated graphics
* System on a chip

Performance|

* Clock rate
* Display resolution
* Fillrate
* Pixel/s
* Texel/s
* FLOP/s
* Frame rate
* Performance per watt
* Transistor count

Misc|

* 2D
* Scrolling
* Sprite
* Tile
* 3D
* GI
* Texture
* ASIC
* GPGPU
* Graphics library
* Hardware acceleration
* Image processing
* Compression
* Parallel computing
* Vector processor
* Video coding
* Codec
* VLIW

* v
* t
* e

Processor technologies

Models|

* Turing machine
* Universal
* Post–Turing
* Quantum
* Belt machine
* Stack machine
* Finite-state machine
* with datapath
* Hierarchical
* Queue automaton
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load/store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* comparison
* addressing modes

|

* x86
* ARM
* MIPS
* Power ISA
* SPARC
* Itanium
* Unicore
* MicroBlaze
* RISC-V
* others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Tomasulo algorithm
* Reservation station
* Re-order buffer
* Register renaming

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* SWAR
* SIMT
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Coprocessor
* ASIC
* FPGA
* CPLD
* Multi-chip module (MCM)
* System in package (SiP)

| By application|

* Microprocessor
* Microcontroller
* Mobile
* Notebook
* Ultra-low-voltage
* ASIP

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Programmable (PSoC)
* Network on a chip (NoC)

Hardware
accelerators|

* AI accelerator
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor processing unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 2-bit
* 4-bit
* 8-bit
* 16-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Integrated memory controller (IMC)

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Program counter

Control unit|

* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)
* Race to sleep

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model

* v
* t
* e

Parallel computing

General|

* Distributed computing
* Parallel computing
* Massively parallel
* Cloud computing
* High-performance computing
* Multiprocessing
* Manycore processor
* GPGPU
* Computer network
* Systolic array

Levels|

* Bit
* Instruction
* Thread
* Task
* Data
* Memory
* Loop
* Pipeline

Multithreading|

* Temporal
* Simultaneous (SMT)
* Speculative (SpMT)
* Preemptive
* Cooperative
* Clustered Multi-Thread (CMT)
* Hardware scout

Theory|

* PRAM model
* PEM Model
* Analysis of parallel algorithms
* Amdahl's law
* Gustafson's law
* Cost efficiency
* Karp–Flatt metric
* Slowdown
* Speedup

Elements|

* Process
* Thread
* Fiber
* Instruction window
* Array data structure

Coordination|

* Multiprocessing
* Memory coherency
* Cache coherency
* Cache invalidation
* Barrier
* Synchronization
* Application checkpointing

Programming|

* Stream processing
* Dataflow programming
* Models
* Implicit parallelism
* Explicit parallelism
* Concurrency
* Non-blocking algorithm

Hardware|

* Flynn's taxonomy
* SISD
* SIMD
* SIMT
* MISD
* MIMD
* Dataflow architecture
* Pipelined processor
* Superscalar processor
* Vector processor
* Multiprocessor
* symmetric
* asymmetric
* Memory
* shared
* distributed
* distributed shared
* UMA
* NUMA
* COMA
* Massively parallel computer
* Computer cluster
* Grid computer
* Hardware acceleration

APIs|

* Ateji PX
* Boost.Thread
* Chapel
* HPX
* Charm++
* Cilk
* Coarray Fortran
* CUDA
* HIP
* Dryad
* C++ AMP
* Global Arrays
* MPI
* OpenMP
* OpenCL
* OpenHMPP
* OpenACC
* TPL
* PLINQ
* PVM
* POSIX Threads
* RaftLib
* UPC
* TBB
* ZPL

Problems|

* Automatic parallelization
* Deadlock
* Livelock
* Deterministic algorithm
* Embarrassingly parallel
* Parallel slowdown
* Race condition
* Software lockout
* Scalability
* Starvation

* Category: parallel computing
* Media related to Parallel computing at Wikimedia Commons

* v
* t
* e

Emerging technologies

Fields|

| Agriculture|

* Agricultural robot
* Cellular agriculture
* Closed ecological systems
* Cultured meat
* Genetically modified food
* Precision agriculture
* Vertical farming

|

Architecture|

* Arcology
* Building printing
* Contour crafting
* Domed city

Biomedical|

* Artificial uterus
* Ampakine
* Brain transplant
* Cryonics
* Cryoprotectant
* Cryopreservation
* Vitrification
* Suspended animation
* De-extinction
* Genetic engineering
* Gene therapy
* Head transplant
* Isolated brain
* Life extension
* Strategies for Engineered Negligible Senescence
* Nanomedicine
* Nanosensors
* Organ printing
* Personalized medicine
* Regenerative medicine
* Stem-cell therapy
* Tissue engineering
* Robot-assisted surgery
* Synthetic biology
* Synthetic genomics
* Virotherapy
* Oncolytic virus
* Tricorder
* Whole genome sequencing

Displays|

| Next generation|

* FED
* FLCD
* iMoD
* Laser
* LPD
* OLED
* OLET
* QD-LED
* SED
* TPD
* TDEL
* TMOS
* MicroLED

|

Screenless|

* Bionic contact lens
* Head-mounted display
* Head-up display
* Optical head-mounted display
* Virtual retinal display

Other|

* Autostereoscopy
* Flexible display
* Holographic display
* Computer-generated holography
* Multi-primary color display
* Ultra HD
* Volumetric display

Electronics|

* Electronic nose
* E-textiles
* Flexible electronics
* Molecular electronics
* Nanoelectromechanical systems
* Memristor
* Spintronics
* Thermal copper pillar bump
* Twistronics

Energy|

| Production|

* Airborne wind turbine
* Artificial photosynthesis
* Biofuels
* Carbon-neutral fuel
* Concentrated solar power
* Fusion power
* Home fuel cell
* Hydrogen economy
* Methanol economy
* Molten salt reactor
* Nantenna
* Photovoltaic pavement
* Space-based solar power
* Vortex engine

|

Storage|

* Beltway battery
* Compressed air energy storage
* Flywheel energy storage
* Grid energy storage
* Lithium–air battery
* Molten-salt battery
* Nanowire battery
* Research in lithium-ion batteries
* Silicon–air battery
* Thermal energy storage
* Ultracapacitor

Other|

* Smart grid
* Wireless power

Information and
communications

* Ambient intelligence
* Internet of things
* Artificial intelligence
* Applications of artificial intelligence
* Progress in artificial intelligence
* Machine translation
* Mobile translation
* Machine vision
* Semantic Web
* Speech recognition
* Atomtronics
* Carbon nanotube field-effect transistor
* Cybermethodology
* Fourth-generation optical discs
* 3D optical data storage
* Holographic data storage
* GPGPU
* Memory
* CBRAM
* FRAM
* Millipede
* MRAM
* NRAM
* PRAM
* Racetrack memory
* RRAM
* SONOS
* Optical computing
* RFID
* Chipless RFID
* Software-defined radio
* Three-dimensional integrated circuit

Manufacturing|

* 3D printing
* Claytronics
* Molecular assembler
* Utility fog

Materials science|

* Aerogel
* Amorphous metal
* Artificial muscle
* Conductive polymer
* Femtotechnology
* Fullerene
* Graphene
* High-temperature superconductivity
* High-temperature superfluidity
* Linear acetylenic carbon
* Metamaterials
* Metamaterial cloaking
* Metal foam
* Multi-function structures
* Nanotechnology
* Carbon nanotubes
* Molecular nanotechnology
* Nanomaterials
* Picotechnology
* Programmable matter
* Quantum dots
* Silicene
* Superalloy
* Synthetic diamond

Military|

* Antimatter weapon
* Caseless ammunition
* Directed-energy weapon
* Laser
* Maser
* Particle-beam weapon
* Sonic weapon
* Coilgun
* Railgun
* Plasma weapon
* Pure fusion weapon
* Stealth technology
* Vortex ring gun

Neuroscience|

* Artificial brain
* Brain–computer interface
* Electroencephalography
* Mind uploading
* Brain-reading
* Neuroinformatics
* Neuroprosthetics
* Bionic eye
* Brain implant
* Exocortex
* Retinal implant

Quantum|

* Quantum algorithms
* Quantum amplifier
* Quantum bus
* Quantum channel
* Quantum circuit
* Quantum complexity theory
* Quantum computing
* Quantum cryptography
* Quantum dynamics
* Quantum electronics
* Quantum error correction
* Quantum imaging
* Quantum information
* Quantum key distribution
* Quantum logic
* Quantum logic gates
* Quantum machine
* Quantum machine learning
* Quantum metamaterial
* Quantum metrology
* Quantum network
* Quantum neural network
* Quantum optics
* Quantum programming
* Quantum sensing
* Quantum simulator
* Quantum teleportation

Robotics|

* Domotics
* Nanorobotics
* Powered exoskeleton
* Self-reconfiguring modular robot
* Swarm robotics
* Uncrewed vehicle

Space science|

| Launch|

* Fusion rocket
* Non-rocket spacelaunch
* Mass driver
* Orbital ring
* Skyhook
* Space elevator
* Space fountain
* Space tether
* Reusable launch system

|

Propulsion|

* Beam-powered propulsion
* Ion thruster
* Laser propulsion
* Plasma propulsion engine
* Helicon thruster
* VASIMR
* Nuclear pulse propulsion
* Solar sail

Other|

* Interstellar travel
* Propellant depot
* Laser communication in space

Transport|

| Aerial|

* Adaptive compliant wing
* Backpack helicopter
* Delivery drone
* Flying car
* High-altitude platform
* Jet pack
* Pulse detonation engine
* Scramjet
* Spaceplane
* Supersonic transport

|

Land|

* Airless tire
* Alternative fuel vehicle
* Hydrogen vehicle
* Driverless car
* Ground effect train
* Hyperloop
* Maglev train
* Personal rapid transit
* Transit Elevated Bus
* Vactrain
* Vehicular communication systems

Pipeline|

* Pneumatic transport
* Automated vacuum collection

Other|

* Anti-gravity
* Cloak of invisibility
* Digital scent technology
* Force field
* Plasma window
* Immersive virtual reality
* Magnetic refrigeration
* Phased-array optics

Topics|

* Collingridge dilemma
* Differential technological development
* Disruptive Innovation
* Ephemeralization
* Exploratory engineering
* Fictional technology
* Proactionary principle
* Technological change
* Technological unemployment
* Technological convergence
* Technological evolution
* Technological paradigm
* Technology forecasting
* Accelerating change
* Moore's law
* Technological singularity
* Technology scouting
* Technology readiness level
* Technology roadmap
* Transhumanism

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* List

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