ARC (processor)

Short description: Family of RISC-based computer processors

ARCDesigner| ARC International PLC

|

Bits| 32-bit, 64-bit
Introduced| 1996; 30 years ago (1996)
Version| ARCv3
Design| RISC
Type| Register–Register
Encoding| Variable (16- and 32-bit)
Branching| Compare and branch
Endianness| Bi
Extensions| APEX user-defined instructions
Registers
16 or 32 including SP user can increase to 60

ARC (Argonaut RISC Core) embedded system processors are a family of 32-bit and 64-bit reduced instruction set computer (RISC) central processing units (CPUs) originally designed by ARC International.

ARC processors are configurable and extensible for a wide range of uses in system on a chip (SoC) devices, including storage, digital home, mobile, automotive, and Internet of things (IoT) applications. They have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year.[1]

ARC processors employ the 16-/32-bit ARCompact instruction set architecture (ISA) that provides good performance and code density for embedded and host SoC applications.

## Contents

* 1 History
* 2 Design configuration
* 3 See also
* 4 References
* 5 Further reading
* 6 External links

## History

The ARC concept was developed initially within Argonaut Games through a series of 3D pipeline development projects starting with the Super FX chip for the Super Nintendo Entertainment System.

In 1995, Argonaut was split into Argonaut Technologies Limited (ATL), which had a variety of technology projects, and Argonaut Software Limited (ASL).

At the start of 1996, the General Manager of Argonaut, John Edelson, started reducing ATL projects such as BRender and motion capture and investing in the development of the ARC concept. In September 1996 Rick Clucas decided that the value of the ARC processor was in other people using it rather than Argonaut doing projects using it and asked Bob Terwilliger to join as CEO; Rick Clucas then took on the role of CTO.

In 1997, following investment by Apax Partners, ATL became ARC International and fully independent from Argonaut Games. Before their initial public offering on the London Stock Exchange, underwritten by Goldman Sachs and five other investment banks, three related technology companies were acquired: Metaware in Santa Cruz, California (development and modeling software),[2] VAutomation in Nashua, New Hampshire (peripheral semiconductor IP), and Precise Software in Nepean, Ontario (RTOS).

In 2009, ARC International was acquired by Virage Logic. In 2010, Virage was acquired by Synopsys, and ARC processors became part of the Synopsys DesignWare series.

In April 2020 Synopsys released the ARCv3 ISA with 64-bit support.[3]

## Design configuration

Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements.

Configuration of the ARC processors occurs at design time, using the ARChitect processor configurator.[4] The core was designed to be extensible, allowing designers to add their own custom instructions that can significantly increase performance or reduce power consumption.

Unlike most embedded microprocessors, extra instructions, registers, and functions can be added in a modular fashion. Customers analyse the task, break down the operations, and then choose the appropriate extensions, or develop their own, to create their own custom microprocessor. They might optimise for speed, energy efficiency, or code density. Extensions can include, for example, a memory management unit (MMU), a fast multiplier–accumulator, a Universal Serial Bus (USB) host, a Viterbi path decoder, or a user's proprietary RTL functions.

The processors are synthesizable and can be implemented in any foundry or process, and are supported by a complete suite of development tools.[5]

## See also

* List of common microcontrollers
* Comparison of instruction set architectures

## References

1. ↑ "Overcoming the power/performance paradox in processor IP". http://www.techdesignforums.com/practice/technique/power-performance-processor-ip/.
2. ↑ Ascierto, Jerry (27 September 1999). "ARC Acquires MetaWare". https://www.edn.com/arc-acquires-metaware/.
3. ↑ "Synopsys Introduces New 64-bit ARC Processor IP". https://news.synopsys.com/2020-04-07-Synopsys-Introduces-New-64-bit-ARC-Processor-IP-Delivering-Up-to-3x-Performance-Increase-for-High-End-Embedded-Applications.
4. ↑ "ARChitect Processor Configurator". Arc.com. http://www.arc.com/configurablecores/architect/.
5. ↑ "Accelerating Development of Performance-Efficient SoCs". synopsys.com. http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx.

## Further reading

* Toshiba, ARC in configurable processor collaboration, 15 May 2006
* SPF: All About Power, Performance, 30 June 2006
* Architectures: Programmable ARC platform targets low-cost multimedia, 2 October 2006
* ARC adopts clustered parallelism in media multiprocessing, 9 October 2006
* ARC signs "landmark" licensing deal with Intel, EE Times 9/11/2007

## External links

Template:Programmable logic

* v
* t
* e

Reduced instruction set computer (RISC) architectures

* IBM 801
* Berkeley RISC
* Stanford MIPS

Active|

* Analog Devices Blackfin
* ARC
* ARM
* AVR
* eSi-RISC
* LatticeMico8
* LatticeMico32
* MIPS
* OpenRISC
* Power ISA
* Renesas M32R
* Renesas SuperH
* Renesas V850
* RISC-V
* Sunway
* SPARC
* Unicore
* Xilinx MicroBlaze
* Xilinx PicoBlaze
* POWER
* PowerPC
* XMOS XCore XS1

Historic|

* Alpha
* AMD Am29000
* Apollo PRISM
* Atmel AVR32
* Clipper
* CRISP
* DEC Prism
* Intel i860
* Intel i960
* Meta
* MIPS-X
* Motorola 88000
* Motorola M·CORE
* PA-RISC
* ROMP

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