Excavator (microarchitecture)

Short description: Microarchitecture by AMD

Excavator – Family 15h (4th-gen)General Info

Launched| June 2, 2015; 8 years ago (June 2, 2015)[1]
Common manufacturer(s)|

* AMD

Architecture and classification
Min. feature size| 28 nm bulk silicon (GF28A)[2]
Instruction set| AMD64 (x86-64)
Physical specifications
Socket(s)|

* Socket FM2+ (Carrizo)
* Socket AM4 (Bristol Ridge)
* Socket FP3 (µBGA)

Products, models, variants
Core name(s)|

* Carrizo
* Bristol Ridge
* Stoney Ridge

History
Predecessor| Steamroller – Family 15h (3rd-gen)
Successor| Zen

AMD Excavator Family 15h is a microarchitecture developed by AMD to succeed Steamroller Family 15h for use in AMD APU processors and normal CPUs. On October 12, 2011, AMD revealed Excavator to be the code name for the fourth-generation Bulldozer-derived core.

The Excavator-based APU for mainstream applications is called Carrizo and was released in 2015.[3][4] The Carrizo APU is designed to be HSA 1.0 compliant.[5] An Excavator-based APU and CPU variant named Toronto for server and enterprise markets was also produced.[6]

Excavator was the final revision of the "Bulldozer" family, with two new microarchitectures replacing Excavator a year later.[7][8] Excavator was succeeded by the x86-64 Zen architecture in early 2017.[9][10]

## Contents

* 1 Architecture
* 2 Features and ASICs
* 3 Processors
* 3.1 APU lines
* 3.1.1 CPU Desktop lines
* 3.2 Server lines
* 4 References

## Architecture

Excavator added hardware support for new instructions such as AVX2, BMI2 and RDRAND.[11] Excavator is designed using High Density (aka "Thin") Libraries normally used for GPUs to reduce electric energy consumption and die size, delivering a 30 percent increase in efficient energy use.[12] Excavator can process up to 15% more instructions per clock compared to AMD's previous core Steamroller.[13]

## Features and ASICs

The following table shows features of AMD's APUs (see also: List of AMD accelerated processing units).

[ VisualEditor ] [view * talk * edit]

Codename | Server  | Basic  |  | Toronto |  |  |

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Micro  |  |  | Kyoto |
Desktop | Mainstream  |  | Carrizo | Bristol Ridge | Raven Ridge | Picasso |  |
Entry  | Llano | Trinity | Richland | Kaveri |
Basic  |  |  | Kabini |
Mobile | Performance  |  | Renoir |
Mainstream  | Llano | Trinity | Richland | Kaveri | Carrizo | Bristol Ridge | Raven Ridge | Picasso
Entry  |  |  | Dalí
Basic  |  | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge
Embedded  |  | Trinity |  | Bald Eagle | Merlin Falcon,
Brown Falcon |  | Great Horned Owl |  | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle,
LX-Family |  | Prairie Falcon | Banded Kestrel
Platform | High, standard and low power | Low and ultra-low power
Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019
CPU microarchitecture | K10 | Piledriver | Steamroller | Excavator | "Excavator+"[14] | Zen | Zen+ | Zen 2 | Bobcat | Jaguar | Puma | Puma+[15] | "Excavator+" | Zen
ISA | x86-64 | x86-64
Socket | Desktop | High-end | N/A | N/A
Mainstream | N/A | AM4
Entry | FM1 | FM2 | FM2+[lower-alpha 1] | N/A
Basic | N/A | N/A | AM1 | N/A
Other | FS1 | FS1+, FP2 | FP3 | FP4 | FP5 | FP6 | FT1 | FT3 | FT3b | FP4 | FP5
PCI Express version | 2.0 | 3.0 | 2.0 | 3.0
[[Engineering:Semiconductor device fabricatFab. (Nanometre|nm]]) | GF 32SHP
(HKMG SOI) | GF 28SHP
(HKMG bulk) | GF 14LPP
(FinFET bulk) | GF 12LP
(FinFET bulk) | TSMC N7
(FinFET bulk) | TSMC N40
(bulk) | TSMC N28
(HKMG bulk) | GF 28SHP
(HKMG bulk) | GF 14LPP
(FinFET bulk)
Die area (mm2) | 228 | 246 | 245 | 245 | 250 | 210[16] | 156 | 75 (+ 28 FCH) | 107 | ? | 125 |
Min TDP (W) | 35 | 17 | 12 | 10 | 4.5 | 4 | 3.95 | 10 | 6
Max APU TDP (W) | 100 | 95 | 65 | 54 | 18 | 25
Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.3 | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 3.3
Max APUs per node[lower-alpha 2] | 1 | 1
Max CPU[lower-alpha 3] cores per APU | 4 | 8 | 2 | 4 | 2
Max threads per CPU core | 1 | 2 | 1 | 2
Integer structure | 3+3 | 2+2 | 4+2 | 4+2+1 | 1+1+1+1 | 2+2 | 4+2
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF |  |
IOMMU[lower-alpha 4] | N/A |
BMI1, AES-NI, CLMUL, and F16C | N/A |
MOVBE | N/A |
AVIC, BMI2 and RDRAND | N/A |
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO | N/A |  | N/A |
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT | N/A |  | N/A
FPUs per core | 1 | 0.5 | 1 | 1 | 0.5 | 1
Pipes per FPU | 2 | 2
FPU pipe width | 128-bit | 256-bit | 80-bit | 128-bit
CPU instruction set SIMD level | SSE4a[lower-alpha 5] | AVX | AVX2 | SSSE3 | AVX | AVX2
3DNow! | 3DNow!+ | N/A | N/A
PREFETCH/PREFETCHW |  |
FMA4, LWP, TBM, and XOP | N/A |  | N/A | N/A |  | N/A
FMA3 |  |
L1 data cache per core (KiB) | 64 | 16 | 32 | 32
L1 data cache associativity (ways) | 2 | 4 | 8 | 8
L1 instruction caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1
Max APU total L1 instruction cache (KiB) | 256 | 128 | 192 | 256 | 64 | 128 | 96 | 128
L1 instruction cache associativity (ways) | 2 | 3 | 4 | 8 | 2 | 3 | 4
L2 caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1
Max APU total L2 cache (MiB) | 4 | 2 | 4 | 1 | 2 | 1
L2 cache associativity (ways) | 16 | 8 | 16 | 8
APU total L3 cache (MiB) | N/A | 4 | 8 | N/A | 4
APU L3 cache associativity (ways) | 16 | 16
L3 cache scheme | Victim | N/A | Victim | Victim
Max stock DRAM support | DDR3-1866 | DDR3-2133 | DDR3-2133, DDR4-2400 | DDR4-2400 | DDR4-2933 | DDR4-3200, LPDDR4-4266 | DDR3L-1333 | DDR3L-1600 | DDR3L-1866 | DDR3-1866, DDR4-2400 | DDR4-2400
Max DRAM channels per APU | 2 | 1 | 2
Max stock DRAM bandwidth (GB/s) per APU | 29.866 | 34.132 | 38.400 | 46.932 | 68.256 | 10.666 | 12.800 | 14.933 | 19.200 | 38.400
GPU microarchitecture | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | GCN 2nd gen | GCN 3rd gen | GCN 5th gen[17] | TeraScale 2 (VLIW5) | GCN 2nd gen | GCN 3rd gen[17] | GCN 5th gen
GPU instruction set | TeraScale instruction set | GCN instruction set | TeraScale instruction set | GCN instruction set
Max stock GPU base clock (MHz) | 600 | 800 | 844 | 866 | 1108 | 1250 | 1400 | 1750 | 538 | 600 | ? | 847 | 900 | 1200
Max stock GPU base GFLOPS[lower-alpha 6] | 480 | 614.4 | 648.1 | 886.7 | 1134.5 | 1760 | 1971.2 | 1792 | 86 | ? | ? | ? | 345.6 | 460.8
3D engine[lower-alpha 7] | Up to 400:20:8 | Up to 384:24:6 | Up to 512:32:8 | Up to 704:44:16[18] | Up to 512:?:? | 80:8:4 | 128:8:4 | Up to 192:?:? | Up to 192:?:?
IOMMUv1 | IOMMUv2 |  | IOMMUv1 | ? | IOMMUv2
Video decoder | UVD 3.0 | UVD 4.2 | UVD 6.0 | VCN 1.0[19] |  | UVD 3.0 | UVD 4.0 | UVD 4.2 | UVD 6.0 | UVD 6.3 | VCN 1.0
Video encoder | N/A | VCE 1.0 | VCE 2.0 | VCE 3.1 |  | N/A | VCE 2.0 | VCE 3.1
GPU power saving | PowerPlay | PowerTune |  | PowerPlay | PowerTune[20]
TrueAudio | N/A | [21] | N/A |
FreeSync | 1
2 | 1

HDCP[lower-alpha 8] | ? | 1.4 | 1.4
2.2 | ? | 1.4 | 1.4
2.2
PlayReady[lower-alpha 8] | N/A | 3.0 not yet |  | N/A | 3.0 not yet
Supported displays[lower-alpha 9] | 2–3 | 2–4 | 3 | 3 (desktop)
4 (mobile, embedded) | 4 | 2 | 3 | 4
`/drm/radeon`[lower-alpha 10][23][24] |  | N/A |  | N/A
`/drm/amdgpu`[lower-alpha 10][25] | N/A | [26] |  | N/A | [26] |

1. ↑ APU models: A8-7680, A6-7480. CPU only: Athlon X4 845.
2. ↑ A PC would be one node.
3. ↑ An APU combines a CPU and a GPU. Both have cores.
4. ↑ Requires firmware support.
5. ↑ No SSE4. No SSSE3.
6. ↑ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
7. ↑ Unified shaders : texture mapping units : render output units
8. ↑ 8.0 8.1 To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
9. ↑ To feed more than two displays, the additional panels must have native DisplayPort support.[22] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
10. ↑ 10.0 10.1 DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

## Processors

### APU lines

There are three APU lines announced or released:

1. Budget and mainstream markets (desktop and mobile): Carrizo APU
* The Carrizo mobile APUs were launched in 2015 based on Excavator x86 cores and featuring Heterogeneous System Architecture for integrated task sharing between CPUs and GPUs, which allows a GPU to perform compute functions, which is claimed provide greater performance increases than shrinking the feature size alone.[5]
* Carrizo desktop APUs were launched in 2018. The mainstream product (A8-7680) has 4 Excavator cores and a GPU based on GCN1.2 architecture. Also, an entry-level APU (A6-7480) with 2 Excavator cores is also launched.
2. Budget and mainstream markets (desktop and mobile): Bristol Ridge, and Stoney Ridge (for entry level notebooks), APUs[27]
* Bristol Ridge APUs utilize socket AM4 and DDR4 RAM
* Bristol Ridge APUs have up to 4 Excavator CPU cores and up to 8 3rd generation GCN GPU cores
* Up to a 20% CPU performance increase over Carrizo
* TDP of 15W to 65W, 15–35W for mobile
3. Enterprise and server markets:  Toronto APU
* The Toronto APU for server and enterprise markets featured four x86 Excavator CPU core modules and Volcanic Islands integrated GPU core.
* The Excavator cores has a greater advantage with IPC than Steamroller. The improvement is 4–15%.
* Support for HSA/hUMA, DDR3/DDR4, PCIe 3.0, GCN 1.2[5][6][10]
* The Toronto APU was available in BGA and SoC variants. The SoC variant had the southbridge on the same die as the APU to save space and power and to optimize workloads.
* A complete system with a Toronto APU would have a maximum power usage of 70 W.[6]

#### CPU Desktop lines

There are no CPUs Steamroller (3rd gen Bulldozer) or Excavator (4th gen Bulldozer) architectures on high-end desktop platforms.

Excavator CPU for Desktop announced on 2nd Feb 2016, named Athlon X4 845.[28]In 2017, three more desktop CPUs (Athlon X4 9x0) were launched. They come in Socket AM4, with a TDP of 65W. In fact, they are APUs with their graphics cores disabled.

List of desktop Excavator CPUs  Brand

Name

| Model

Number

| Code

Name

| Freq. (GHz)  | Cores  | TDP

(W)

| Socket  | Cache  | PCI Express 3.0  | Relative IPC | Locked

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Base  | Turbo | L1D | L2
Athlon X4  | 845  | Carrizo | 3.5  | 3.8 | 4 | 65  | FM2+ | 4x

32KB

| 2x

1MB

| x8 | 1.0  | Yes
940  | Bristol Ridge | 3.2  | 3.6  | AM4 | x16 | 1.1  | No
950  | 3.5  | 3.8
970  | 3.8  | 4.0

### Server lines

Main page: Engineering:List of AMD Opteron microprocessors

The AMD Opteron roadmaps for 2015 show the Excavator-based Toronto APU and Toronto CPU intended for 1 Processor (1P) cluster applications:[6]

* For 1P Web and Enterprise Services Clusters:
* Toronto CPU – quad-core x86 Excavator architecture
* plans for Cambridge CPU – 64-bit AArch64 core
* For 1P Compute and Media Clusters:
* Toronto APU – quad-core x86 Excavator architecture
* For 2P/4P Servers:
* Warsaw CPU – 12/16 core x86 Piledriver (2nd gen Bulldozer) (Opteron 6338P and 6370P)
* no plans for Steamroller (3rd gen Bulldozer) or Excavator (4th gen Bulldozer) architectures on high-end multi-processor platforms

## References

1. ↑ "Computex 2015: AMD launches Carrizo A-Series processors | ZDNet". https://www.zdnet.com/article/computex-2015-amd-launches-carrizo-processors/.
2. ↑ "AMD leak confirms that Excavator APU will be 28nm, and that some production is moving back to GlobalFoundries - ExtremeTech". https://www.extremetech.com/computing/176919-amd-leak-confirms-that-excavator-apu-will-be-28nm-and-that-some-production-is-moving-back-to-globalfoundries.
3. ↑ Reynolds, Sam (October 31, 2013). "New confirmed details on AMD's 2014 APU lineup, Kaveri delayed". Vr-zone.com. http://vr-zone.com/articles/new-confirmed-details-on-amds-2014-apu-lineup-kaveri-delayed/47455.html.
4. ↑ "AMD updates product roadmap for 2014 and 2015". Digitimes.com. August 26, 2013. http://www.digitimes.com/news/a20130826PD216.html.
5. ↑ 5.0 5.1 5.2 Hachman, Mark (November 21, 2014). "AMD reveals high-end 'Carrizo' APU, the first chip to fully embrace audacious HSA tech". PCWorld. http://www.pcworld.com/article/2850853/amd-reveals-high-end-carrizo-apu-its-first-fully-hsa-compliant-chip.html.
6. ↑ 6.0 6.1 6.2 6.3 Mujtaba, Hassan (December 26, 2013). "AMD Opteron Roadmap Reveals Next Generation Toronto and Carrizo APU Details". WCCF Tech. http://wccftech.com/amd-opteron-roadmap-reveals-generation-tronoto-carrizo-apu-details-excavator-cores-volcanic-islands-gpu-fusion/.
7. ↑ "AMD hints at high-performance Zen x86 architecture | bit-tech.net". https://bit-tech.net/news/tech/cpus/amd-zen/1/.
8. ↑ "AMD to Introduce New High-Performance Micro-Architecture in 2015 – Report - X-bit labs". http://www.xbitlabs.com/news/cpu/display/20140510165441_AMD_to_Introduce_New_High_Performance_Micro_Architecture_in_2015_Report.html.
9. ↑ Moammer, Khalid (September 9, 2014). "AMD's Next Gen x86 High Performance Core is Zen". WCCF Tech. http://wccftech.com/breaking-amds-gen-x86-high-performance-core-code-named-zen-debut-k12/.
10. ↑ 10.0 10.1 Mujtaba, Hassan (May 5, 2014). "AMD Announces 2014-2016 Roadmap – 20nm Project SkyBridge and K12 64-bit ARM Cores For 2016". WCCF Tech. http://wccftech.com/amd-announces-20142016-roadmap-20nm-project-skybridge-k12-64bit-arm-cores-2016/.
11. ↑ "AMDs Carrizo architecture detailed and explored". Extremetech.com. June 2, 2015. https://www.extremetech.com/mobile/207229-207229.
12. ↑ Crowthers, Doug (August 28, 2012). "AMD Explains Advantages of High Density (Thin) Libraries". https://www.tomshardware.com/news/Steamroller-High_Density_Libraries-hot-chips-cpu-gpu,17218.html.
13. ↑ Mujtaba, Hassan (August 26, 2015). "AMD Details Carrizo APUs Energy Efficient Design at Hot Chips 2015 - 28nm Bulk High Density Design With 3.1 Billion Transistors, 250mm2 Die". https://wccftech.com/amd-carrizo-apu-architecture-hot-chips/.
14. ↑ "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks. Retrieved 3 January 2020.
15. ↑ "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
16. ↑ "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/. Retrieved 13 December 2017.
17. ↑ 17.0 17.1 "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/. Retrieved 6 June 2017.
18. ↑ Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3. Retrieved 7 February 2018.
19. ↑ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands. Retrieved 20 November 2017.
20. ↑ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture", AMD, http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf, retrieved 13 August 2016
21. ↑ "A technical look at AMD's Kaveri architecture". Semi Accurate. http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/. Retrieved 6 July 2014.
22. ↑ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. http://support.amd.com/en-us/search/faq/154. Retrieved 8 December 2014.
23. ↑ Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". http://airlied.livejournal.com/68805.html. Retrieved 16 January 2016.
24. ↑ "Radeon feature matrix". freedesktop.org. http://xorg.freedesktop.org/wiki/RadeonFeature/. Retrieved 10 January 2016.
25. ↑ Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU". http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf. Retrieved 16 January 2016.
26. ↑ 26.0 26.1 Michel Dänzer (17 November 2016). "[ANNOUNCE xf86-video-amdgpu 1.2.0"]. lists.x.org. https://lists.x.org/archives/xorg-announce/2016-November/002741.html.
27. ↑ Cutress, Ian (1 June 2016). "AMD Announces 7th Generation APU". Anandtech.com. http://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks.
28. ↑ Jeff Kampman (2 February 2016). "AMD puts Excavator on the desktop with the Athlon X4 845". http://techreport.com/news/29669/amd-puts-excavator-on-the-desktop-with-the-athlon-x4-845.

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AMD processors

Lists|

* Microprocessors
* Microarchitectures
* Chipsets
* Sockets
* Duron
* Athlon
* XP
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* X2
* Sempron
* Phenom
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* Turion
* Opteron
* FX
* APUs

Microarchitectures|

| IA-32 (32-bit)|

* K5
* K6
* Athlon/K7

|

x86-64 desktop|

* K8
* K9
* K10 (aka 10h)
* 15h
* Bulldozer
* Piledriver
* Steamroller
* Excavator
* Zen
* 1st gen.
* Zen+
* Zen 2
* Zen 3

x86-64 low-power|

* Bobcat (aka 14h)
* 16h
* Jaguar
* Puma

ARM64|

* K12 (aka 12h)

Current products|

| x86-64 (64-bit)|

* Athlon
* Ryzen
* Threadripper
* Epyc

|

Discontinued|

| Early x86 (16-bit)|

* Am286

|

IA-32 (32-bit)|

* Am386
* Am486
* Am5x86
* K5
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* Athlon
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* MP
* Duron
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x86-64 (64-bit)|

* Athlon 64
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* II
* Sempron
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* A-series APUs

Other|

* Am9080
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