List of Intel CPU microarchitectures

Short description: None

The following is a list of Intel CPU microarchitectures. Intel has produced many generations of CPU microarchitectures since the 1970s, spanning x86 processors for desktop, mobile, and server markets. Additional details about Intel's manufacturing and architecture strategy can be found in Intel's tick–tock model and the process–architecture–optimization model, which describe how Intel historically alternated between shrinking manufacturing processes and introducing new architectures. See also Template:Intel processor roadmap for planned future architectures.

## Contents

* 1 x86 microarchitectures
* 1.1 16-bit
* 1.2 32-bit (IA-32)
* 1.3 64-bit (x86-64)
* 1.4 x86 ULV (Atom)
* 1.5 x86 MIC (Many Integrated Core)
* 2 Other microarchitectures
* 2.1 IA-64 (Itanium)
* 2.2 Miscellaneous
* 3 Roadmap
* 3.1 Pentium 4 / Core / P-Core lines
* 3.2 Atom / E-Core lines
* 4 See also
* 5 Notes
* 6 References
* 7 External links

## x86 microarchitectures

x86 microarchitectures  Year  | Micro­architecture  | Pipeline stages  | Max
clock
(MHz)  | Process node

|
|
|
|

1978  | 8086 (8086, 8088)  | 02  | 0005  | 3000 nm
1982  | 186 (80186, 80188)  | 02  | 0025
1982  | 286 (80286)  | 03  | 0025  | 1500 nm
1985  | 386 (80386)  | 06[1] | 0033
1989  | 486 (80486)  | 05  | 0100  | 1000 nm
1993  | P5 (Pentium)  | 05  | 0200  | 800, 600, 350 nm
1995  | P6 (Pentium Pro, Pentium II)  | 14 (17 with load & store/retire)  | 0450  | 500, 350, 250 nm
1997  | P5 (Pentium MMX)  | 06  | 0233  | 350 nm
1999  | P6 (Pentium III)  | 12 (15 with load & store/retire)  | 1400  | 250, 180, 130 nm
2000  | NetBurst (Pentium 4)
(Willamette)  | 20 unified with branch prediction  | 2000  | 180 nm
2002  | NetBurst (Pentium 4)
(Northwood, Gallatin)  | 3466  | 130 nm
2003  | Pentium M (Banias, Dothan)
Enhanced Pentium M (Yonah)  | 10 (12 with fetch/retire)  | 2333  | 130, 90, 65 nm
2004  | NetBurst (Pentium 4, Pentium D)
(Prescott)  | 31 unified with branch prediction  | 3800  | 90, 65 nm
2006  | Intel Core | 12 (14 with fetch/retire)  | 3000  | 65 nm
2007  | Penryn (die shrink)  | 3333  | 45 nm
2008  | Nehalem | 20 unified (14 without miss prediction)  | 3600
Bonnell | 16 (20 with prediction miss)  | 2100
2010  | Westmere (die shrink)  | 20 unified (14 without miss prediction)  | 3866  | 32 nm
2011  | Saltwell (die shrink) | 16 (20 with prediction miss)  | 2130
Sandy Bridge | 14 (16 with fetch/retire)  | 4000
2012  | Ivy Bridge (die shrink)  | 4100  | 22 nm
2013  | Silvermont | 14–17 (16–19 with fetch/retire)  | 2670
Haswell | 14 (16 with fetch/retire)  | 4400
2014  | Broadwell (die shrink)  | 3700  | 14 nm
2015  | Airmont (die shrink) | 14–17 (16–19 with fetch/retire)  | 2640
Skylake | 14 (16 with fetch/retire)  | 5300
2016  | Goldmont | 20 unified with branch prediction  | 2600
2017  | Goldmont Plus | 20 unified with branch prediction (?)  | 2800
2018  | Palm Cove  | 14 (16 with fetch/retire)  | 3200  | 10 nm
2019  | Sunny Cove  | 12–19 (misprediction)  | 4100
2020  | Tremont | 20 unified  | 3300
Willow Cove | 12 unified  | 5300
2021  | Cypress Cove  | 12 unified  | 5300  | 14 nm
Golden Cove | 12 unified  | 5500  | Intel 7
Gracemont | 20 unified with misprediction penalty  | 4300
2022  | Raptor Cove  | 12 unified  | 6200
2023  | Redwood Cove  | 10 unified  |  | Intel 4, Intel 3
Crestmont |  |  | Intel 4, TSMC N6, Intel 3
2024  | Lion Cove | 10 unified  |  | TSMC N3B
Skymont | 16 unified  |
2026  | Cougar Cove  |  |  | Intel 18A
Panther Cove |  |
Darkmont |  |
Coyote Cove |  |  |
Arctic Wolf |  |  |
2027 | Griffin Cove |  |  |
Note: Atom/Power efficient microarchitectures are in Italic

### 16-bit

8086
first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. The 8088 version, with an 8-bit bus, was used in the original IBM Personal Computer.
186
included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus.
286
first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3 to 4 over 8086. Included instructions relating to protected mode. The 80286 had a 24-bit address bus.

### 32-bit (IA-32)

i386
first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
i486
Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.

original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction.

used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".

* Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
* Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in the first Intel Core microprocessors, first x86 to have shadow register architecture and speed step technology.

NetBurst
commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.

### 64-bit (x86-64)

Core
reengineered P6-based microarchitecture used in Intel Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.

* Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.

Nehalem
released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.

* Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.

Sandy Bridge
32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007.[2] First x86 to introduce 256 bit AVX instruction set and implementation of YMM registers.

* Ivy Bridge: successor to Sandy Bridge, using 22 nm process, released in April 2012.

Haswell
22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including AVX2 and FMA.

* Broadwell: 14 nm derivative of the Haswell microarchitecture, released in September 2014. Three-cycle FMUL latency, 64 entry scheduler. Formerly called Rockwell.

Skylake
14 nm microarchitecture, released August 5, 2015.

* Kaby Lake: successor to Skylake, released in August 2016, broke Intel's tick-tock schedule due to delays with the 10 nm process.
* Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes)[3]
* Whiskey Lake: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities)[3]
* Skylake-X: high-end desktop, workstation and server microarchitecture, released on June 19, 2017 (HEDT), July 11, 2017 (SP) and August 29, 2017 (W). Introduces support for AVX-512 instruction set.
* Coffee Lake: successor to Kaby Lake, using 14++ nm process, released in October 2017
* Cascade Lake: server and high-end desktop successor to Kaby Lake-X and Skylake-X, using 14++ nm process, released in April 2019
* Comet Lake: successor to Coffee Lake, using 14++ nm process, released in August 2019[4]
* Cooper Lake: server-only, optimized for AI oriented workloads using bfloat16, with limited availability only to Intel priority partners, using 14++ nm process, released in 2020[5][6]

Palm Cove
Originally meant to be successor to Skylake, but cancelled after releasing just one chip. Includes the AVX-512 instruction set.[7][8]

* Cannon Lake: mobile-only successor of Kaby Lake, using Intel's 10 nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019.[9]

Starting with Cannon Lake, Intel has changed their microarchitecture naming scheme, decoupling core codenames from CPU codenames.[10]

Sunny Cove
Successor to the Palm Cove core, first non-Atom core to include hardware acceleration for SHA hashing algorithms.[11]

* Ice Lake: low power, mobile-only successor to Whiskey Lake, using 10 nm process, released in September 2019
* Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Sunny Cove is used in the singular performance core (P-core) of Lakefield processors.[12] AVX and more advanced instruction sets are disabled due to the E-core not supporting them.
* Ice Lake-SP: server-only successor to Cascade Lake, using 10 nm process, released in April 2021[5][13]

Cypress Cove
Backport of Sunny Cove to Intel's 14 nm process

* Rocket Lake: Successor to Comet Lake, using Intel's 14++ nm process, released on March 30, 2021[14][15][16]

Willow Cove
Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem.[17]

* Tiger Lake: successor to Ice Lake, using Intel's 10 nm SuperFin (10SF) process, released in Q4 2020

Golden Cove
Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions.[18]

* Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake; uses Intel 7 process (previously known as 10ESF),[19] released on November 4, 2021.[20] Golden Cove is used in P-cores of Alder Lake processors.[21]
* Sapphire Rapids: server and workstation-only, successor to Ice Lake-SP, manufactured on Intel 7 process,[19][22] released on January 10, 2023. Introduces AMX.

Raptor Cove
A refresh of Golden Cove with increased L2 and L3 caches and core clocks.

* Raptor Lake: successor to Alder Lake with increased cache sizes, core clocks and the number of E-cores, released on October 20, 2022. Manufactured using Intel 7 process. Raptor Cove is used in the P-cores while the E-cores are still implemented using Gracemont microarchitecture.
* Emerald Rapids: successor to Sapphire Rapids, server- and workstation-only. Fifth-generation Xeon Scalable server processors based on the Intel 7 node.

### x86 ULV (Atom)

Bonnell
45 nm, low-power, in-order microarchitecture for use in Atom processors.

* Saltwell: 32 nm shrink of the Bonnell microarchitecture.

Silvermont
22 nm, out-of-order microarchitecture for use in Atom processors, released on May 6, 2013.

* Airmont: 14 nm shrink of the Silvermont microarchitecture.

Goldmont
14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released in April 2016.[23][24]

* Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released on December 11, 2017.

Tremont
10 nm Atom microarchitecture iteration after Goldmont Plus.[25]

* Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Tremont is used in efficiency cores (E-cores) of Lakefield processors.[12]
* Jasper Lake: Celeron and Pentium Silver desktop and mobile processors, released in Q1 2021.
* Elkhart Lake: embedded processors targeted at IoT, released in Q1 2021.

Gracemont
Intel 7 process[19] Atom microarchitecture iteration after Tremont. First Atom class core with AVX and AVX2 support.

* Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake, released on November 4, 2021. Gracemont is used in E-cores of Alder Lake processors.[21]
* Raptor Lake: a refresh of Alder Lake, released on October 20, 2022.

### x86 MIC (Many Integrated Core)

Larrabee (cancelled 2010)
multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics.

Xeon Phi

## Other microarchitectures

### IA-64 (Itanium)

Merced
original Itanium microarchitecture. Used only in the first Itanium microprocessors.
McKinley
enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor. Madison is the 130 nm version.
Montecito
enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements. The Montvale update added demand-based switching (SpeedStep) and core-level lockstep execution.
Tukwila
enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, an integrated memory controller, QuickPath Interconnect, and other improvements e.g. a more active SoEMT.
Poulson
Itanium processor featuring an all-new microarchitecture.[26] 8 cores, decoupling in pipeline and in multithreading. 12-wide issue with partial out-of-order execution.[27]
Kittson
the last Itanium. It has the same microarchitecture as Poulson, but slightly higher clock speed for the top two models.

### Miscellaneous

4004/4040

8008

8080/8085

iAPX 432

80960

80860[note 1]

XScale
a microarchitecture implementing the ARM architecture instruction set.

## Roadmap

### Pentium 4 / Core / P-Core lines

Pentium 4 / Core roadmap  Fab
process | Micro­arch | Code
name  | Core
gen | Xeon
Scalable
gen | Release
date  | Processors

|
|
|
|
|
|

Mobile  | Desktop  | Enthusiast /
Workstation  | 1P/2P
Server  | 4P/8P
Server
180 nm  | P6,
NetBurst | Willamette  | -- | 2000-11-20 | -- | Willamette  | -- | Foster  | Foster MP
130 nm | Northwood/
Mobile Pentium 4
Banias | 2002-01-07 | Northwood Mobile
Banias | Northwood  | Northwood-XE  | Prestonia
Gallatin  | Gallatin
90 nm | Prescott
Dothan | 2004-02-01 | Dothan | Prescott
Smithfield  | Prescott 2M-XE
Smithfield-XE  | Nocona
Irwindale
Paxville  | Potomac
Cranford
Paxville
65 nm  | Cedar Mill
Yonah
Presler  | 1
(Yonah
only) | -- | 2006-01-05 | Yonah | Cedar Mill
Presler | Presler-XE | Dempsey
Sossaman  | Tulsa
Core | Merom  | 2  | 2006-07-27
[28][29] | Merom | Conroe  | Kentsfield | Woodcrest
Clovertown  | Tigerton
45 nm  | Penryn | 2007-11-11
[30] | Penryn | Wolfdale | Yorkfield | Harpertown  | Dunnington
Nehalem | Nehalem | 1
(Core i)  | 2008-11-17
[31] | Clarksfield | Lynnfield | Bloomfield | Gainestown | Beckton
32 nm  | Westmere | 2010-01-04
[32][33] | Arrandale  | Clarkdale | Gulftown | Westmere-EP | Westmere-EX
Sandy
Bridge | Sandy
Bridge | 2  | 2011-01-09
[34] | Sandy Bridge-M | Sandy Bridge | Sandy Bridge-E  | Sandy Bridge-EP | --[35]
22 nm | Ivy
Bridge  | 3  | 2012-04-29 | Ivy Bridge-M  | Ivy Bridge  | Ivy Bridge-E
[36] | Ivy Bridge-EP
[37] | Ivy Bridge-EX
[37]
Haswell | Haswell | 4  | 2013-06-02 | Haswell-H
Haswell-MB
Haswell-ULP/ULX[38] | Haswell-DT
[38] | Haswell-E  | Haswell-EP  | Haswell-EX
Devil's
Canyon  | 2014-06  | -- | Haswell-DT  | --
14 nm  | Broadwell | 5  | 2014-09-05 | Broadwell-H
Broadwell-U
Broadwell-Y  | Broadwell-DT  | Broadwell-E  | Broadwell-EP[39] | Broadwell-EX[39]
Skylake[lower-alpha 1] | Skylake | 6  | 1  | 2015-08-05
[40] | Skylake-H
Skylake-U
Skylake-Y  | Skylake-S  | Skylake-W
Skylake-X[41] | Skylake-SP
(formerly Skylake-EP/-EX)[42]
Kaby
Lake | 7 / 8  | -- | 2016-10  | Kaby Lake-G
Kaby Lake-H
Kaby Lake-U
Kaby Lake-Y  | Kaby Lake-S  | Kaby Lake-X
[41] | --
Coffee
Lake | 8 / 9  | 2017-10
[43] | Coffee Lake-B
Coffee Lake-H
Coffee Lake-U | Coffee Lake-S  | Coffee Lake-W | Coffee Lake
(Xeon E)  | --
Whiskey
Lake | 8  | 2018-08-28  | Whiskey Lake-U | --
Amber
Lake  | 8 / 10  | Amber Lake-Y
Cascade
Lake | -- | 2  | 2019-04-02 | -- | Cascade Lake-W
Cascade Lake-X | Cascade Lake-AP
Cascade Lake-SP  | Cascade Lake-SP
Comet
Lake | 10  | -- | 2019-09
[lower-alpha 2] | Comet Lake-H
Comet Lake-U[44]
Comet Lake-Y[44] | Comet Lake-S  | Comet Lake-W | --
Cooper
Lake  | -- | 3  | 2020-06  | --[45][46] | Cooper Lake-SP
Cypress
Cove[47][48] | Rocket
Lake | 11  | -- | 2021-03  | -- | Rocket Lake-S | Rocket
Lake-W | Rocket Lake
(Xeon E)  | --
10 nm | Palm
Cove  | Cannon
Lake  | 8  | 2018-05
[lower-alpha 2] | Cannon Lake-U  | --
Sunny
Cove[49] | Ice
Lake | 10  | 3  | 2019-09
(mobile)[lower-alpha 2]
2021-04
(server) | Ice Lake-U[50]
Ice Lake-Y[50] | -- | Ice Lake-W  | Ice Lake-SP[51] | --
Lakefield
(hybrid) | -- | -- | 2020-06-10
[52] | Lakefield  | --
Willow
Cove | Tiger
Lake | 11  | 2020-09  | Tiger Lake-H
Tiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4
Intel 7[lower-alpha 3] | Golden
Cove | Alder
Lake
(hybrid) | 12  | 2021-11-04
[16][53] | Alder Lake-H
Alder Lake-HX
Alder Lake-P
Alder Lake-U  | Alder Lake-S  | --
Sapphire
Rapids  | -- | 4  | 2023-01-10 | -- | Sapphire Rapids-WS  | Sapphire Rapids-SP
Sapphire Rapids-HBM  | Sapphire Rapids-SP
Raptor
Cove  | Raptor
Lake
(hybrid) | 13 / 14 /
Series
1 / 2  | -- | 2022-10-20 | Raptor Lake-H
Raptor Lake-HX
Raptor Lake-P
Raptor Lake-PX
Raptor Lake-U  | Raptor Lake-S  | -- | Raptor Lake
(Xeon E)  | --
Emerald
Rapids | -- | 5  | 2023-12-14 | -- | Emerald Rapids-SP
Intel 4[19] | Redwood
Cove  | Meteor
Lake
(hybrid) | Ultra Series 1 | -- | 2023-12-14
[54] | Meteor Lake-H
Meteor Lake-U  | --
Intel 3 | Granite
Rapids | -- | 6  | 2024-09-24
2026-02-02
(workstation) | -- | Granite Rapids-WS  | Granite Rapids-AP
Granite Rapids-SP  | Granite Rapids-SP
TSMC N3B  | Lion
Cove | Lunar
Lake
(hybrid) | Ultra
Series 2[55] | -- | 2024-09  | Lunar Lake-V  | --
Arrow
Lake
(hybrid)[56] | 2024-10-24
(desktop)
2025-01-06
(mobile)[57] | Arrow Lake-H
Arrow Lake-HX  | Arrow Lake-S  | --
Intel 3  | Redwood
Cove  | Arrow Lake-U
(Meteor Lake refresh) | --
Intel 18A  | Cougar
Cove  | Panther
Lake
(hybrid) | Ultra
Series 3  | 2026-01-05 | Panther Lake-H
Panther Lake-U
Panther Lake-HL
Panther Lake-UL
Panther
Cove X  | Diamond Rapids  | -- | TBA  | 2026  | -- |  | Diamond Rapids-AP  |
TBA
(TSMC
2 nm or
Intel 18A)  | Coyote
Cove  | Nova
Lake
(hybrid) | Ultra
Series 4  | -- | 2026  | Nova Lake-H
Nova Lake-HX
Nova Lake-U  | Nova Lake-S  | TBA  |  | --
Griffin
Cove  | Razor
Lake
(hybrid) |  | -- | 2027  | TBA  | TBA  | TBA  |  | --
|  | Titan
Lake  |  | -- | 2028  | TBA  | TBA  | TBA  |  | --
|  | Hammer
Lake  |  | -- | 2029  | TBA  | TBA  | TBA  |  | --

1. ↑ Cascade Lake and Cooper Lake microprocessors have additional instructions that enable Intel Deep Learning Boost.
2. ↑ 2.0 2.1 2.2 Retail availability.
3. ↑ Previously known as 10nm Enhanced Super Fin or 10ESF.[19]

### Atom / E-Core lines

Atom roadmap[58] Fabri­cation
process  | Micro­architecture  | Release
date  | Processors/SoCs

|
|
|

MID, smartphone  | Tablet  | Laptop  | Desktop  | Embedded  | Server  | Communication  | CE
45 nm  | Bonnell | 2008  | Silverthorne  | -- | Diamondville  | Tunnel Creek,
Stellarton  | -- |  | Sodaville
2010  | Lincroft  | Pineview  |  | Groveland
32 nm  | Saltwell  | 2011  | Medfield (Penwell & Lexington),
Clover Trail+ (Cloverview)  | Clover Trail (Cloverview)  | Cedar Trail (Cedarview)  |  | Centerton & Briarwood  |  | Berryville
22 nm  | Silvermont | 2013  | Merrifield (Tangier),[59] Slayton,
Moorefield (Anniedale)[60] | Bay Trail-T
(Valleyview)  | Bay Trail-M
(Valleyview)  | Bay Trail-D
(Valleyview)  | Bay Trail-I
(Valleyview)  | Avoton  | Rangeley  |
014 nm[58] | Airmont  | 2014  | Binghamton & Riverton  | Cherry Trail-T (Cherryview)[61] | Braswell[62] | Denverton  Cancelled |  |
Goldmont
[63] | 2016  | Broxton  Cancelled | Willow Trail  Cancelled
Apollo Lake  | Apollo Lake[64] | Denverton[65] |  |
Goldmont
Plus[66] | 2017  |  |  | Gemini Lake[67]
Gemini Lake Refresh[68] |  |  |
10 nm | Tremont[25] | 2020  |  | Lakefield (hybrid)  | Lakefield (hybrid)[69]
Elkhart Lake[70]
Jasper Lake[71] | Jacobsville
Parker Ridge[72]
Snow Ridge[73] |  |
Intel 7  | Gracemont[74] | 2021  |  |  | Alder Lake (hybrid)[75]
Raptor Lake (hybrid)
Alder Lake-N[76][77]
Twin Lake[78] |  |  |
Intel 4 | Crestmont  | 2023  |  |  |  | Grand Ridge  |  |
Intel 4 +
TSMC N6  |  |  | Meteor Lake (hybrid)  |  |  |
Intel 3 | 2024  |  |  |  | Sierra Forest |  |
TSMC N3B | Skymont  |  |  | Lunar Lake (hybrid)  |  |  |  |  |
|  | Arrow Lake (hybrid)  |  |  |
Intel 18A  | Darkmont  | 2026  |  |  | Panther Lake (hybrid)  |  |  | Clearwater Forest  |  |
| Arctic Wolf  |  |  | Nova Lake (hybrid)  |  |  |

## See also

* List of Intel processors \- Consumer Computer or non-consumer workstation
* List of AMD CPU microarchitectures
* Marvell Technology Group XScale microarchitecture
* Transient execution CPU vulnerability

## Notes

1. ↑ Completely unrelated to 80960.

## References

1. ↑ Rant, Jon; "Extending the Legacy of Leadership: The 80386 Arrives", Intel Corporation, Special 32-Bit Issue Solutions, November/December 1985, page 2
2. ↑ "An Update On Our Graphics-related Programs". May 25, 2010. http://blogs.intel.com/technology/2010/05/an_update_on_our_graphics-rela.php.
3. ↑ 3.0 3.1 Cutress, Ian. "Spectre and Meltdown in Hardware: Intel Clarifies Whiskey Lake and Amber Lake". https://www.anandtech.com/show/13301/spectre-and-meltdown-in-hardware-intel-clarifies-whiskey-lake-and-amber-lake.
4. ↑ "Intel Expands 10th Gen Intel Core Mobile Processor Family, Offering Double Digit Performance Gains" (in en-US). https://newsroom.intel.com/news/intel-expands-10th-gen-intel-core-mobile-processor-family-offering-double-digit-performance-gains/.
5. ↑ 5.0 5.1 Cutress, Ian. "Intel's Cooper Lake Plans: The Chip That Wasn't Meant to Exist, Fades Away". https://www.anandtech.com/show/15631/intels-cooper-lake-plans-the-chip-that-wasnt-meant-to-exist-dies-for-you.
6. ↑ Kennedy, Patrick (2020-03-16). "Intel Cooper Lake Rationalized Still Launching 1H 2020" (in en-US). https://www.servethehome.com/intel-cooper-lake-rationalized-still-launching-1h-2020/.
7. ↑ Cutress, Ian. "Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review". https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review.
8. ↑ "Palm Cove - Microarchitectures - Intel - WikiChip" (in en). https://en.wikichip.org/wiki/intel/microarchitectures/palm_cove.
9. ↑ Liu, Zhiye (October 31, 2019). "Intel Fires 10nm Cannon Lake NUC Into Oblivion". https://www.tomshardware.com/news/intel-fires-10nm-cannon-lake-nuc-into-oblivion.
10. ↑ Schor, David (December 23, 2018). "Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips". https://fuse.wikichip.org/news/1941/intel-reveals-10nm-sunny-cove-core-a-new-core-roadmap-and-teases-ice-lake-chips/.
11. ↑ "Sunny Cove - Microarchitectures - Intel". https://en.wikichip.org/wiki/intel/microarchitectures/sunny_cove.
12. ↑ 12.0 12.1 Cutress, Ian (July 2, 2020). "The Intel Lakefield Deep Dive: Everything To Know About the First x86 Hybrid CPU". https://www.anandtech.com/show/15877/intel-hybrid-cpu-lakefield-all-you-need-to-know.
13. ↑ "New Intel Processors Accelerate 5G Network Transformation". Newsroom.intel.com. 2021-04-06. https://newsroom.intel.com/news/new-intel-processors-accelerate-5g-network-transformation/. Retrieved 2022-05-08.
14. ↑ Cutress, Ian (March 30, 2021). "Intel octet Lake (14nm) Review: Core i911900K, Core i7-11700K, and Core i5-11600K". https://www.anandtech.com/show/16495/intel-rocket-lake-14nm-review-11900k-11700k-11600k.
15. ↑ "Intel Confirms Rocket Lake on Desktop for Q1 2021, with PCIe 4.0". https://www.anandtech.com/show/16145/intel-confirms-rocket-lake-on-desktop-for-q1-2021-with-pcie-40.
16. ↑ 16.0 16.1 Cutress, Ian (October 29, 2020). "Intel's 11th Gen Core Rocket Lake Detailed: Ice Lake Core with Xe Graphics". https://www.anandtech.com/show/16205/intels-11th-gen-core-rocket-lake-detailed-ice-lake-core-with-xe-graphics.
17. ↑ "Willow Cove - Microarchitectures - Intel". https://en.wikichip.org/wiki/intel/microarchitectures/willow_cove.
18. ↑ Cutress, Dr Ian. "Intel Alder Lake: Confirmed x86 Hybrid with Golden Cove and Gracemont for 2021". https://www.anandtech.com/show/15979/intel-alder-lake-confirmed-x86-hybrid-with-golden-cove-and-gracemont-for-2021.
19. ↑ 19.0 19.1 19.2 19.3 19.4 Cutress, Dr Ian. "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros.
20. ↑ Cutress, Ian (April 1, 2020). "Intel Updates ISA Manual: New Instructions for Alder Lake, also BF16 for Sapphire Rapids". https://www.anandtech.com/show/15686/intel-updates-isa-manual-new-instructions-for-alder-lake-also-bf16-for-sapphire-rapids.
21. ↑ 21.0 21.1 Cutress, Ian; Frumusanu, Andrei (2021-08-19). "Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed" (in en). https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures.
22. ↑ Pirzada, Usman (2020-10-07). "Intel Sapphire Rapids: MCM Design, 56 Golden Cove Cores, 64GB HBM2 On-Board Memory, Massive IPC Improvement and 400 Watt TDP" (in en-US). https://wccftech.com/intel-sapphire-rapids-mcm-design-56-golden-cove-cores-64gb-hbm2-on-board-memory-massive-ipc-improvement-and-400-watt-tdp/.
23. ↑ "Intel Software Development Emulator". http://software.intel.com/en-us/articles/intel-software-development-emulator.
24. ↑ ""Goldmont"- the sequel to Silvermont Atom?". 23 July 2013. https://forums.anandtech.com/threads/goldmont-the-sequel-to-silvermont-atom.2332517/.
25. ↑ 25.0 25.1 Cutress, Dr Ian. "Intel's new Atom Microarchitecture: The Tremont Core in Lakefield". https://www.anandtech.com/show/15009/intels-new-atom-microarchitecture-the-tremont-core.
26. ↑ Anton Shilov (June 19, 2007). "Intel Plans to change Itanium Micro-Architecture". X-bit Labs. http://www.xbitlabs.com/news/cpu/display/20070619230827.html.
27. ↑ David Kanter (2011-05-18). "Poulson: The Future of Itanium Servers". Realworldtech.com. https://www.realworldtech.com/poulson/. Retrieved 2022-05-08.
28. ↑ "Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing". http://www.intel.com/pressroom/archive/releases/20060105corp.htm.
29. ↑ "Intel Unveils World's Best Processor". http://www.intel.com/pressroom/archive/releases/20060727comp.htm.
30. ↑ "Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology". http://www.intel.com/pressroom/archive/releases/20080107comp.htm.
31. ↑ "Intel Launches Fastest Processor on the Planet". http://www.intel.com/pressroom/archive/releases/2008/20081117comp_sm.htm.
32. ↑ Mark Bohr (Intel Senior Fellow, Logic Technology Development) (2009-02-10). "Intel 32nm Technology". http://download.intel.com/pressroom/kits/32nm/westmere/Mark_Bohr_32nm.pdf.
33. ↑ "Intel - Data Center Solutions, IoT, and PC Innovation". http://www.intel.com/technology/architecture-silicon/32nm/index.htm.
34. ↑ "Intel Sandy Bridge chip coming January 5". http://news.cnet.com/8301-13924_3-20022893-64.html.
35. ↑ Pop, Sebastian (9 April 2012). "Intel Ivy Bridge CPU Range Complete by Next Year". http://news.softpedia.com/news/Intel-Ivy-Bridge-CPU-Range-Complete-by-Next-Year-263451.shtml.
36. ↑ "Ivy Bridge-E delayed until second half of 2013". 19 March 2012. http://www.techspot.com/news/47849-ivy-bridge-e-delayed-until-second-half-of-2013.html.
37. ↑ 37.0 37.1 "Ivy Bridge EP and EX coming up in a year's time - the multi-socket platform heaven". 9 April 2012. http://vr-zone.com/articles/ivy-bridge-ep-and-ex-coming-up-in-a-year-s-time--the-multi-socket-platform-heaven/15488.html.
38. ↑ 38.0 38.1 "Leaked specifications of Haswell GT1/GT2/GT3 IGP". Tech News Pedia. 2012-05-20. http://technewspedia.com/leaked-specifications-of-haswell-gt1gt2gt3-igp.
39. ↑ 39.0 39.1 "Intel to release 22-core Xeon E5 v4 "Broadwell-EP" late in 2015 - KitGuru". http://www.kitguru.net/components/cpu/anton-shilov/intel-to-release-22-core-xeon-e5-v4-broadwell-ep-late-in-2015-company/.
40. ↑ "The wait for Skylake is almost over, first desktop chips likely to hit August 5". 6 July 2015. http://www.digitaltrends.com/computing/unlocked-intel-skylake-s-processors-reportedly-coming-august-5th/.
41. ↑ 41.0 41.1 Mujtaba, Hassan (25 April 2017). "Intel X299 HEDT Platform For Skylake X and Kaby Lake X Processors Announcement on 30th May, Launch on 26th June – Reviews Go Live on 16th June". https://wccftech.com/intel-x299-hedt-skylake-x-kaby-lake-x-launch-26-june-nda/.
42. ↑ Windeck, Christof (30 April 2017). "Intel Xeon Gold, Platinum: Skylake-SP für Server "Mitte Sommer"". https://www.heise.de/newsticker/meldung/Intel-Xeon-Gold-Platinum-Skylake-SP-fuer-Server-Mitte-Sommer-3700559.html.
43. ↑ "Coffee Lake: Intels 6C-Prozessoren erfordern neue Boards - Golem.de". https://www.golem.de/news/coffee-lake-intels-6c-prozessoren-erfordern-neue-boards-1708-129594.html.
44. ↑ 44.0 44.1 online, heise (21 August 2019). "Comet Lake-U: 15-Watt-CPUs für Notebook-CPUs mit sechs Kernen" (in de). https://www.heise.de/newsticker/meldung/Comet-Lake-U-15-Watt-CPUs-fuer-Notebook-CPUs-mit-sechs-Kernen-4501680.html.
45. ↑ "Intel streicht Cooper-Lake-Prozessoren für viele Server" (in de). 17 March 2020. https://www.heise.de/newsticker/meldung/Intel-streicht-Cooper-Lake-Prozessoren-fuer-viele-Server-4684519.html.
46. ↑ Kennedy, Patrick (2020-03-16). "Intel Cooper Lake Rationalized Still Launching 1H 2020" (in en-US). https://www.servethehome.com/intel-cooper-lake-rationalized-still-launching-1h-2020/.
47. ↑ "Intel's 11th Gen Processor (Rocket Lake-S) Architecture Detailed" (in en-US). https://newsroom.intel.com/news/intels-11th-gen-processor-rocket-lake-s-architecture-detailed/.
48. ↑ "Intel "Rocket Lake-S": 11. Core-i-Generation mit mehr Rechenleistung pro Takt" (in de). 29 October 2020. https://www.heise.de/news/Intel-Rocket-Lake-S-11-Core-i-Generation-mit-mehr-Rechenleistung-pro-Takt-4942543.html.
49. ↑ Bright, Peter (2018-12-12). "Intel unveils a new architecture for 2019: Sunny Cove" (in en-us). https://arstechnica.com/gadgets/2018/12/intel-unveils-a-new-architecture-for-2019-sunny-cove/.
50. ↑ 50.0 50.1 "Ice Lake Processor Family" (in en). https://www.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html.
51. ↑ "Server-CPUs: Cooper Lake und Ice Lake nutzen gleichen Sockel - Golem.de" (in de-DE). https://www.golem.de/news/server-cpus-cooper-lake-und-ice-lake-nutzen-gleichen-sockel-1808-135909.html.
52. ↑ "Intel Launches Lakefield Hybrid Processors: Uncompromised PC Experiences for Innovative Form-Factors". 2020-06-10. https://www.techpowerup.com/268337/intel-launches-lakefield-hybrid-processors-uncompromised-pc-experiences-for-innovative-form-factors.
53. ↑ "Intels neuer Anlauf mit "Sunny Cove", Gen-11-GPU und Chiplets" (in de). 12 December 2018. https://www.heise.de/newsticker/meldung/Intels-neuer-Anlauf-mit-Sunny-Cove-Gen-11-GPU-und-Chiplets-4248713.html.
54. ↑ "Intel Innovation 2023: Empowering Developers to Bring AI Everywhere". https://www.intel.com/content/www/us/en/newsroom/news/2023-intel-innovation-day-1-all-news.html.
55. ↑ "Intel® Core™ Ultra Processors (Series 2) Product Specifications" (in en). https://www.intel.com/content/www/us/en/ark/products/series/241071/intel-core-ultra-processors-series-2.html.
56. ↑ Mujtaba, Hassan (17 February 2022). "Intel Client & Server CPU Roadmap Updates: Meteor Lake In 2023, 20A & 18A Powered Xeons & Core Chips Beyond 2024". https://wccftech.com/intel-client-server-cpu-roadmap-updates-meteor-lake-in-2023-20a-18a-powered-xeons-core-chips-beyond-2024/.
57. ↑ Wiggers, Kyle (6 January 2025). "Intel shows off its latest chip lineup at CES 2025". https://techcrunch.com/2025/01/06/intel-shows-off-its-latest-chip-lineup-at-ces-2025/.
58. ↑ 58.0 58.1 "Intel's Silvermont Architecture Revealed: Getting Serious About Mobile". http://www.anandtech.com/show/6936/intels-silvermont-architecture-revealed-getting-serious-about-mobile.
59. ↑ Hiroshige, Goto. "Intel Products for Tablets & SmartPhones". 標準. Impress. http://pc.watch.impress.co.jp/video/pcw/docs/569/575/p2.pdf.
60. ↑ "Import Data and Price of anniedale". https://www.zauba.com/import-anniedale-hs-code.html.
61. ↑ "アウトオブオーダーと最新プロセスを採用する今後のAtom". 30 November 2012. http://pc.watch.impress.co.jp/docs/column/ubiq/20121130_576105.html.
62. ↑ "Products (Formerly Braswell)". http://ark.intel.com/products/codename/66094/Braswell#@All.
63. ↑ Smith, Ryan; Cutress, Ian (29 April 2016). "Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Canceled". Anandtech.com. http://www.anandtech.com/show/10288/intel-broxton-sofia-smartphone-socs-cancelled.
64. ↑ "Products (Formerly Apollo Lake)". http://ark.intel.com/products/codename/80644/Apollo-Lake.
65. ↑ "Products (Formerly Denverton)". https://ark.intel.com/products/codename/63508/Denverton.
66. ↑ Shilov, Anton (December 12, 2017). "Intel Launches New Pentium Silver and Celeron Atom Processors: Gemini Lake is Here". https://www.anandtech.com/show/12146/intel-launches-gemini-lake-pentium-silver-and-celeron-socs-new-cpu-media-features.
67. ↑ "Products (Formerly Gemini Lake)". https://ark.intel.com/products/codename/83915/Gemini-Lake.
68. ↑ "Products (Formerly Gemini Lake Refresh)". https://ark.intel.com/content/www/us/en/ark/products/codename/197862/gemini-lake-refresh.html.
69. ↑ "Products formerly Lakefield". https://ark.intel.com/content/www/us/en/ark/products/codename/81657/lakefield.html.
70. ↑ "Products formerly Elkhart Lake". https://ark.intel.com/content/www/us/en/ark/products/codename/128825/elkhart-lake.html.
71. ↑ "Products formerly Jasper Lake". https://ark.intel.com/content/www/us/en/ark/products/codename/128823/jasper-lake.html.
72. ↑ "Products formerly Parker Ridge". https://ark.intel.com/content/www/us/en/ark/products/codename/229610/products-formerly-parker-ridge.html.
73. ↑ "Products formerly Snow Ridge". https://ark.intel.com/content/www/us/en/ark/products/codename/87586/snow-ridge.html.
74. ↑ "Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed". https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/4.
75. ↑ "Products formerly Alder Lake". https://ark.intel.com/content/www/us/en/ark/products/codename/147470/alder-lake.html.
76. ↑ "Intel Introduces New Intel Processor for Upcoming Essential Segment". https://www.intel.com/content/www/us/en/newsroom/news/welcome-the-new-intel-processor.html.
77. ↑ "Products formerly Alder Lake-N". https://ark.intel.com/content/www/us/en/ark/products/codename/232598/products-formerly-alder-laken.html.
78. ↑ "Intel Processor N150". https://www.notebookcheck.net/Intel-Processor-N150-Processor-Benchmarks-and-Specs.951351.0.html.

## External links

* Intel Automated Relational Knowledgebase

* v
* t
* e

Intel CPU core roadmaps from P6 to Tiger Lake

| Atom (ULV) |  | Feature size |  | x86 |

|
|
|
|
|

Microarchi. | Step | Microarchi. | Step
| 600 nm | P6 | Pentium Pro
(133 MHz)
500 nm | Pentium Pro
(150 MHz)
350 nm | Pentium Pro
(166–200 MHz)
Klamath
250 nm | Deschutes
Katmai |  | NetBurst |
180 nm | Coppermine | Willamette
130 nm | Tualatin | Northwood
Banias |  | NetBurst(HT) |  | NetBurst(×2)
90 nm | Dothan | Prescott | ⇨ | Prescott‑2M | ⇨ | Smithfield
~~Tejas~~ | -> | ⇩ | -> | ~~Cedarmill (Tejas)~~
65 nm | Yonah | ~~Nehalem (NetBurst)~~ |  | Cedar Mill | ⇨ | Presler
Core | Merom | (x86-64) DDR2 \+ DDR3, 4 cores on mainstream desktop
Bonnell | Bonnell | 45 nm | Penryn |
Nehalem | Nehalem | HT reintroduced, integrated MC, PCH,
L3-cache introduced, 256KiB L2-cache/core, DDR3
Saltwell | 32 nm | Westmere | GPU on same package in 45nm, AES-NI introduced
Sandy Bridge | Sandy Bridge | on-die ring bus, GPU on die, no more non-UEFI motherboards, DDR3
Silvermont | Silvermont | 22 nm | Ivy Bridge |
Haswell | Haswell | FIVR, DDR3 \+ DDR3L
Airmont | 14 nm | Broadwell |
Skylake | Skylake | DDR3L \+ DDR4
Goldmont | Goldmont | Kaby Lake |
Coffee Lake | DDR4, 6 cores on mainstream desktop
Amber Lake |
Goldmont Plus | Whiskey Lake |
Coffee Lake Refresh | 8 cores on mainstream desktop
Comet Lake | 10 cores on mainstream desktop
Rocket Lake |
Tremont | Tremont | 10 nm | Cannon Lake |  | Hybrid
Sunny Cove | Ice Lake | 512KiB L2-cache/core | Lakefield
Gracemont | Willow Cove | Tiger Lake | Xe graphics engine |
Golden Cove | ? |  |

* ~~Strike-through~~ indicates cancelled processors
* Bold names are the microarchitecture names
* Italic names are future processors

* v
* t
* e

Intel processors

Discontinued

BCD oriented (4-bit)|

* 4004 (1971)
* 4040 (1974)

pre-x86 (8-bit)|

* 8008 (1972)
* 8080 (1974)
* 8085 (1977)

Early x86 (16-bit)|

* 8086 (1978)
* 8088 (1979)
* 80186 (1982)
* 80188 (1982)
* 80286 (1982)

x87 (external FPUs)|

8/16-bit databus
8087 (1980)
16-bit databus
80187
80287
80387SX
32-bit databus
80387DX
80487

IA-32 (32-bit)|

* 80386
* SX
* 376
* EX
* 80486
* SX
* DX2
* DX4
* SL
* RapidCAD
* OverDrive
* A100/A110
* Celeron (1998)
* M
* D (2004)
* Pentium
* Original P5
* OverDrive
* Pro
* II
* II OverDrive
* III
* 4
* M
* Dual-Core
* some Core
* Solo
* Duo
* Tolapai

x86-64 (64-bit)|

* Celeron
* D
* Dual-Core
* Pentium
* 4
* D
* Extreme Edition
* Dual-Core
* some Core
* 2
* some i7

Other|

CISC
iAPX 432
Itanium
RISC
i860
i960
StrongARM
XScale

Current

IA-32 (32-bit)|

* Atom
* CE
* SoC
* Quark

x86-64 (64-bit)|

* Atom
* CE
* SoC
* Celeron
* Pentium
* Core
* i3
* i5
* i7
* i9
* M
* Xeon
* E3
* E5
* E7
* D
* Phi

Lists

* Celeron
* Pentium
* Pro
* II
* III
* 4
* D
* M
* Core
* Core
* 2
* i3
* i5
* i7
* i9
* M
* Atom
* Xeon
* Itanium

Related

* Tick–tock model
* Chipsets
* GPUs
* GMA
* HD and Iris Graphics
* PCHs
* SCHs
* ICHs
* PIIXs
* Stratix
* Codenames

Microarchitectures

x86|

| P5|

800 nm

600 nm
P54C
350 nm
P54CS
P55C
250 nm
Tillamook

|

P6, Pentium M,
Enhanced Pentium M|

500 nm

350 nm

Klamath
250 nm
Mendocino
Dixon
Tonga
Covington
Deschutes
Katmai
Drake
Tanner
180 nm
Coppermine
Coppermine T
Timna
Cascades
130 nm
Tualatin
Banias
90 nm
Dothan
Stealey
Tolapai
Canmore
65 nm
Yonah
Sossaman

NetBurst|

180 nm
Willamette
Foster
130 nm
Northwood
Gallatin
Prestonia
90 nm
Tejas and Jayhawk
Prescott
Smithfield
Nocona
Irwindale
Cranford
Potomac
Paxville
65 nm
Cedar Mill
Presler
Dempsey
Tulsa

Core|

65 nm
Merom-L
Merom
Conroe-L
Allendale
Conroe
Kentsfield
Woodcrest
Clovertown
Tigerton

45 nm
Penryn
Penryn-QC
Wolfdale
Yorkfield
Wolfdale-DP
Harpertown
Dunnington

Nehalem|

45 nm
Auburndale
Beckton (Nehalem-EX)
Bloomfield
Clarksfield
Gainestown (Nehalem-EP)
Havendale
Jasper Forest
Lynnfield

32 nm
Arrandale
Clarkdale
Gulftown (Westmere-EP)
Westmere-EX

Sandy Bridge|

32 nm
Sandy Bridge
Sandy Bridge-E
Gladden

22 nm
Ivy Bridge
Ivy Bridge-EP
Ivy Bridge-EX

Haswell|

22 nm
Haswell

14 nm
Broadwell

Skylake|

14 nm
Skylake
Kaby Lake (Amber Lake • Whiskey Lake)
Coffee Lake
Cascade Lake
Comet Lake

Palm Cove|

10 nm
Cannon Lake

Sunny Cove|

14 nm
Cooper Lake

10 nm
Ice Lake

Willow Cove|

14 nm
Rocket Lake

10 nm
Tiger Lake
Sapphire Rapids

Golden Cove|

7 nm
Alder Lake
Granite Rapids

Atom|

| Bonnell
Saltwell|

45 nm
Silverthorne
Diamondville
Pineview
Lincroft
Tunnel Creek
Stellarton
Sodaville
Groveland

32 nm
Cedarview
Penwell
Cloverview
Berryville
Centerton

|

Silvermont
Airmont|

22 nm
Valleyview
Tangier
Anniedale

14 nm
Cherryview

Goldmont|

14 nm
Goldmont
Goldmont Plus

Tremont|

10 nm
Tremont
Gracemont

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