Page (computer memory)

Short description: Fixed-length contiguous block of virtual memory

Not to be confused with Bank (computer memory) or Block (computer memory).

A page, memory page, or virtual page is a fixed-length contiguous block of virtual memory, described by a single entry in a page table. It is the smallest unit of data for memory management in an operating system that uses virtual memory. Similarly, a page frame is the smallest fixed-length contiguous block of physical memory into which memory pages are mapped by the operating system.[1][2][3]

A transfer of pages between main memory and an auxiliary store, such as a hard disk drive, is referred to as paging or swapping.[4]

## Contents

* 1 Explanation
* 2 Page size
* 2.1 Page size trade-off
* 2.1.1 Page table size
* 2.1.2 TLB usage
* 2.1.3 Internal fragmentation
* 2.1.4 Disk access
* 2.2 Getting page size programmatically
* 2.2.1 Unix and POSIX-based operating systems
* 2.2.2 Windows-based operating systems
* 2.3 Multiple page sizes
* 3 See also
* 4 References
* 5 Further reading

## Explanation

Computer memory is divided into pages so that information can be found more quickly.

The concept is named by analogy to the pages of a printed book. If a reader wanted to find, for example, the 5,000th word in the book, they could count from the first word. This would be time-consuming. It would be much faster if the reader had a listing of how many words are on each page. From this listing they could determine which page the 5,000th word appears on, and how many words to count on that page. This listing of the words per page of the book is analogous to a page table of a computer file system.[5]

## Page size

### Page size trade-off

Page size is usually determined by the processor architecture. Traditionally, pages in a system had uniform size, such as 4,096 bytes. However, processor designs often allow two or more, sometimes simultaneous, page sizes due to its benefits. There are several points that can factor into choosing the best page size.[6]

#### Page table size

A system with a smaller page size uses more pages, requiring a page table that occupies more space. For example, if a 232 virtual address space is mapped to 4 KiB (212 bytes) pages, the number of virtual pages is 220 = (232 / 212). However, if the page size is increased to 32 KiB (215 bytes), only 217 pages are required. A multi-level paging algorithm can decrease the memory cost of allocating a large page table for each process by further dividing the page table up into smaller tables, effectively paging the page table.

#### TLB usage

Since every access to memory must be mapped from virtual to physical address, reading the page table every time can be quite costly. Therefore, a very fast kind of cache, the translation lookaside buffer (TLB), is often used. The TLB is of limited size, and when it cannot satisfy a given request (a TLB miss) the page tables must be searched manually (either in hardware or software, depending on the architecture) for the correct mapping. Larger page sizes mean that a TLB cache of the same size can keep track of larger amounts of memory, which avoids the costly TLB misses.

#### Internal fragmentation

Rarely do processes require the use of an exact number of pages. As a result, the last page will likely only be partially full, wasting some amount of memory. Larger page sizes lead to a large amount of wasted memory, as more potentially unused portions of memory are loaded into the main memory. Smaller page sizes ensure a closer match to the actual amount of memory required in an allocation.

As an example, assume the page size is 1024 B. If a process allocates 1025 B, two pages must be used, resulting in 1023 B of unused space (where one page fully consumes 1024 B and the other only 1 B).

#### Disk access

When transferring from a rotational disk, much of the delay is caused by seek time, the time it takes to correctly position the read/write heads above the disk platters. Because of this, large sequential transfers are more efficient than several smaller transfers. Transferring the same amount of data from disk to memory often requires less time with larger pages than with smaller pages.

### Getting page size programmatically

Most operating systems allow programs to discover the page size at runtime. This allows programs to use memory more efficiently by aligning allocations to this size and reducing overall internal fragmentation of pages.

#### Unix and POSIX-based operating systems

Unix and POSIX-based systems may use the system function `sysconf()`,[7][8][9][10][11] as illustrated in the following example written in the C programming language.

#include <stdio.h>
#include <unistd.h> /* sysconf(3) */

int main(void)

printf("The page size for this system is %ld bytes.\n",
sysconf(_SC_PAGESIZE)); /* _SC_PAGE_SIZE is OK too. */

return 0;

In many Unix systems, the command-line utility `getconf` can be used.[12][13][14] For example, `getconf PAGESIZE` will return the page size in bytes.

#### Windows-based operating systems

Win32-based operating systems, such as those in the Windows 9x and Windows NT families, may use the system function `GetSystemInfo()`[15][16] from `kernel32.dll`.

#include <stdio.h>
#include <windows.h>

int main(void)

SYSTEM_INFO si;
GetSystemInfo(&si);

printf("The page size for this system is %u bytes.\n", si.dwPageSize);

return 0;

### Multiple page sizes

Some instruction set architectures can support multiple page sizes, including pages significantly larger than the standard page size. The available page sizes depend on the instruction set architecture, processor type, and operating (addressing) mode. The operating system selects one or more sizes from the sizes supported by the architecture. Note that not all processors implement all defined larger page sizes. This support for larger pages (known as "huge pages" in Linux, "superpages" in FreeBSD, and "large pages" in Microsoft Windows and IBM AIX terminology) allows for "the best of both worlds", reducing the pressure on the TLB cache (sometimes increasing speed by as much as 15%) for large allocations while still keeping memory usage at a reasonable level for small allocations.

Page sizes among architectures[17] Architecture | Smallest page size | Larger page sizes

|
|

IA-32 (32-bit x86)[18] | 4 KiB | 4 MiB in PSE mode, 2 MiB in PAE mode[19]
x86-64[18] | 4 KiB | 2 MiB, 1 GiB (only when the CPU has `PDPE1GB` flag)
IA-64 (Itanium)[20] | 4 KiB | 8 KiB, 64 KiB, 256 KiB, 1 MiB, 4 MiB, 16 MiB, 256 MiB[19]
Power ISA[21] | 4 KiB | 64 KiB, 16 MiB, 16 GiB
SPARC v8 with SPARC Reference MMU[22] | 4 KiB | 256 KiB, 16 MiB
UltraSPARC Architecture 2007[23] | 8 KiB | 64 KiB, 512 KiB (optional), 4 MiB, 32 MiB (optional), 256 MiB (optional), 2 GiB (optional), 16 GiB (optional)
ARMv7[24] | 4 KiB | 64 KiB, 1 MiB ("section"), 16 MiB ("supersection") (defined by a particular implementation)
AArch64[25] | 4 KiB | 16 KiB, 64 KiB, 2 MiB, 32 MiB, 512 MiB, 1 GiB
RISCV32[26] | 4 KiB  | 4 MiB ("megapage")
RISCV64[26] | 4 KiB  | 2 MiB ("megapage"), 1 GiB ("gigapage"), 512 GiB ("terapage", only for CPUs with 43-bit address space or more), 256 TiB ("petapage", only for CPUs with 57-bit address space or more),

Starting with the Pentium Pro, and the AMD Athlon, x86 processors support 4 MiB pages (called Page Size Extension) (2 MiB pages if using PAE) in addition to their standard 4 KiB pages; newer x86-64 processors, such as AMD's newer AMD64 processors and Intel's Westmere[27] and later Xeon processors can use 1 GiB pages in long mode. IA-64 supports as many as eight different page sizes, from 4 KiB up to 256 MiB, and some other architectures have similar features.[specify]

Larger pages, despite being available in the processors used in most contemporary personal computers, are not in common use except in large-scale applications, the applications typically found in large servers and in computational clusters, and in the operating system itself. Commonly, their use requires elevated privileges, cooperation from the application making the large allocation (usually setting a flag to ask the operating system for huge pages), or manual administrator configuration; operating systems commonly, sometimes by design, cannot page them out to disk.

However, SGI IRIX has general-purpose support for multiple page sizes. Each individual process can provide hints and the operating system will automatically use the largest page size possible for a given region of address space.[28] Later work proposed transparent operating system support for using a mix of page sizes for unmodified applications through preemptible reservations, opportunistic promotions, speculative demotions, and fragmentation control.[29]

Linux has supported huge pages on several architectures since the 2.6 series via the `hugetlbfs` filesystem[30] and without `hugetlbfs` since 2.6.38.[31] Windows Server 2003 (SP1 and newer), Windows Vista and Windows Server 2008 support huge pages under the name of large pages.[32] Windows 2000 and Windows XP support large pages internally, but do not expose them to applications.[33] Beginning with version 9, Solaris supports large pages on SPARC and x86.[34][35] FreeBSD 7.2-RELEASE features superpages.[36] Note that until recently in Linux, applications needed to be modified in order to use huge pages. The 2.6.38 kernel introduced support for transparent use of huge pages.[31] On Linux kernels supporting transparent huge pages, as well as FreeBSD and Solaris, applications take advantage of huge pages automatically, without the need for modification.[36]

## See also

* Page fault
* Page table
* Memory paging
* Virtual memory
* Zero page \- a (often 256-bytes large[37][38]) memory area at the very start of a processor's address room
* Zero page (CP/M) - a 256-byte[38] data structure at the start of a program

## References

1. ↑ Christopher Kruegel (2012-12-03). "Operating Systems (CS170-08 course)". https://www.cs.ucsb.edu/~chris/teaching/cs170/doc/cs170-08.pdf.
2. ↑ Martin C. Rinard (1998-08-22). "Operating Systems Lecture Notes, Lecture 9. Introduction to Paging". http://people.csail.mit.edu/rinard/osnotes/h9.html.
3. ↑ "Virtual Memory: pages and page frames". 2012-10-31. http://blog.cs.miami.edu/burt/2012/10/31/virtual-memory-pages-and-page-frames/.
4. ↑ Belzer, Jack; Holzman, Albert G.; Kent, Allen, eds. (1981), "Virtual memory systems", Encyclopedia of computer science and technology, 14, CRC Press, p. 32, ISBN 0-8247-2214-0, https://books.google.com/books?id=KUgNGCJB4agC
5. ↑ Kazemi, Darius (11 January 2019). "RFC-11". https://write.as/365-rfcs/rfc-11.
6. ↑ Weisberg, P.; Wiseman, Y. (2009-08-10). "Using 4KB Page Size for Virtual Memory is Obsolete". 2009 IEEE International Conference on Information Reuse & Integration. doi:10.1109/IRI.2009.5211562.
7. ↑ `limits.h` – Base Definitions Reference, The Single UNIX Specification, Issue 7 from The Open Group
8. ↑ `sysconf` – System Interfaces Reference, The Single UNIX Specification, Issue 7 from The Open Group
9. ↑ `sysconf(3)` – Linux Library Functions Manual
10. ↑ `sysconf(3)` – Darwin and macOS Library Functions Manual
11. ↑ `sysconf(3C)` – Solaris 10 Basic Library Functions Reference Manual
12. ↑ `getconf` – Commands & Utilities Reference, The Single UNIX Specification, Issue 7 from The Open Group
13. ↑ `getconf(1)` – Linux User Commands Manual
14. ↑ `getconf(1)` – Darwin and macOS General Commands Manual
15. ↑ "GetSystemInfo function". Microsoft. 13 October 2021. http://msdn.microsoft.com/en-us/library/windows/desktop/ms724381(v=vs.85).aspx.
16. ↑ "SYSTEM_INFO structure". Microsoft. 23 September 2022. http://msdn.microsoft.com/en-us/library/windows/desktop/ms724958(v=vs.85).aspx.
17. ↑ "Hugepages - Debian Wiki". Wiki.debian.org. 2011-06-21. http://wiki.debian.org/Hugepages.
18. ↑ 18.0 18.1 "Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide". December 2016. p. 4-2. https://software.intel.com/sites/default/files/managed/a4/60/325384-sdm-vol-3abcd.pdf.
19. ↑ 19.0 19.1 "Documentation/vm/hugetlbpage.txt". Linux kernel documentation. kernel.org. https://www.kernel.org/doc/Documentation/vm/hugetlbpage.txt.
20. ↑ "Intel Itanium Architecture Software Developer's Manual Volume 2: System Architecture". May 2010. p. 2:58. http://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-software-developer-rev-2-3-vol-2-manual.pdf.
21. ↑ IBM Power Systems Performance Guide: Implementing and Optimizing. IBM Redbooks. February 2013. ISBN 978-0-7384-3766-8. https://books.google.com/books?id=lHTJAgAAQBAJ&q=ibm+power+large+page&pg=PA138. Retrieved 2014-03-17.
22. ↑ "The SPARC Architecture Manual, Version 8". 1992. p. 249. http://sparc.org/wp-content/uploads/2014/01/v8.pdf.gz.
23. ↑ "UltraSPARC Architecture 2007". September 27, 2010. p. 427. http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-arch-2007-2516668.pdf.
24. ↑ "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition". Arm. May 20, 2014. p. B3-1324. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architecture/index.html.
25. ↑ "Translation granule". Learn the architecture - AArch64 memory management. Arm. https://developer.arm.com/documentation/101811/0102/Translation-granule.
26. ↑ 26.0 26.1 Waterman, Andrew; Asanović, Krste; Hauser, John (2021). The RISC-V Instruction Set Manual Volume II: Privileged Architecture. pp. 79–87. https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf.
27. ↑ "The Intel Xeon 5670: Six Improved Cores". AnandTech. http://anandtech.com/show/2964/.
28. ↑ "General Purpose Operating System Support for Multiple Page Sizes". http://static.usenix.org/publications/library/proceedings/usenix98/full_papers/ganapathy/ganapathy.pdf.
29. ↑ Navarro, Juan; Iyer, Sitararn; Druschel, Peter; Cox, Alan (December 2002). "Practical, Transparent Operating System Support for Superpages". 5th Usenix Symposium on Operating Systems Design and Implementation. https://people.mpi-sws.org/~druschel/publications/superpages.pdf.
30. ↑ "Pages - dankwiki, the wiki of nick black". https://nick-black.com/dankwiki/index.php/Pages.
31. ↑ 31.0 31.1 Corbet, Jonathan. "Transparent huge pages in 2.6.38". LWN. https://lwn.net/Articles/423584.
32. ↑ "Large-Page Support". May 8, 2018. https://docs.microsoft.com/en-us/windows/win32/memory/large-page-support.
33. ↑ "AGP program may hang when using page size extension on Athlon processor". Support.microsoft.com. 2007-01-27. http://support.microsoft.com/kb/270715.
34. ↑ "Supporting Multiple Page Sizes in the Solaris Operating System". Sun BluePrints Online. Sun Microsystems. http://www.sun.com/blueprints/0304/817-5917.pdf.
35. ↑ "Supporting Multiple Page Sizes in the Solaris Operating System Appendix". Sun BluePrints Online. Sun Microsystems. http://www.sun.com/blueprints/0304/817-6242.pdf.
36. ↑ 36.0 36.1 "FreeBSD 7.2-RELEASE Release Notes". FreeBSD Foundation. http://www.freebsd.org/releases/7.2R/relnotes-detailed.html.
37. ↑ "2.3.1 Read-Only Memory / 2.3.2 Program Random Access Memory". MCS-4 Assembly Language Programming Manual - The INTELLEC 4 Microcomputer System Programming Manual (Preliminary ed.). Santa Clara, California, USA: Intel Corporation. December 1973. pp. 2-3 – 2-4. MCS-030-1273-1. http://bitsavers.trailing-edge.com/components/intel/MCS4/MCS-4_Assembly_Language_Programming_Manual_Dec73.pdf. Retrieved 2020-03-02. "[…] ROM is further divided into pages, each of which contains 256 bytes. Thus locations 0 through 255 comprise page 0 of ROM, location 256 through 511 comprise page 1 and so on. […] Program random access memory (RAM) is organized exactly like ROM. […]"
38. ↑ 38.0 38.1 "1. Introduction: Segment Alignment". 8086 Family Utilities - User's Guide for 8080/8085-Based Development Systems (A620/5821 6K DD ed.). Santa Clara, California, USA: Intel Corporation. May 1982. p. 1-6. Order Number: 9800639-04. http://bitsavers.trailing-edge.com/pdf/intel/ISIS_II/9800639-04E_8086_Famility_Utilities_Users_Guide_May82.pdf. Retrieved 2020-02-29.

## Further reading

* Dandamudi, Sivarama P. (2003). Fundamentals of Computer Organization and Design (1st ed.). Springer. pp. 740–741. ISBN 0-387-95211-X.

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