ST6 and ST7

Short description: 8-bit microcontroller product lines from STMicroelectronics

Not to be confused with ST6 or ST7.

ST62E40 microcontroller, based on the ST6 architecture

The ST6 and ST7 are 8-bit microcontroller product lines from STMicroelectronics. They are commonly used in small embedded applications like washing machines.

Although they use similar peripherals and are marketed as part of the same product line,[1][2] the two architectures are actually quite different.

Both have an 8-bit accumulator used for most operations, plus two 8-bit index registers (X and Y) used for memory addressing. Also both have 8-bit instructions followed by up to 2 bytes of operands, and both have support for manipulating and branching on individual bits of memory.

There, the similarities end.

The ST6 is a Harvard architecture with an 8-bit (256 byte) data address space and a separate 12-bit (4096 byte) program space. Operands are always 1 byte long, and some instructions support two operands, such as "move 8-bit immediate to 8-bit memory address". Subroutine calls are done using a separate hardware stack. Data registers (but not the program counter or flags) are memory-mapped.

The ST6's addressing modes are limited to immediate, 8-bit absolute memory address, and register indirect modes (X) and (Y).

The ST7 is a von Neumann architecture with a single 16-bit (64 kiB) address space. The first 256 bytes of RAM (the zero page) have extra flexibility. There are no two-operand instructions except for "test bit and branch". Its registers are not memory-mapped, and it uses general-purpose RAM (plus a stack pointer register) for subroutine calls.

The ST7 supports a wide variety of addressing modes, including base+index and double-indirect.

Three members of the ST6 microcontroller family: ST62E01, ST62E20, ST62E25

## ST6 architecture

The ST6 has 64 bytes of RAM and 4096 bytes of program ROM. Larger amounts are accessed by bank-switching the low 2K section of the ROM.

The RAM address space is actually 256 bytes, divided as follows:

* 0-63: Not implemented
* 64-127: Bank-switchable window into program ROM and data EPROM.
* 128-191: General-purpose RAM
* 192-255: Peripheral control registers (GPIO ports, timers, etc.) The accumulator is mapped at address 255, but is more commonly addressed implicitly.

Not mapped into the address space is a 12-bit program counter and an associated hardware stack (four or six levels deep, depending on model). There are only two status bits (carry and zero), and they are banked based on processor mode, with separate status bits for normal, interrupt and non-maskable interrupt operation.

The first four general-purpose RAM locations are also known as the X, Y, V and W registers, and some instructions can access them using special short addressing modes. The X and Y registers serve as index registers, and can use indirect addressing modes `(X)` and `(Y)`.

The instruction set consists of one byte of opcode, followed by up to two one-byte operands. The instruction set can be summarized as follows:

ST6 family instruction set[3] 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | Mnemonic | C | Z | Description

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offset | opc | 0 | -- | -- | Conditional branches (5-bit PC-relative)
offset | 0 | 0 | 0 | -- | -- | JRNZ address |  |  | Jump to PC + simm5 if Z == 0
offset | 1 | 0 | 0 | -- | -- | JRZ address |  |  | Jump to PC + simm5 if Z == 1
offset | 0 | 1 | 0 | -- | -- | JRNC address |  |  | Jump to PC + simm5 if C == 0
offset | 1 | 1 | 0 | -- | -- | JRC address |  |  | Jump to PC + simm5 if C == 1
imm4 | c | 0 | 0 | 1 | imm8 | -- | Unconditional branches (12-bit absolute)
imm4 | 0 | 0 | 0 | 1 | imm8 | -- | CALL imm12 |  |  | Push PC, jump to 12-bit address
imm4 | 1 | 0 | 0 | 1 | imm8 | -- | JP imm12 |  |  | Jump to 12-bit address
-- | 0 | 0 | 1 | 0 | 1 | -- | -- | (reserved)
reg | c | 1 | c | 1 | 0 | 1 | -- | -- | Register operations (on X, Y, V or W)
reg | 0 | 1 | 0 | 1 | 0 | 1 | -- | -- | INC reg | Z |  | Increment register. Z is set, C is not.
reg | 1 | 1 | 0 | 1 | 0 | 1 | -- | -- | LD A,reg | Z |  | A := {X, Y, V or W}
reg | 0 | 1 | 1 | 1 | 0 | 1 | -- | -- | DEC reg | Z |  | Decrement register. Z is set, C is not.
reg | 1 | 1 | 1 | 1 | 0 | 1 | -- | -- | LD reg,A | Z |  | {X, Y, V or W} := A
opcode | 0 | 1 | 1 | 0 | 1 | -- | -- | Miscellaneous operations
0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | addr | imm8 | LDI addr,imm8 |  |  | Set RAM to 8-bit immediate value
1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | -- | -- | (reserved)
0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | -- | -- | RETI |  |  | Return from interrupt. Pop PC, restore flags.
1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | -- | -- | RET |  |  | Return from subroutine. Pop PC from hardware stack.
0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | -- | -- | COM A | Z | C | Complement: C := msbit(A); A := ~A
1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | -- | -- | RLC A |  | C | A := A + A + C
0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | -- | -- | STOP |  |  | Halt processor, clock, most peripherals until next interrupt
1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | -- | -- | WAIT |  |  | Halt processor until next interrupt; clock continues
bit | opc | 0 | 1 | 1 | address | ? | Bit operations (absolute address only)
bit | 0 | 0 | 0 | 1 | 1 | src | simm8 | JRR bit,src,address |  | C | C := src.bit; jump to PC+simm8 if reset (clear)
bit | 1 | 0 | 0 | 1 | 1 | src | simm8 | JRS bit,src,address |  | C | C := src.bit; jump to PC+simm8 if set
bit | 0 | 1 | 0 | 1 | 1 | dst | -- | RES bit,dst |  |  | Reset (set to 0) dst.bit
bit | 1 | 1 | 0 | 1 | 1 | dst | -- | SET bit,dst |  |  | Set (to 1) dst.bit
opcode | data | 1 | 1 | 1 | ? | -- | ALU operations with RAM or immediate
opcode | 0 | 0 | 1 | 1 | 1 | -- | -- | (X) |  |  | Operand is (X)
opcode | 0 | 1 | 1 | 1 | 1 | -- | -- | (Y) |  |  | Operand is (Y)
opcode | 1 | 0 | 1 | 1 | 1 | imm8 | -- | imm8 |  |  | Operand is 8-bit immediate (source only)
opcode | 1 | 1 | 1 | 1 | 1 | addr | -- | addr |  |  | Operand is 8-bit RAM address
0 | 0 | 0 | src | 1 | 1 | 1 | ? | -- | LD A,src | Z |  | A := src
1 | 0 | 0 | dst | 1 | 1 | 1 | ? | -- | LD dst,A | Z |  | dst := A (immediate forbidden)
0 | 1 | 0 | src | 1 | 1 | 1 | ? | -- | ADD A,src | Z | C | A := A + src
1 | 1 | 0 | src | 1 | 1 | 1 | ? | -- | SUB A,src | Z | C† | A := A − src
0 | 0 | 1 | src | 1 | 1 | 1 | ? | -- | CP A,src | Z | C† | A − src
1 | 0 | 1 | src | 1 | 1 | 1 | ? | -- | AND A,src | Z |  | A := A & src
0 | 1 | 1 | dst | 1 | 1 | 1 | ? | -- | INC dst | Z |  | dst := dst \+ 1 (immediate forbidden)
1 | 1 | 1 | dst | 1 | 1 | 1 | ? | -- | DEC dst | Z |  | dst := dst − 1 (immediate forbidden)

†: ^ a b Confusingly, different models of the ST6 family use different conventions for the value of the carry bit after a subtraction. ST60 processors use the "carry" convention, which clears the bit if the subtract underflows, while the ST62 and ST63 processors use the "borrow" convention, which sets the bit in that case.[3]: 21–22,42

## ST7 architecture

See also: Engineering:STM8

The ST7 has six registers: the accumulator, X and Y index registers, stack pointer, program counter, and condition code register. Also, double-indirect addressing allows the zero page of RAM to serve as additional registers. An unusual but useful feature is that an interrupt pushes four of these registers on the stack (A and X as well as the usual PC and CC), and interrupt return restores them.

ALU instructions fall into two categories, two-operand and one-operand.

Two-operand instructions use the accumulator as the first source. The addressing mode specifies the second source, which may be:

* 8-bit immediate
* 8-bit absolute address
* 16-bit absolute address
* Indexed (X)
* Indexed plus 8-bit offset (address8,X)
* Indexed plus 16-bit offset (address16,X)

The destination is usually the accumulator, but a few instructions modify the second source. (Immediate operands are forbidden in such cases.)

One-operand instructions use the specified operand for both source and destination. The operand may be:

* The accumulator A
* The X register
* 8-bit absolute address
* Indexed (X)
* Indexed plus 8-bit offset (address8,X)

Register plus offset computes a full-width sum, so the 8-bit form may address memory up to 255+255 = 510.

In addition to the above, there are three prefix bytes which may be prepended to any instruction for which they make sense:

* PDY (0x90) changes all references to the X register to Y. This allows (Y), (address8,Y) and (address16,Y) addressing modes. This affects implicit operands as well, so the "load X" instruction becomes "load Y". A consequence of this is that load X can only use the X-relative addressing modes, and load Y can only use the Y-relative ones.
* PIX (0x92) adds an indirection step to the instruction. The 8- or 16-bit address following the opcode byte is replaced by an 8-bit address of a memory location which holds an 8- or 16-bit address (the latter in big-endian order). This may then be indexed by the X register as usual. This allows (address8), (address16), ([address8],X) and ([address8.w],X) addressing modes.
* PIY (0x91) combines the above effects. This allows the ([address8],Y) and ([address8.w],Y) addressing modes. (It may also be used with other modes as part of the "load Y" and "store Y" instructions.)

ST7 family instruction set[4] 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | Mnemonic | Description

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0 | 0 | 0 | c | bit | v | address | ? | Bit operations
0 | 0 | 0 | 0 | bit | 0 | addr8 | soff8 | BTJT addr8,#bit,label | Jump to PC + soff8 if source bit is true (set)
0 | 0 | 0 | 0 | bit | 1 | addr8 | soff8 | BTJF addr8,#bit,label | Jump to PC + soff8 if source bit is false (clear)
0 | 0 | 0 | 1 | bit | 0 | addr8 | -- | BSET addr8,#bit | Set specified bit to 1
0 | 0 | 0 | 1 | bit | 1 | addr8 | -- | BRES addr8,#bit | Reset (clear) specified bit to 0
0 | 0 | 1 | 0 | condition | soff8 | -- | Conditional branches (8-bit relative offset)
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | soff8 | -- | JRA label | Branch always (true)
0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | soff8 | -- | JRF label | Branch never (false)
0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | soff8 | -- | JRUGT label | Branch if unsigned greater than (C=0 and Z=0)
0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | soff8 | -- | JRULE label | Branch if unsigned less than or equal (C=1 or Z=1)
0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | soff8 | -- | JRNC label | Branch if no carry (C=0)
0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | soff8 | -- | JRC label | Branch if carry (C=1)
0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | soff8 | -- | JRNE label | Branch if not equal (Z=0)
0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | soff8 | -- | JREQ label | Branch if equal (Z=1)
0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | soff8 | -- | JRNH label | Branch if not half-carry (H=0)
0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | soff8 | -- | JRH label | Branch if half-carry (H=1)
0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | soff8 | -- | JRPL label | Branch if plus (N=0)
0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | soff8 | -- | JRMI label | Branch if minus (N=1)
0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | soff8 | -- | JRNM label | Branch if not interrupt mask (M=0)
0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | soff8 | -- | JRM label | Branch if interrupts masked (M=1)
0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | soff8 | -- | JRIL label | Branch if interrupt line is low
0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | soff8 | -- | JRIH label | Branch if interrupt line is high
0 | mode | opcode | ? | -- | One-operand instructions
0 | 0 | 1 | 1 | opcode | addr8 | -- | OP addr8 | 8-bit absolute address
0 | 1 | 0 | 0 | opcode | -- | -- | OP A | Accumulator
0 | 1 | 0 | 1 | opcode | -- | -- | OP X | X register (Y register with prefix)
0 | 1 | 1 | 0 | opcode | addr8 | -- | OP (addr8,X) | 8-bit address plus X
0 | 1 | 1 | 1 | opcode | -- | -- | OP (X) | Indexed with no offset
0 | mode | 0 | 0 | 0 | 0 | ? | -- | NEG operand | Two's-complement negate
0 | mode | 0 | 0 | 0 | 1 | ? | -- | (reserved)
0 | mode | 0 | 0 | 1 | 0 | ? | -- | (reserved)
0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | -- | -- | MUL X,A | X:A := X × A. (MUL Y,A with prefix)
0 | mode | 0 | 0 | 1 | 1 | ? | -- | CPL operand | Ones' complement, logical not
0 | mode | 0 | 1 | 0 | 0 | ? | -- | SRL operand | Shift right logical. Msbit cleared, lsbit to carry.
0 | mode | 0 | 1 | 0 | 1 | ? | -- | (reserved)
0 | mode | 0 | 1 | 1 | 0 | ? | -- | RRC operand | Rotate right through carry, (operand:C) := (C:operand)
0 | mode | 0 | 1 | 1 | 1 | ? | -- | SRA operand | Shift right arithmetic. Msbit preserved, lebit to carry.
0 | mode | 1 | 0 | 0 | 0 | ? | -- | SLL operand | Shift left. Msbit to carry.
0 | mode | 1 | 0 | 0 | 1 | ? | -- | RLC operand | Rotate left through carry.
0 | mode | 1 | 0 | 1 | 0 | ? | -- | DEC operand | Decrement. (N and Z set, carry unaffected)
0 | mode | 1 | 0 | 1 | 1 | ? | -- | (reserved)
0 | mode | 1 | 1 | 0 | 0 | ? | -- | INC operand | Increment. (N and Z set, carry unaffected)
0 | mode | 1 | 1 | 0 | 1 | ? | -- | TNZ operand | Test non-zero. Set N and Z based on operand.
0 | mode | 1 | 1 | 1 | 0 | ? | -- | SWAP operand | Swap halves of operand (4-bit rotate).
0 | mode | 1 | 1 | 1 | 1 | ? | -- | CLR operand | Set operand to 0. N and Z set to fixed values.operand.
1 | 0 | 0 | opcode | -- | -- | Miscellaneous instructions. None implicitly set the condition codes.
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -- | -- | IRET | Return from interrupt (pop CC, A, X, PC)
1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | -- | -- | RET | Return from subroutine (pop PC)
1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | -- | -- | TRAP | Force trap interrupt
1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | -- | -- | (reserved)
1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -- | -- | POP A | Pop A from stack
1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | -- | -- | POP X | Pop X from stack
1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | -- | -- | POP CC | Pop condition codes from stack
1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | -- | -- | (reserved)
1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | -- | -- | PUSH A | Push A onto stack
1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | -- | -- | PUSH X | Push X onto stack
1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | -- | -- | PUSH CC | Push condition codes onto stack
1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | -- | -- | (reserved)
1 | 0 | 0 | 0 | 1 | 1 | 0 | -- | -- | -- | (reserved)
1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | -- | -- | HALT | Halt processor and clocks
1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | -- | -- | WFI | Wait for interrupt, halting processor but not clocks
1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | -- | -- | PDY | Instruction prefix; swap X and Y in next instruction
1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | -- | -- | PIY | Instruction prefix; PDY plus PIX
1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | -- | -- | PIX | Instruction prefix; use 8-bit memory indirect for operand
1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | -- | -- | LD X,Y | X := Y. With PDY, does "LD Y,X".
1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | -- | -- | LD S,X | S := X. Load stack pointer.
1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | -- | -- | LD S,A | S := A. Load stack pointer.
1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | -- | -- | LD X,S | X := S.
1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | -- | -- | LD X,A | X := A.
1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | -- | -- | RCF | Reset (clear) carry flag
1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | -- | -- | SCF | Set carry flag
1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | -- | -- | RIM | Reset interrupt mask (enable interrupts)
1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | -- | -- | SIM | Set interrupt mask (disable interrupts)
1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | -- | -- | RSP | Reset stack pointer (to top of RAM)
1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | -- | -- | NOP | No operation. (=LD A,A)
1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | -- | -- | LD A,S | A := S
1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | -- | -- | LD A,X | A := X.
1 | mode | opcode | value | ? | Two-operand instructions A := A op operand
1 | 0 | 1 | 0 | opcode | imm8 | -- | OP #imm8 | 8-bit immediate operand (forbidden as destination)
1 | 0 | 1 | 1 | opcode | addr8 | -- | OP addr8 | 8-bit absolute address
1 | 1 | 0 | 0 | opcode | addrhi | addrlo | OP addr16 | 16-bit absolute address
1 | 1 | 0 | 1 | opcode | addrhi | addrlo | OP (addr16,X) | Indexed with 16-bit offset
1 | 1 | 1 | 0 | opcode | addr8 | -- | OP (addr8,X) | Indexed with 8-bit offset
1 | 1 | 1 | 1 | opcode | -- | -- | OP (X) | Indexed with no offset
1 | mode | 0 | 0 | 0 | 0 | value | ? | SUB A,operand | A := A − operand
1 | mode | 0 | 0 | 0 | 1 | value | ? | CP A,operand | Compare A − operand
1 | mode | 0 | 0 | 1 | 0 | value | ? | SBC A,operand | Subtract with borrow A := A − operand − C
1 | mode | 0 | 0 | 1 | 1 | value | ? | CP X,operand | Compare X − operand
1 | mode | 0 | 1 | 0 | 0 | value | ? | AND A,operand | A := A & operand, bitwise and
1 | mode | 0 | 1 | 0 | 1 | value | ? | BCP A,operand | Bitwise test A & operand
1 | mode | 0 | 1 | 1 | 0 | value | ? | LD A,operand | Load A := operand
1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | imm8 | -- | (reserved, =LD #imm8,A)
1 | mode | 0 | 1 | 1 | 1 | value | ? | LD operand,A | Store operand := A
1 | mode | 1 | 0 | 0 | 0 | value | ? | XOR A,operand | A := A ^ operand, exclusive-or
1 | mode | 1 | 0 | 0 | 1 | value | ? | ADC A,operand | A := A + operand + C, add with carry
1 | mode | 1 | 0 | 1 | 0 | value | ? | OR A,operand | A := A | operand, inclusive or
1 | mode | 1 | 0 | 1 | 1 | value | ? | ADD X,operand | A := A + operand
1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | imm8 | x | (reserved, =JP #imm8)
1 | mode | 1 | 1 | 0 | 0 | value | ? | JP operand | PC := operand, unconditional jump
1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | soff8 | -- | CALLR label | PUSH PC, PC := PC + operand
1 | mode | 1 | 1 | 0 | 1 | value | ? | CALL operand | Push PC, PC := operand
1 | mode | 1 | 1 | 1 | 0 | value | ? | LD X,operand | Load X := operand
1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | imm8 | -- | (reserved, =LD #imm8,X)
1 | mode | 1 | 1 | 1 | 1 | value | ? | LD operand,X | Store operand := X

## References

1. ↑ Datasheet: ST62T00C/T01C from 1998
2. ↑ "2006 EDN Microcontroller/Microprocessor directory, 8-bit microprocessors sorted by Instruction Set Architecture". p. 26. http://www.edn.com/contents/images/edn06mpd_8bit_ISA.pdf?industryid=45943. 100616 edn.com
3. ↑ 3.0 3.1 "ST6 Family Programming Manual". STMicroelectronics. October 2004. http://www.st.com/content/ccc/resource/technical/document/programming_manual/4d/05/d1/a5/a0/9e/40/8b/CD00004606.pdf/files/CD00004606.pdf/jcr:content/translations/en.CD00004606.pdf.
4. ↑ "ST7 Family Programming Manual". STMicroelectronics. November 2005. http://www.st.com/content/ccc/resource/technical/document/programming_manual/f5/1c/5f/0c/c6/8f/44/73/CD00004607.pdf/files/CD00004607.pdf/jcr:content/translations/en.CD00004607.pdf.

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