SPARC

Short description: RISC instruction set architecture

SPARC

Designer| Sun Microsystems (acquired by Oracle Corporation)[1][2]
Bits| 64-bit (32 → 64)
Introduced| 1986; 40 years ago (1986) (production)
1987; 39 years ago (1987) (shipments)
Version| V9 (1993) / OSA2017
Design| RISC
Type| Register–Register
Encoding| Fixed
Branching| Condition code
Endianness| Bi (Big → Bi)
Page size| 8 KB (4 KB → 8 KB)
Extensions| VIS 1.0, 2.0, 3.0, 4.0
Open| Yes, and royalty free
Registers
General purpose| 31 (G0 = 0; non-global registers use register windows)
Floating point| 32 (usable as 32 single-precision, 32 double-precision, or 16 quad-precision)
A Sun UltraSPARC II microprocessor (1997)

SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems.[1][2] Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987,[3][2] SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s.

The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in symmetric multiprocessing (SMP) and non-uniform memory access (CC-NUMA) servers produced by Sun, Solbourne, and Fujitsu, among others.

The design was turned over to the SPARC International trade group in 1989, and since then its architecture has been developed by its members. SPARC International is also responsible for licensing and promoting the SPARC architecture, managing SPARC trademarks (including SPARC, which it owns), and providing conformance testing. SPARC International was intended to grow the SPARC architecture to create a larger ecosystem; SPARC has been licensed to several manufacturers, including Atmel, Bipolar Integrated Technology, Cypress Semiconductor, Fujitsu, Matsushita and Texas Instruments. Due to SPARC International, SPARC is fully open, non-proprietary and royalty-free.

As of September 2017, the latest commercial high-end SPARC processors are Fujitsu's SPARC64 XII (introduced in 2017 for its SPARC M12 server) and Oracle's SPARC M8 introduced in September 2017 for its high-end servers.

On Friday, September 1, 2017, after a round of layoffs that started in Oracle Labs in November 2016, Oracle terminated SPARC design after completing the M8. Much of the processor core development group in Austin, Texas, was dismissed, as were the teams in Santa Clara, California, and Burlington, Massachusetts.[4][5]

Fujitsu will also discontinue their SPARC production (has already shifted to producing their own ARM-based CPUs), after two "enhanced" versions of Fujitsu's older SPARC M12 server in 2020–22 (formerly planned for 2021) and again in 2026–27, end-of-sale in 2029, of UNIX servers and a year later for their mainframe and end-of-support in 2034 "to promote customer modernization".[6]

## Contents

* 1 Features
* 2 History
* 3 Architecture
* 3.1 Registers
* 3.2 Instruction formats
* 4 SPARC architecture licensees
* 5 Implementations
* 6 Operating system support
* 7 Open source implementations
* 8 Supercomputers
* 9 See also
* 10 References
* 11 External links

## Features

The SPARC architecture was heavily influenced by the earlier RISC designs, including the RISC I and II from the University of California, Berkeley and the IBM 801. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

The SPARC processor usually contains as many as 160 general-purpose registers. According to the "Oracle SPARC Architecture 2015" specification an "implementation may contain from 72 to 640 general-purpose 64-bit" registers.[7] At any point, only 32 of them are immediately visible to software — 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only seven of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.

The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from three to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only three to reduce cost and complexity of the design, or to implement some number between them. Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

The architecture has gone through several revisions. It gained hardware multiply and divide functionality in Version 8.[8][9] 64-bit (addressing and data) were added to the version 9 SPARC specification published in 1994.[10]

In SPARC Version 8, the floating-point register file has 16 double-precision registers. Each of them can be used as two single-precision registers, providing a total of 32 single-precision registers. An odd-even number pair of double-precision registers can be used as a quad-precision register, thus allowing 8 quad-precision registers. SPARC Version 9 added 16 more double-precision registers (which can also be accessed as 8 quad-precision registers), but these additional registers can not be accessed as single-precision registers. No SPARC CPU implements quad-precision operations in hardware as of 2004.[11]

Tagged add and subtract instructions perform adds and subtracts on values checking that the bottom two bits of both operands are 0 and reporting overflow if they are not. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

The endianness of the 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load–store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.

## History

There have been three major revisions of the architecture. The first published version was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended-precision" floating-point arithmetic to 128-bit "quad-precision" arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.

SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Philips, Ross Technology, Sun Microsystems, and Texas Instruments. Newer specifications always remain compliant with the full SPARC V9 Level 1 specification.

In 2002, the SPARC Joint Programming Specification 1 (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".

At the end of 2003, JPS2 was released to support multicore CPUs. The first CPUs conforming to JPS2 were the UltraSPARC IV by Sun and the SPARC64 VI by Fujitsu.

In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV IV+ as well as CMT extensions starting with the UltraSPARC T1 implementation:

* the VIS 1 and VIS 2 instruction set extensions and the associated GSR register
* multiple levels of global registers, controlled by the GL register
* Sun's 64-bit MMU architecture
* privileged instructions ALLCLEAN, OTHERW, NORMALW, and INVALW
* access to the VER register is now hyperprivileged
* the SIR instruction is now hyperprivileged

In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC T2 implementation complied.

In August 2012, Oracle Corporation made available a new specification, Oracle SPARC Architecture 2011, which besides the overall update of the reference, adds the VIS 3 instruction set extensions and hyperprivileged mode to the 2007 specification.[12]

In October 2015, Oracle released SPARC M7, the first processor based on the new Oracle SPARC Architecture 2015 specification.[7][13] This revision includes VIS 4 instruction set extensions and hardware-assisted encryption and silicon secured memory (SSM).[14]

SPARC architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 through the Sun UltraSPARC Architecture implementations.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

## Architecture

SPARC is a load/store architecture (also known as a register-register architecture); except for the load/store instructions used to access memory, all instructions operate on the registers, in accordance with the RISC design principles.

### Registers

The SPARC architecture has an overlapping register window scheme. At any instant, 32 general purpose registers are visible. A Current Window Pointer (CWP) variable in the hardware points to the current set. The total size of the register file is not part of the architecture, allowing more registers to be added as the technology improves, up to a maximum of 32 windows in SPARC V7 and V8 as CWP is 5 bits and is part of the PSR register.

In SPARC V7 and V8 CWP will usually be decremented by the SAVE instruction (used by the SAVE instruction during the procedure call to open a new stack frame and switch the register window), or incremented by the RESTORE instruction (switching back to the call before returning from the procedure). Trap events (interrupts, exceptions or TRAP instructions) and RETT instructions (returning from traps) also change the CWP. For SPARC V9, CWP register is decremented during a RESTORE instruction, and incremented during a SAVE instruction. This is the opposite of PSR.CWP's behavior in SPARC V8. This change has no effect on nonprivileged instructions.

Window Addressing  Register group | Mnemonic | Register address | Availabilty

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global | G0-G7 | R[0]-R[7] | Always the same ones, G0 being zero always.
out | O0-O7 | R[8]-R[15] | To be handed over to, and returned from, the called subroutine, as its "in".
local | L0-L7 | R[16]-R[23] | Truly local to the current subroutine.
in | I0-I7 | R[24]-R[31] | Handed over from the caller, and returned to the caller, as its "out".

SPARC registers are shown in the figure above.

### Instruction formats

All SPARC instructions occupy a full 32 bit word and start on a word boundary. Four formats are used, distinguished by the first two bits. All arithmetic and logical instructions have 2 source operands and 1 destination operand.

SETHI instruction format copies its 22 bit immediate operand into the high-order 22 bits of any specified register, and sets each of the low-order 10 bits to 0.

Format ALU register, both sources are registers; format ALU immediate, one source is a register and one is a constant in the range -4096 to +4095. Bit 13 selects between them. In both cases, the destination is always a register.

Branch format instructions do control transfers or conditional branches. The icc or fcc field specifies the kind of branch. The 22 bit displacement field give the relative address of the target in words so that conditional branches can go forward or backward up to 8 megabytes. The ANNUL (A) bit is used to get rid of some delay slots. If it is 0 in a conditional branch, the delay slot is executed as usual. If it is 1, the delay slot is only executed if the branch is taken. If it is not taken, the instruction following the conditional branch is skipped.

The CALL instruction uses a 30-bit program counter-relative word offset. This value is enough to reach any instruction within 4 gigabytes of the caller or the entire address space. The CALL instruction deposits the return address in register R15 also known as output register O7.

Just like the arithmetic instructions, the SPARC architecture uses two different formats for load and store instructions. The first format is used for instructions that use one or two registers as the effective address. The second format is used for instructions that use an integer constant as the effective address.

SPARC instruction formats  Type  | Bit

|

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SETHI format | 00 | RD | 100 | Immediate constant 22 bits
I Branch format | 00 | A | icc | 010 | Displacement constant 22 bits
F Branch format | 00 | A | fcc | 110 | Displacement constant 22 bits
CALL disp | 01 | PC-relative displacement
Arithmetic register | 10 | RD | opcode | RS 1 | 0 | 0 | RS 2
Arithmetic immediate | 10 | RD | opcode | RS 1 | 1 | Immediate constant 13 bits
FPU | 10 | FD | 110100/110101 | FS 1 | opf | FS 2
LD/ST register | 11 | RD | opcode | RS 1 | 0 | 0 | RS 2
LD/ST immediate | 11 | RD | opcode | RS 1 | 1 | Immediate constant 13 bits

Most arithmetic instructions come in pairs with one version setting the NZVC condition code bits, and the other does not. This is so that the compiler has a way to move instructions around when trying to fill delay slots.

SPARC V7 does not have multiplication or division instructions, but it does have MULSCC, which does one step of a multiplication testing one bit and conditionally adding the multiplicand to the product. This was because MULSCC can complete over one clock cycle in keeping with the RISC philosophy.

## SPARC architecture licensees

The following organizations have licensed the SPARC architecture:

* Afara Websystems
* Bipolar Integrated Technology (BIT)
* Cypress Semiconductor
* European Space Research and Technology Center (ESTEC)
* Fujitsu (and its Fujitsu Microelectronics subsidiary)
* Gaisler Research
* HAL Computer Systems
* Hyundai
* LSI Logic
* Matra Harris Semiconductors (MHS)
* Matsushita Electrical Industrial Co.
* Meiko Scientific
* Metaflow Technologies
* Philips Electronics
* Prisma
* Ross Technology
* Solbourne Computer
* Systems & Processes Engineering Corporation (SPEC)
* TEMIC
* Weitek

## Implementations

Name (codename)  | Model  | Frequency (MHz)  | Arch. version  | Year  | Total threads[note 1] | Process (nm)  | Transistors (millions)  | Die size (mm2)  | IO pins  | Power (W)  | Voltage (V)  | L1 Dcache (KB)  | L1 Icache (KB)  | L2 cache (KB)  | L3 cache (KB)

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SPARC MB86900 | Fujitsu[1][3][2] | 14.28-33 | V7 | 1986 | 1×1=1 | 1300 | 0.11 | — | 256 | — | — | 0-128 (unified) | none | none
SPARC  | Various[note 2] | 14.28-40 | V7 | 1989–1992 | 1×1=1 | 800-1300 | ~0.1-1.8 | — | 160-256 | — | — | 0-128 (unified) | none | none
MN10501 (KAP)  | Solbourne Computer,

Matsushita[15]

| 33-36  | V8  | 1990-1991  | 1x1=1  | —  | 1.0[16] | —  | —  | —  | —  | 8  | 8  | 0–256  | none
microSPARC I (Tsunami)  | TI TMS390S10  | 40-50 | V8 | 1992 | 1×1=1 | 800 | 0.8 | 225? | 288 | 2.5 | 5 | 2 | 4 | none | none
SuperSPARC I (Viking)  | TI TMX390Z50 / Sun STP1020  | 33-60 | V8 | 1992 | 1×1=1 | 800 | 3.1 | — | 293 | 14.3 | 5 | 16 | 20 | 0–2048 | none
SPARClite  | Fujitsu MB8683x  | 66-108 | V8E | 1992 | 1×1=1 | — | — | — | 144, 176 | — | 2.5/3.3–5.0 V, 2.5–3.3 V | 1, 2, 8, 16 | 1, 2, 8, 16 | none | none
hyperSPARC (Colorado 1)  | Ross RT620A  | 40-90 | V8 | 1993 | 1×1=1 | 500 | 1.5 | — | — | — | 5? | 0 | 8 | 128–256 | none
microSPARC II (Swift)  | Fujitsu MB86904 / Sun STP1012  | 60-125 | V8 | 1994 | 1×1=1 | 500 | 2.3 | 233 | 321 | 5 | 3.3 | 8 | 16 | none | none
hyperSPARC (Colorado 2)  | Ross RT620B  | 90-125 | V8 | 1994 | 1×1=1 | 400 | 1.5 | — | — | — | 3.3 | 0 | 8 | 128–256 | none
SuperSPARC II (Voyager)  | Sun STP1021  | 75-90 | V8 | 1994 | 1×1=1 | 800 | 3.1 | 299 | — | 16 | — | 16 | 20 | 1024–2048 | none
hyperSPARC (Colorado 3)  | Ross RT620C  | 125-166 | V8 | 1995 | 1×1=1 | 350 | 1.5 | — | — | — | 3.3 | 0 | 8 | 512–1024 | none
TurboSPARC | Fujitsu MB86907  | 160-180 | V8 | 1996 | 1×1=1 | 350 | 3.0 | 132 | 416 | 7 | 3.5 | 16 | 16 | 512 | none
UltraSPARC (Spitfire)  | Sun STP1030  | 143-167 | V9 | 1995 | 1×1=1 | 470 | 3.8 | 315 | 521 | 30[note 3] | 3.3 | 16 | 16 | 512–1024 | none
UltraSPARC (Hornet)  | Sun STP1030  | 200 | V9 | 1995 | 1×1=1 | 420 | 5.2 | 265 | 521 | — | 3.3 | 16 | 16 | 512–1024 | none
hyperSPARC (Colorado 4)  | Ross RT620D  | 180-200 | V8 | 1996 | 1×1=1 | 350 | 1.7 | — | — | — | 3.3 | 16 | 16 | 512 | none
SPARC64 | Fujitsu (HAL)  | 101-118 | V9 | 1995 | 1×1=1 | 400 | — | Multichip | 286 | 50 | 3.8 | 128 | 128 | — | —
SPARC64 II | Fujitsu (HAL)  | 141-161 | V9 | 1996 | 1×1=1 | 350 | — | Multichip | 286 | 64 | 3.3 | 128 | 128 | — | —
SPARC64 III | Fujitsu (HAL) MBCS70301  | 250-330 | V9 | 1998 | 1×1=1 | 240 | 17.6 | 240 | — | — | 2.5 | 64 | 64 | 8192 | —
UltraSPARC IIs (Blackbird)  | Sun STP1031  | 250-400 | V9 | 1997 | 1×1=1 | 350 | 5.4 | 149 | 521 | 25[note 4] | 2.5 | 16 | 16 | 1024 or 4096 | none
UltraSPARC IIs (Sapphire-Black)  | Sun STP1032 / STP1034  | 360-480 | V9 | 1999 | 1×1=1 | 250 | 5.4 | 126 | 521 | 21[note 5] | 1.9 | 16 | 16 | 1024-8192 | none
UltraSPARC IIi (Sabre)  | Sun SME1040  | 270-360 | V9 | 1997 | 1×1=1 | 350 | 5.4 | 156 | 587 | 21 | 1.9 | 16 | 16 | 256-2048 | none
UltraSPARC IIi (Sapphire-Red)  | Sun SME1430  | 333-480 | V9 | 1998 | 1×1=1 | 250 | 5.4 | — | 587 | 21[note 6] | 1.9 | 16 | 16 | 2048 | none
UltraSPARC IIe (Hummingbird)  | Sun SME1701  | 400-500 | V9 | 1999 | 1×1=1 | 180 Al | — | — | 370 | 13[note 7] | 1.5–1.7 | 16 | 16 | 256 | none
UltraSPARC IIi (IIe+) (Phantom)  | Sun SME1532  | 550-650 | V9 | 2000 | 1×1=1 | 180 Cu | — | — | 370 | 17.6 | 1.7 | 16 | 16 | 512 | none
SPARC64 GP | Fujitsu SFCB81147  | 400-563 | V9 | 2000 | 1×1=1 | 180 | 30.2 | 217 | — | — | 1.8 | 128 | 128 | 8192 | —
SPARC64 GP | \--  | 600-810 | V9 | — | 1×1=1 | 150 | 30.2 | — | — | — | 1.5 | 128 | 128 | 8192 | —
SPARC64 IV  | Fujitsu MBCS80523  | 450-810 | V9 | 2000 | 1×1=1 | 130 | — | — | — | — | — | 128 | 128 | 2048 | —
UltraSPARC III (Cheetah)  | Sun SME1050  | 600 | JPS1 | 2001 | 1×1=1 | 180 Al | 29 | 330 | 1368 | 53 | 1.6 | 64 | 32 | 8192 | none
UltraSPARC III (Cheetah)  | Sun SME1052  | 750-900 | JPS1 | 2001 | 1×1=1 | 130 Al | 29 | — | 1368 | — | 1.6 | 64 | 32 | 8192 | none
UltraSPARC III Cu (Cheetah+)  | Sun SME1056  | 900-1200 | JPS1 | 2001 | 1×1=1 | 130 Cu | 29 | 232 | 1368 | 50[note 8] | 1.6 | 64 | 32 | 8192 | none
UltraSPARC IIIi (Jalapeño)  | Sun SME1603  | 1064-1593 | JPS1 | 2003 | 1×1=1 | 130 | 87.5 | 206 | 959 | 52 | 1.3 | 64 | 32 | 1024 | none
SPARC64 V (Zeus)  | Fujitsu  | 1100-1350 | JPS1 | 2003 | 1×1=1 | 130 | 190 | 289 | 269 | 40 | 1.2 | 128 | 128 | 2048 | —
SPARC64 V+ (Olympus-B)  | Fujitsu  | 1650-2160 | JPS1 | 2004 | 1×1=1 | 90 | 400 | 297 | 279 | 65 | 1 | 128 | 128 | 4096 | —
UltraSPARC IV (Jaguar)  | Sun SME1167  | 1050-1350 | JPS2 | 2004 | 1×2=2 | 130 | 66 | 356 | 1368 | 108 | 1.35 | 64 | 32 | 16384 | none
UltraSPARC IV+ (Panther)  | Sun SME1167A  | 1500-2100 | JPS2 | 2005 | 1×2=2 | 90 | 295 | 336 | 1368 | 90 | 1.1 | 64 | 64 | 2048 | 32768
UltraSPARC T1 (Niagara)  | Sun SME1905  | 1000-1400 | UA2005 | 2005 | 4×8=32 | 90 | 300 | 340 | 1933 | 72 | 1.3 | 8 | 16 | 3072 | none
SPARC64 VI (Olympus-C)  | Fujitsu  | 2150-2400 | JPS2 | 2007 | 2×2=4 | 90 | 540 | 422 | — | 120-150 | 1.1 | 128×2 | 128×2 | 4096-6144 | none
UltraSPARC T2 (Niagara 2)  | Sun SME1908A  | 1000-1600 | UA2007 | 2007 | 8×8=64 | 65 | 503 | 342 | 1831 | 95 | 1.1-1.5 | 8 | 16 | 4096 | none
UltraSPARC T2 Plus (Victoria Falls)  | Sun SME1910A  | 1200-1600 | UA2007 | 2008 | 8×8=64 | 65 | 503 | 342 | 1831 | — | — | 8 | 16 | 4096 | none
SPARC64 VII (Jupiter)[17] | Fujitsu  | 2400-2880 | JPS2 | 2008 | 2×4=8 | 65 | 600 | 445 | — | 150 | — | 64×4 | 64×4 | 6144 | none
UltraSPARC "RK" (Rock)[18] | Sun SME1832  | 2300 | ???? | canceled[19] | 2×16=32 | 65 | ? | 396 | 2326 | ? | ? | 32 | 32 | 2048 | ?
SPARC64 VIIIfx (Venus)[20][21] | Fujitsu  | 2000 | JPS2 / HPC-ACE | 2009 | 1×8=8 | 45 | 760 | 513 | 1271 | 58 | ? | 32×8 | 32×8 | 6144 | none
LEON2FT | Atmel AT697F  | 100 | V8 | 2009 | 1×1=1 | 180 | — | — | 196 | 1 | 1.8/3.3 | 16 | 32 | — | —|none
SPARC T3 (Rainbow Falls)  | Oracle/Sun  | 1650 | UA2007 | 2010 | 8×16=128 | 40[22] | ???? | 371 | ? | 139 | ? | 8 | 16 | 6144 | none
Galaxy FT-1500  | NUDT (China)  | 1800 | UA2007? | 201? | 8×16=128 | 40 | ???? | ??? | ? | 65 | ? | 16×16 | 16×16 | 512×16 | 4096
SPARC64 VII+ (Jupiter-E or M3)[23][24] | Fujitsu  | 2667–3000 | JPS2 | 2010 | 2×4=8 | 65 | — | — | — | 160 | — | 64×4 | 64×4 | 12288 | none
LEON3FT | Cobham Gaisler GR712RC  | 100 | V8E | 2011 | 1×2=2 | 180 | — | — | — | 1.5[note 9] | 1.8/3.3 | 4x4Kb | 4x4Kb | none | none
R1000 | MCST (Russia)  | 1000 | JPS2 | 2011 | 1×4=4 | 90 | 180 | 128 | — | 15 | 1, 1.8, 2.5 | 32 | 16 | 2048 | none
SPARC T4 (Yosemite Falls)[25] | Oracle  | 2850–3000 | OSA2011 | 2011 | 8×8=64 | 40 | 855 | 403 | ? | 240 | ? | 16×8 | 16×8 | 128×8 | 4096
SPARC64 IXfx[26][27][28] | Fujitsu  | 1850 | JPS2 / HPC-ACE | 2012 | 1x16=16 | 40 | 1870 | 484 | 1442 | 110 | ? | 32×16 | 32×16 | 12288 | none
SPARC64 X (Athena)[29] | Fujitsu  | 2800 | OSA2011 / HPC-ACE | 2012 | 2×16=32 | 28 | 2950 | 587.5 | 1500 | 270 | ? | 64×16 | 64×16 | 24576 | none
SPARC T5 | Oracle  | 3600 | OSA2011 | 2013 | 8×16=128 | 28 | 1500 | 478 | ? | ? | ? | 16×16 | 16×16 | 128×16 | 8192
SPARC M5[30] | Oracle  | 3600 | OSA2011 | 2013 | 8×6=48 | 28 | 3900 | 511 | ? | ? | ? | 16×6 | 16×6 | 128×6 | 49152
SPARC M6[31] | Oracle  | 3600 | OSA2011 | 2013 | 8×12=96 | 28 | 4270 | 643 | ? | ? | ? | 16×12 | 16×12 | 128×12 | 49152
SPARC64 X+ (Athena+)[32] | Fujitsu  | 3200–3700 | OSA2011 / HPC-ACE | 2014 | 2×16=32 | 28 | 2990 | 600 | 1500 | 392 | ? | 64×16 | 64×16 | 24M | none
SPARC64 XIfx[33] | Fujitsu  | 2200 | JPS2 / HPC-ACE2 | 2014 | 1×(32+2)=34 | 20 | 3750 | ? | 1001 | ? | ? | 64×34 | 64×34 | 12M×2 | none
SPARC M7[34][35] | Oracle  | 4133 | OSA2015 | 2015 | 8×32=256 | 20 | >10,000 | ? | ? | ? | ? | 16×32 | 16×32 | 256×24 | 65536
SPARC S7[36][37] | Oracle  | 4270 | OSA2015 | 2016 | 8×8=64 | 20 | ???? | ? | ? | ? | ? | 16×8 | 16×8 | 256×2+256×4 | 16384
SPARC64 XII[38] | Fujitsu  | 4250 | OSA201? / HPC-ACE | 2017 | 8×12=96 | 20 | 5500 | 795 | 1860 | ? | ? | 64×12 | 64×12 | 512×12 | 32768
SPARC M8[39][40] | Oracle  | 5000 | OSA2017 | 2017 | 8×32=256 | 20 | ? | ? | ? | ? | ? | 32×32 | 16×32 | 128×32+256×8 | 65536
LEON4 | Cobham Gaisler GR740  | 250[note 10] | V8E | 2017 | 1×4=4 | 32 | — | — | — | — | 1.2/2.5/3.3 | 4x4 | 4x4 | 2048 | none
R2000 | MCST (Russia)  | 2000 | ? | 2018 | 1×8=8 | 28 | 500 | ? | — | ? | ? | ? | ? | ? | none
LEON5 | Cobham Gaisler  | — | V8E | 2019 | ? | ? | — | — | — | — | — | ? | ? | 16–8192 | none
Name (codename)  | Model  | Frequency (MHz)  | Arch. version  | Year  | Total threads[note 1] | Process (nm)  | Transistors (millions)  | Die size (mm2)  | IO pins  | Power (W)  | Voltage (V)  | L1 Dcache (KB)  | L1 Icache (KB)  | L2 cache (KB)  | L3 cache (KB)

Notes:

1. ↑ 1.0 1.1 Threads per core × number of cores
2. ↑ Various SPARC V7 implementations were produced by Fujitsu, LSI Logic, Weitek, Texas Instruments, Cypress and Temic. A SPARC V7 processor generally consisted of several discrete chips, usually comprising an integer unit (IU), a floating-point unit (FPU), a memory management unit (MMU) and cache memory. Conversely, the Atmel (now Microchip Technology) TSC695 is a single-chip SPARC V7 implementation.
3. ↑ @167 MHz
4. ↑ @250 MHz
5. ↑ @400 MHz
6. ↑ @440 MHz
7. ↑ max. @500 MHz
8. ↑ @1200 MHz
9. ↑ excluding I/O buses
10. ↑ nominal; specification from 100 to 424 MHz depending on attached RAM capabilities

## Operating system support

SPARC machines have generally used Sun's SunOS, Solaris, or OpenSolaris including derivatives illumos and OpenIndiana, but other operating systems have also been used, such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux.

In 1993, Intergraph announced a port of Windows NT to the SPARC architecture,[41] but it was later cancelled.

In October 2015, Oracle announced a "Linux for SPARC reference platform".[42]

## Open source implementations

Several fully open source implementations of the SPARC architecture exist:

* LEON, a 32-bit radiation-tolerant, SPARC V8 implementation, designed especially for space use. Source code is written in VHDL, and licensed under the GPL.
* OpenSPARC T1, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary software license agreement.
* S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC V9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL.
* OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existing open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement.

A fully open source simulator for the SPARC architecture also exists:

* RAMP Gold, a 32-bit, 64-thread SPARC Version 8 implementation, designed for FPGA-based architecture simulation. RAMP Gold is written in ~36,000 lines of SystemVerilog, and licensed under the BSD licenses.

## Supercomputers

For HPC loads Fujitsu builds specialized SPARC64 fx processors with a new instruction extensions set, called HPC-ACE (High Performance Computing – Arithmetic Computational Extensions).

Fujitsu's K computer ranked No. 1 in the TOP500 June 2011 and November 2011 lists. It combines 88,128 SPARC64 VIIIfx CPUs, each with eight cores, for a total of 705,024 cores—almost twice as many as any other system in the TOP500 at that time. The K Computer was more powerful than the next five systems on the list combined, and had the highest performance-to-power ratio of any supercomputer system.[43] It also ranked No. 6 in the Green500 June 2011 list, with a score of 824.56 MFLOPS/W.[44] In the November 2012 release of TOP500, the K computer ranked No. 3, using by far the most power of the top three.[45] It ranked No. 85 on the corresponding Green500 release.[46] Newer HPC processors, IXfx and XIfx, were included in recent PRIMEHPC FX10 and FX100 supercomputers.

Tianhe-2 (TOP500 No. 1 as of November 2014[47]) has a number of nodes with Galaxy FT-1500 OpenSPARC-based processors developed in China. However, those processors did not contribute to the LINPACK score.[48][49]

## See also

* ERC32 — based on SPARC V7 specification
* Ross Technology, Inc. — a SPARC microprocessor developer during the 1980s and 1990s
* Sparcle — a modified SPARC with multiprocessing support used by the MIT Alewife project
* LEON — a space rated SPARC V8 processor.
* R1000 — a Russian quad-core microprocessor based on SPARC V9 specification
* Galaxy FT-1500 — a Chinese 16-core OpenSPARC based processor

## References

1. ↑ 1.0 1.1 1.2 "Fujitsu to take ARM into the realm of Super". June 21, 2016. http://www.cpushack.com/2016/06/21/fujitsu-to-take-arm-into-the-realm-of-super/.
2. ↑ 2.0 2.1 2.2 2.3 "Timeline". https://sparc.org/timeline/.
3. ↑ 3.0 3.1 "Fujitsu SPARC". http://www.cpu-collection.de/?tn=0&l0=cl&l1=SPARC&l2=Fujitsu.
4. ↑ Vaughan-Nichols, Steven J. (September 5, 2017). "Sun set: Oracle closes down last Sun product lines". http://www.zdnet.com/article/sun-set-oracle-closes-down-last-sun-product-lines/.
5. ↑ Nichols, Shaun (August 31, 2017). "Oracle finally decides to stop prolonging the inevitable, begins hardware layoffs". https://www.theregister.co.uk/2017/08/31/oracle_stops_prolonging_inevitable_layoffs/.
6. ↑ "Roadmap: Fujitsu Global". https://www.fujitsu.com/global/products/computing/servers/unix/sparc/key-reports/roadmap/.
7. ↑ 7.0 7.1 "Oracle SPARC Architecture 2015: One Architecture ... Multiple Innovative Implementations". January 12, 2016. http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-architecture-2015-2868130.pdf. "IMPL. DEP. #2-V8: An Oracle SPARC Architecture implementation may contain from 72 to 640 general-purpose 64-bit R registers. This corresponds to a grouping of the registers into MAXPGL + 1 sets of global R registers plus a circular stack of N_REG_WINDOWS sets of 16 registers each, known as register windows. The number of register windows present (N_REG_WINDOWS) is implementation dependent, within the range of 3 to 32 (inclusive)."
8. ↑ "SPARC Options", Using the GNU Compiler Collection (GCC), GNU, https://gcc.gnu.org/onlinedocs/gcc/SPARC-Options.html, retrieved January 8, 2013
9. ↑ SPARC Optimizations With GCC, OSNews, February 23, 2004, http://www.osnews.com/story/6136, retrieved January 8, 2013
10. ↑ Weaver, D. L.; Germond, T., eds. (1994), "The SPARC Architecture Manual, Version 9", SPARC International, Inc. (Prentice Hall), ISBN 0-13-825001-4, http://sparc.org/wp-content/uploads/2014/01/SPARCV9.pdf.gz, retrieved December 6, 2011
11. ↑ "SPARC Behavior and Implementation". Numerical Computation Guide – Sun Studio 10. Sun Microsystems, Inc. 2004. http://download.oracle.com/docs/cd/E19059-01/stud.10/819-0499/ncg_sparc.html. Retrieved September 24, 2011. "There are four situations, however, when the hardware will not successfully complete a floating-point instruction: ... The instruction is not implemented by the hardware (such as ... quad-precision instructions on any SPARC FPU)."
12. ↑ "Oracle SPARC Architecture 2011", Oracle Corporation, May 21, 2014, http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/140521-ua2011-d096-p-ext-2306580.pdf, retrieved November 25, 2015
13. ↑ Soat, John. "SPARC M7 Innovation". Oracle web site. Oracle Corporation. http://www.oracle.com/us/corporate/features/sparc-m7/.
14. ↑ "Software in Silicon Cloud - Oracle". https://www.oracle.com/servers/sparc/software-in-silicon.html.
15. ↑ "Floodgap Retrobits presents the Solbourne Solace: a shrine to the forgotten SPARC". http://www.floodgap.com/retrobits/solace/.
16. ↑ Sager, D.; Hinton, G.; Upton, M.; Chappell, T.; Fletcher, T.D.; Samaan, S.; Murray, R. (2001). "A 0.18 μm CMOS IA32 microprocessor with a 4 GHz integer execution unit". 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) (San Francisco, CA, USA: IEEE): 324–325. doi:10.1109/ISSCC.2001.912658. ISBN 978-0-7803-6608-4.
17. ↑ FX1 Key Features & Specifications, Fujitsu, February 19, 2008, http://www.fujitsu.com/downloads/PR/2008/20080219-01a.pdf, retrieved December 6, 2011
18. ↑ Tremblay, Marc; Chaudhry, Shailender (February 19, 2008), "A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC(R) Processor", OpenSPARC (Sun Microsystems), http://www.opensparc.net/pubs/preszo/08/RockISSCC08.pdf, retrieved December 6, 2011
19. ↑ Vance, Ashlee (June 15, 2009), "Sun Is Said to Cancel Big Chip Project", The New York Times, http://bits.blogs.nytimes.com/2009/06/15/sun-is-said-to-cancel-big-chip-project, retrieved May 23, 2010
20. ↑ "Fujitsu shows off SPARC64 VII", heise online, August 28, 2008, http://www.h-online.com/newsticker/news/item/Hot-Chips-Fujitsu-shows-off-SPARC64-VII-737073.html, retrieved December 6, 2011
21. ↑ Barak, Sylvie (May 14, 2009), "Fujitsu unveils world's fastest CPU", The Inquirer, http://www.theinquirer.net/inquirer/news/1137342/fujitsu-unveils-world-s-fastest-cpu, retrieved December 6, 2011
22. ↑ "Sparc T3 processor", Oracle Corporation, http://www.oracle.com/us/products/servers-storage/servers/sparc-enterprise/t-series/sparc-t3-chip-ds-173097.pdf, retrieved December 6, 2011
23. ↑ Morgan, Timothy Prickett (December 3, 2010), "Ellison: Sparc T4 due next year", The Register, http://www.channelregister.co.uk/2010/12/03/oracle_sparct4_fujitsu_sparc64/, retrieved December 6, 2011
24. ↑ "SPARC Enterprise M-series Servers Architecture", Fujitsu, April 2011, http://www.fujitsu.com/downloads/SPARCE/whitepapers/sparc-architecture-m-series-en.pdf, retrieved November 5, 2011
25. ↑ Morgan, Timothy Prickett (August 22, 2011), "Oracle's Sparc T4 chip", The Register, https://www.theregister.co.uk/2011/08/22/oracle_sparc_t4_hot_chips/, retrieved December 6, 2011
26. ↑ Morgan, Timothy Prickett (November 21, 2011), "Fujitsu parades 16-core Sparc64 super stunner", The Register, https://www.theregister.co.uk/2011/11/21/fujitsu_sparc64_ixfx_fx10_details, retrieved December 8, 2011
27. ↑ "Fujitsu Launches PRIMEHPC FX10 Supercomputer", Fujitsu, November 7, 2011, http://www.fujitsu.com/global/news/pr/archives/month/2011/20111107-01.html, retrieved February 3, 2012
28. ↑ "Ixfx Download". fujitsu.com. http://www.fujitsu.com/downloads/TC/sc11/sparc64-ixfx-sc11.pdf.
29. ↑ "Images of SPARC64". fujitsu.com. https://www.fujitsu.com/global/Images/HC25.27.910-SPARC64.pdf.
30. ↑ "Oracle Products". oracle.com. http://www.oracle.com/us/products/servers-storage/servers/sparc/oracle-sparc/m5-32/m5-processor-ds-1922646.pdf.
31. ↑ "Oracle SPARC products". oracle.com. http://www.oracle.com/us/products/servers-storage/servers/sparc/oracle-sparc/m6-32/sparc-m6-processor-ds-2015586.pdf.
32. ↑ "Fujitsu Presentation pdf". fujitsu.com. https://www.fujitsu.com/global/Images/HotChips24_Fujitsu_presentation.pdf.
33. ↑ "Fujitsu Global Images". fujitsu.com. http://www.fujitsu.com/global/Images/20140811hotchips26.pdf.
34. ↑ "M7: Next Generation SPARC. Hotchips 26". swisdev.oracle.com. http://swisdev.oracle.com/_files/M7_Preso.pdf.
35. ↑ "Oracle's SPARC T7 and SPARC M7 Server Architecture". oracle.com. http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-t7-m7-server-architecture-2702877.pdf.
36. ↑ Vinaik, Basant; Puri, Rahoul (August 24, 2015). "Hot Chips – August 23–25, 2015 – Conf. Day1 – Oracle's Sonoma Processor: Advanced low-cost SPARC processor for enterprise workloads". hotchips.org. https://old.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.24-Monday-Epub/HC27.24.30-HP-Cloud-Comm-Epub/HC27.24.330-sonoma.Vinalk-oracle-v3.pdf.
37. ↑ "Blueprints revealed: Oracle crams Sparc M7 and InfiniBand into cheaper 'Sonoma' chips". theregister.co.uk. https://www.theregister.co.uk/2015/08/24/oracle_sonoma_processor_sparc/?page=1.
38. ↑ "Documents at Fujitsu". fujitsu.com. http://www.fujitsu.com/jp/documents/products/computing/servers/unix/sparc/events/2017/coolchips20/CoolChips20-rev8.pdf.
39. ↑ "Oracle's New SPARC Systems Deliver 2-7x Better Performance, Security Capabilities, and Efficiency than Intel-based Systems". oracle.com. https://www.oracle.com/corporate/pressrelease/oracle-sparc-m8-091817.html.
40. ↑ "SPARC M8 Processor". oracle.com. http://www.oracle.com/us/products/servers-storage/sparc-m8-processor-ds-3864282.pdf.
41. ↑ McLaughlin, John (July 7, 1993), "Intergraph to Port Windows NT to SPARC", The Florida SunFlash 55 (11), http://ftp.lanet.lv/ftp/sun-info/sunflash/1993/Jul/55.11-Sun-Intergraph:-SPARC-and-Windows-NT, retrieved December 6, 2011
42. ↑ Project: Linux for SPARC - oss.oracle.com, October 12, 2015, https://oss.oracle.com/projects/linux-sparc/, retrieved December 4, 2015
43. ↑ "TOP500 List (1-100)", TOP500, June 2011, http://top500.org/list/2011/06/100, retrieved December 6, 2011
44. ↑ "The Green500 List", Green500, June 2011, http://www.green500.org/lists/2011/06/top/list.php
45. ↑ "Top500 List – November 2012 | TOP500 Supercomputer Sites", TOP500, November 2012, http://www.top500.org/list/2012/11/, retrieved January 8, 2013
46. ↑ "The Green500 List – November 2012 | The Green500", Green500, November 2012, http://www.green500.org/lists/green201211&green500from=1&green500to=100, retrieved January 8, 2013
47. ↑ "Tianhe-2 (MilkyWay-2)", TOP500, May 2015, http://top500.org/system/177999, retrieved May 27, 2015
48. ↑ Keane, Andy, "Tesla Supercomputing" (mp4), Nvidia, http://www.nvidia.com/content/mp4/sc-2010/theater/keane-sc10.mp4, retrieved December 6, 2011
49. ↑ Thibodeau, Patrick (November 4, 2010), U.S. says China building 'entirely indigenous' supercomputer, Computerworld, http://www.computerworld.com/s/article/9194799/U.S._says_China_building_entirely_indigenous_supercomputer_, retrieved August 28, 2017

## External links

* SPARC International, Inc.
*   * SPARC Technical Documents
* OpenSPARC Architecture specification
* Hypervisor/Sun4v Reference Materials
* Fujitsu SPARC64 V, VI, VII, VIIIfx, IXfx Extensions and X / X+ Specification
*   *   *   *   * Fujitsu SPARC Roadmap
* SPARC processor images and descriptions
* The Rough Guide to MBus Modules (SuperSPARC, hyperSPARC)
* SPARC at Curlie

* v
* t
* e

Reduced instruction set computer (RISC) architectures

* IBM 801
* Berkeley RISC
* Stanford MIPS

Active|

* Analog Devices Blackfin
* ARC
* ARM
* AVR
* eSi-RISC
* LatticeMico8
* LatticeMico32
* MIPS
* OpenRISC
* Power ISA
* Renesas M32R
* Renesas SuperH
* Renesas V850
* RISC-V
* Sunway
* SPARC
* Unicore
* Xilinx MicroBlaze
* Xilinx PicoBlaze
* POWER
* PowerPC
* XMOS XCore XS1

Historic|

* Alpha
* AMD Am29000
* Apollo PRISM
* Atmel AVR32
* Clipper
* CRISP
* DEC Prism
* Intel i860
* Intel i960
* Meta
* MIPS-X
* Motorola 88000
* Motorola M·CORE
* PA-RISC
* ROMP

* v
* t
* e

Computer hardware by Sun Microsystems (acquired by Oracle Corporation, 2010)

Processors|

* SPARC
* MB86900
* microSPARC
* SuperSPARC
* UltraSPARC
* UltraSPARC II
* UltraSPARC IIe
* UltraSPARC IIi
* Gemini
* UltraSPARC III
* UltraSPARC III Cu
* UltraSPARC IIIi
* UltraSPARC IV
* UltraSPARC T1
* UltraSPARC T2
* SPARC T3
* SPARC T4
* SPARC T5
* Rock
* MAJC

Workstations, servers|

* Sun-1
* Sun-2
* Sun-3
* Sun386i
* Sun-4
* SPARCstation/server/center
* Netra
* Ultra
* Enterprise
* Sun Blade
* Sun Fire
* Java Workstation
* SPARC Enterprise

Network computers|

* JavaStation
* Sun Ray

Storage hardware|

* StorageTek 5800
* Sun Fire X4500

Other|

* Sun Modular Datacenter
* Sun SPOT
* Sun Neptune

* v
* t
* e

Oracle Corporation

Corporate directors|

* Jeffrey Berg
* H. Raymond Bingham
* Michael Boskin
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* Larry Ellison
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* Joseph Grundfest
* Jeffrey O. Henley
* Mark Hurd
* Jack F. Kemp
* Donald L. Lucas
* Naomi O. Seligman

Acquisitions (list)|

* Sun
* PeopleSoft
* Hyperion
* Siebel
* BEA
* JD Edwards
* RightNow
* Virtual Iron
* TimesTen
* Sunopsis
* NetSuite

Databases|

* Oracle Database
* MySQL
* InnoDB
* Berkeley DB
* TimesTen
* Rdb
* Essbase

Programming languages|

* Java
* PL/SQL

IDEs|

* JDeveloper
* Forms
* NetBeans
* Apex
* SQL Developer
* Developer Studio

Middleware|

* Fusion Middleware
* WebCenter
* SOA Suite
* WebLogic Server
* Coherence
* Tuxedo
* GlassFish

Operating systems|

* Oracle Linux
* Oracle Solaris

Computer hardware|

* Sun Fire
* SPARC (T-Series, Enterprise)
* StorageTek

Computer appliances|

* Oracle Exadata
* Oracle Exalogic
* Big Data Appliance

Education and recognition|

* Oracle Certification Program

* Category

* v
* t
* e

Processor technologies

Models|

* Turing machine
* Universal
* Post–Turing
* Quantum
* Belt machine
* Stack machine
* Finite-state machine
* with datapath
* Hierarchical
* Queue automaton
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load/store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* comparison
* addressing modes

|

* x86
* ARM
* MIPS
* Power ISA
* SPARC
* Itanium
* Unicore
* MicroBlaze
* RISC-V
* others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Tomasulo algorithm
* Reservation station
* Re-order buffer
* Register renaming

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* SWAR
* SIMT
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Coprocessor
* ASIC
* FPGA
* CPLD
* Multi-chip module (MCM)
* System in package (SiP)

| By application|

* Microprocessor
* Microcontroller
* Mobile
* Notebook
* Ultra-low-voltage
* ASIP

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Programmable (PSoC)
* Network on a chip (NoC)

Hardware
accelerators|

* AI accelerator
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor processing unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 2-bit
* 4-bit
* 8-bit
* 16-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Integrated memory controller (IMC)

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Program counter

Control unit|

* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)
* Race to sleep

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model

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