AI accelerator

Short description: Hardware acceleration unit for artificial intelligence tasks

An AI accelerator is a class of specialized hardware accelerator[1] or computer system[2][3] designed to accelerate artificial intelligence and machine learning applications, including artificial neural networks and machine vision. Typical applications include algorithms for robotics, internet of things, and other data-intensive or sensor-driven tasks.[4] They are often manycore designs and generally focus on low-precision arithmetic, novel dataflow architectures or in-memory computing capability. (As of 2018), a typical AI integrated circuit chip contains billions of MOSFET transistors.[5] A number of vendor-specific terms exist for devices in this category, and it is an emerging technology without a dominant design.

## Contents

* 1 History
* 1.1 Early attempts
* 1.2 Heterogeneous computing
* 1.3 Use of GPU
* 1.4 Use of FPGAs
* 1.5 Emergence of dedicated AI accelerator ASICs
* 1.6 In-memory computing architectures
* 1.7 In-memory computing with analog resistive memories
* 1.8 Atomically thin semiconductors
* 1.9 Integrated photonic tensor core
* 2 Nomenclature
* 3 Potential applications
* 4 See also
* 5 References
* 6 External links

## History

Computer systems have frequently complemented the CPU with special-purpose accelerators for specialized tasks, known as coprocessors. Notable application-specific hardware units include video cards for graphics, sound cards, graphics processing units and digital signal processors. As deep learning and artificial intelligence workloads rose in prominence in the 2010s, specialized hardware units were developed or adapted from existing products to accelerate these tasks.

### Early attempts

First attempts like Intel's ETANN 80170NX[6] incorporated analog circuits to compute neural functions. Another example for chips of this category is ANNA, a neural net CMOS accelerator developed by Yann LeCun.[7] Later all digital chips like Nestor/Intel Ni1000 followed. As early as 1993, digital signal processors were used as neural network accelerators e.g. to accelerate optical character recognition software.[8] In the 1990s, there were also attempts to create parallel high-throughput systems for workstations aimed at various applications, including neural network simulations.[9][10][11] FPGA-based accelerators were also first explored in the 1990s for both inference[12] and training.[13] Smartphones began incorporating AI accelerators starting with the Qualcomm Snapdragon 820 in 2015.[14][15]

### Heterogeneous computing

Heterogeneous computing refers to incorporating a number of specialized processors in a single system, or even a single chip, each optimized for a specific type of task. Architectures such as the Cell microprocessor[16] have features significantly overlapping with AI accelerators including: support for packed low precision arithmetic, dataflow architecture, and prioritizing 'throughput' over latency. The Cell microprocessor was subsequently applied to a number of tasks[17][18][19] including AI.[20][21][22]

In the 2000s, CPUs also gained increasingly wide SIMD units, driven by video and gaming workloads; as well as support for packed low-precision data types.[23] Due to increasing performance of CPUs, they are also being used for running AI workloads. CPUs are superior for DNNs with DNNs with small or medium-scale parallelism, for sparse DNNs and in low-batch-size scenarios.

### Use of GPU

Graphics processing units or GPUs are specialized hardware for the manipulation of images and calculation of local image properties. The mathematical basis of neural networks and image manipulation are similar, embarrassingly parallel tasks involving matrices, leading GPUs to become increasingly used for machine learning tasks.[24][25][26] (As of 2016), GPUs are popular for AI work, and they continue to evolve in a direction to facilitate deep learning, both for training[27] and inference in devices such as self-driving cars.[28] GPU developers such as Nvidia NVLink are developing additional connective capability for the kind of dataflow workloads AI benefits from.[29] As GPUs have been increasingly applied to AI acceleration, GPU manufacturers have incorporated neural network-specific hardware to further accelerate these tasks.[30][31] Tensor cores are intended to speed up the training of neural networks.[31]

### Use of FPGAs

Deep learning frameworks are still evolving, making it hard to design custom hardware. Reconfigurable devices such as field-programmable gate arrays (FPGA) make it easier to evolve hardware, frameworks, and software alongside each other.[32][12][13][33]

Microsoft has used FPGA chips to accelerate inference.[34]

### Emergence of dedicated AI accelerator ASICs

While GPUs and FPGAs perform far better than CPUs for AI related tasks, a factor of up to 10 in efficiency[35][36] may be gained with a more specific design, via an application-specific integrated circuit (ASIC). These accelerators employ strategies such as optimized memory use and the use of lower precision arithmetic to accelerate calculation and increase throughput of computation.[37][38] Some adopted low-precision floating-point formats used AI acceleration are half-precision and the bfloat16 floating-point format.[39][40][41][42][43][44][45] Companies such as Google, Qualcomm, Amazon, Apple, Facebook, AMD and Samsung are all designing their own AI ASICs.[46][47][48][49][50][51]

### In-memory computing architectures

In June 2017, IBM researchers announced an architecture in contrast to the Von Neumann architecture based on in-memory computing and phase-change memory arrays applied to temporal correlation detection, intending to generalize the approach to heterogeneous computing and massively parallel systems.[52] In October 2018, IBM researchers announced an architecture based on in-memory processing and modeled on the human brain's synaptic network to accelerate deep neural networks.[53] The system is based on phase-change memory arrays.[54]

### In-memory computing with analog resistive memories

In 2019 researchers from Politecnico di Milano found a way to solve systems of linear equations in a few tens of nanoseconds via a single operation. Their algorithm is based on in-memory computing with analog resistive memories which performs with high efficiencies of time and energy, via conducting matrix-vector multiplication in one step using Ohm's law and Kirchhoff's law. The researchers showed that a feedback circuit with cross-point resistive memories can solve algebraic problems such as systems of linear equations, matrix eigenvectors, and differential equations in just one step. Such an approach improves computational times drastically in comparison with digital algorithms.[55]

### Atomically thin semiconductors

In 2020, Marega et al. published experiments with a large-area active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFETs).[56] Such atomically thin semiconductors are considered promising for energy-efficient machine learning applications, where the same basic device structure is used for both logic operations and data storage. The authors used two-dimensional materials such as semiconducting molybdenum disulfide.[56]

### Integrated photonic tensor core

In 2021, J. Feldmann et al. proposed an integrated photonic hardware accelerator for parallel convolutional processing.[57] The authors identify two key advantages of integrated photonics over its electronic counterparts: (1) massively parallel data transfer through wavelength division multiplexing in conjunction with frequency combs, and (2) extremely high data modulation speeds.[57] Their system can execute trillions of multiply-accumulate operations per second, indicating the potential of integrated photonics in data-heavy AI applications.[57]

## Nomenclature

As of 2016, the field is still in flux and vendors are pushing their own marketing term for what amounts to an "AI accelerator", in the hope that their designs and APIs will become the dominant design. There is no consensus on the boundary between these devices, nor the exact form they will take; however several examples clearly aim to fill this new space, with a fair amount of overlap in capabilities.

In the past when consumer graphics accelerators emerged, the industry eventually adopted Nvidia's self-assigned term, "the GPU",[58] as the collective noun for "graphics accelerators", which had taken many forms before settling on an overall pipeline implementing a model presented by Direct3D.

## Potential applications

* Agricultural robots, for example pesticide-free weed control.[59]
* Autonomous vehicles: Nvidia has targeted their Drive PX-series boards at this application.[60]
* Computer-aided diagnosis
* Industrial robots, increasing the range of tasks that can be automated, by adding adaptability to variable situations.
* Machine translation
* Military robots
* Natural-language processing
* Search engines, increasing the energy efficiency of data centers and ability to use increasingly advanced queries.
* Unmanned aerial vehicles, e.g. navigation systems, e.g. the Movidius Myriad 2 has been demonstrated successfully guiding autonomous drones.[61]
* Voice user interface, e.g. in mobile phones, a target for Qualcomm Zeroth.[62]

## See also

* Cognitive computer
* Deep learning processor
* Neuromorphic computing
* Optical neural network
* Physical neural network

## References

1. ↑ "Intel unveils Movidius Compute Stick USB AI Accelerator". July 21, 2017. https://www.v3.co.uk/v3-uk/news/3014293/intel-unveils-movidius-compute-stick-usb-ai-accelerator.
2. ↑ "Inspurs unveils GX4 AI Accelerator". June 21, 2017. https://insidehpc.com/2017/06/inspurs-unveils-gx4-ai-accelerator/.
3. ↑ Wiggers, Kyle (November 6, 2019), Neural Magic raises $15 million to boost AI inferencing speed on off-the-shelf processors, https://venturebeat.com/2019/11/06/neural-magic-raises-15-million-to-boost-ai-training-speed-on-off-the-shelf-processors/, retrieved March 14, 2020
4. ↑ "Google Designing AI Processors". https://www.eetimes.com/google-designing-ai-processors/. Google using its own AI accelerators.
5. ↑ "13 Sextillion & Counting: The Long & Winding Road to the Most Frequently Manufactured Human Artifact in History". April 2, 2018. https://computerhistory.org/blog/13-sextillion-counting-the-long-winding-road-to-the-most-frequently-manufactured-human-artifact-in-history/?key=13-sextillion-counting-the-long-winding-road-to-the-most-frequently-manufactured-human-artifact-in-history.
6. ↑ John C. Dvorak: Intel’s 80170 chip has the theoretical intelligence of a cockroach in PC Magazine Volume 9 Number 10 (May 1990), p. 77, [1], retrieved May 16, 2021
7. ↑ "Application of the ANNA Neural Network Chip to High-Speed Character Recognition". http://yann.lecun.com/exdb/publis/pdf/saeckinger-92.pdf.
8. ↑ "convolutional neural network demo from 1993 featuring DSP32 accelerator". https://www.youtube.com/watch?v=FwFduRA_L6Q.
9. ↑ "design of a connectionist network supercomputer". http://people.eecs.berkeley.edu/~krste/papers/cns-injs1993.ps.
10. ↑ "The end of general purpose computers (not)". https://www.youtube.com/watch?v=VtJthbiiTBQ. This presentation covers a past attempt at neural net accelerators, notes the similarity to the modern SLI GPGPU processor setup, and argues that general purpose vector accelerators are the way forward (in relation to RISC-V hwacha project. Argues that NN's are just dense and sparse matrices, one of several recurring algorithms)
11. ↑ Ramacher, U.; Raab, W.; Hachmann, J.A.U.; Beichter, J.; Bruls, N.; Wesseling, M.; Sicheneder, E.; Glass, J. et al. (1995). Proceedings of 9th International Parallel Processing Symposium. pp. 774–781. doi:10.1109/IPPS.1995.395862. ISBN 978-0-8186-7074-9.
12. ↑ 12.0 12.1 "Space Efficient Neural Net Implementation". https://www.researchgate.net/publication/2318589.
13. ↑ 13.0 13.1 Gschwind, M.; Salapura, V.; Maischberger, O. (1996). "A Generic Building Block for Hopfield Neural Networks with On-Chip Learning". 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96. pp. 49–52. doi:10.1109/ISCAS.1996.598474. ISBN 0-7803-3073-0.
14. ↑ "Qualcomm Helps Make Your Mobile Devices Smarter With New Snapdragon Machine Learning Software Development Kit". https://www.qualcomm.com/news/releases/2016/05/02/qualcomm-helps-make-your-mobile-devices-smarter-new-snapdragon-machine.
15. ↑ Rubin, Ben Fox. "Qualcomm's Zeroth platform could make your smartphone much smarter" (in en). https://www.cnet.com/tech/mobile/qualcomms-zeroth-platform-could-make-your-smartphone-much-smarter/.
16. ↑ Gschwind, Michael; Hofstee, H. Peter; Flachs, Brian; Hopkins, Martin; Watanabe, Yukio; Yamazaki, Takeshi (2006). "Synergistic Processing in Cell's Multicore Architecture". IEEE Micro 26 (2): 10–24. doi:10.1109/MM.2006.41.
17. ↑ De Fabritiis, G. (2007). "Performance of Cell processor for biomolecular simulations". Computer Physics Communications 176 (11–12): 660–664. doi:10.1016/j.cpc.2007.02.107.
18. ↑ Video Processing and Retrieval on Cell architecture.
19. ↑ Benthin, Carsten; Wald, Ingo; Scherbaum, Michael; Friedrich, Heiko (2006). 2006 IEEE Symposium on Interactive Ray Tracing. pp. 15–23. doi:10.1109/RT.2006.280210. ISBN 978-1-4244-0693-7.
20. ↑ "Development of an artificial neural network on a heterogeneous multicore architecture to predict a successful weight loss in obese individuals". https://www.teco.edu/~scholz/papers/ScholzDiploma.pdf.
21. ↑ Kwon, Bomjun; Choi, Taiho; Chung, Heejin; Kim, Geonho (2008). 2008 5th IEEE Consumer Communications and Networking Conference. pp. 1030–1034. doi:10.1109/ccnc08.2007.235. ISBN 978-1-4244-1457-4.
22. ↑ Duan, Rubing; Strey, Alfred (2008). Euro-Par 2008 – Parallel Processing. Lecture Notes in Computer Science. 5168. pp. 665–675. doi:10.1007/978-3-540-85451-7_71. ISBN 978-3-540-85450-0.
23. ↑ "Improving the performance of video with AVX". February 8, 2012. https://software.intel.com/content/www/us/en/develop/articles/improving-the-compute-performance-of-video-processing-software-using-avx-advanced-vector-extensions-instructions.html.
24. ↑ "microsoft research/pixel shaders/MNIST". https://hal.inria.fr/inria-00112631/document.
25. ↑ "How GPU came to be used for general computation". http://igoro.com/archive/how-gpu-came-to-be-used-for-general-computation/.
26. ↑ "ImageNet Classification with Deep Convolutional Neural Networks". https://papers.nips.cc/paper/2012/file/c399862d3b9d6b76c8436e924a68c45b-Paper.pdf.
27. ↑ "nvidia driving the development of deep learning". May 17, 2016. https://insidehpc.com/2016/05/nvidia-driving-the-development-of-deep-learning/.
28. ↑ "Nvidia introduces supercomputer for self driving cars". January 6, 2016. http://gas2.org/2016/01/06/nvidia-introduces-supercomputer-for-self-driving-cars/.
29. ↑ "how nvlink will enable faster easier multi GPU computing". November 14, 2014. https://developer.nvidia.com/blog/how-nvlink-will-enable-faster-easier-multi-gpu-computing/.
30. ↑ "A Survey on Optimized Implementation of Deep Learning Models on the NVIDIA Jetson Platform", 2019
31. ↑ 31.0 31.1 Harris, Mark (May 11, 2017). "CUDA 9 Features Revealed: Volta, Cooperative Groups and More". https://developer.nvidia.com/blog/cuda-9-features-revealed/.
32. ↑ Sefat, Md Syadus; Aslan, Semih; Kellington, Jeffrey W; Qasem, Apan (August 2019). "Accelerating HotSpots in Deep Neural Networks on a CAPI-Based FPGA". 2019 IEEE 21st International Conference on High Performance Computing and Communications; IEEE 17th International Conference on Smart City; IEEE 5th International Conference on Data Science and Systems (HPCC/SmartCity/DSS): 248–256. doi:10.1109/HPCC/SmartCity/DSS.2019.00048. ISBN 978-1-7281-2058-4. https://ieeexplore.ieee.org/document/8855410.
33. ↑ "FPGA Based Deep Learning Accelerators Take on ASICs". August 23, 2016. http://www.nextplatform.com/2016/08/23/fpga-based-deep-learning-accelerators-take-asics/.
34. ↑ "Project Brainwave" (in en-US). https://www.microsoft.com/en-us/research/project/project-brainwave/.
35. ↑ "Google boosts machine learning with its Tensor Processing Unit". May 19, 2016. https://techreport.com/news/30155/google-boosts-machine-learning-with-its-tensor-processing-unit/.
36. ↑ "Chip could bring deep learning to mobile devices". February 3, 2016. https://www.sciencedaily.com/releases/2016/02/160203134840.htm.
37. ↑ "Deep Learning with Limited Numerical Precision". http://proceedings.mlr.press/v37/gupta15.pdf.
38. ↑ Rastegari, Mohammad; Ordonez, Vicente; Redmon, Joseph; Farhadi, Ali (2016). "XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks". arXiv:1603.05279 [cs.CV].
39. ↑ Khari Johnson (May 23, 2018). "Intel unveils Nervana Neural Net L-1000 for accelerated AI training". VentureBeat. https://venturebeat.com/2018/05/23/intel-unveils-nervana-neural-net-l-1000-for-accelerated-ai-training/. "...Intel will be extending bfloat16 support across our AI product lines, including Intel Xeon processors and Intel FPGAs."
40. ↑ Michael Feldman (May 23, 2018). "Intel Lays Out New Roadmap for AI Portfolio". TOP500 Supercomputer Sites. https://www.top500.org/news/intel-lays-out-new-roadmap-for-ai-portfolio/. "Intel plans to support this format across all their AI products, including the Xeon and FPGA lines"
41. ↑ Lucian Armasu (May 23, 2018). "Intel To Launch Spring Crest, Its First Neural Network Processor, In 2019". Tom's Hardware. https://www.tomshardware.com/news/intel-neural-network-processor-lake-crest,37105.html. "Intel said that the NNP-L1000 would also support bfloat16, a numerical format that’s being adopted by all the ML industry players for neural networks. The company will also support bfloat16 in its FPGAs, Xeons, and other ML products. The Nervana NNP-L1000 is scheduled for release in 2019."
42. ↑ "Available TensorFlow Ops | Cloud TPU | Google Cloud". Google Cloud. https://cloud.google.com/tpu/docs/tensorflow-ops. "This page lists the TensorFlow Python APIs and graph operators available on Cloud TPU."
43. ↑ Elmar Haußmann (April 26, 2018). "Comparing Google's TPUv2 against Nvidia's V100 on ResNet-50". RiseML Blog. https://blog.riseml.com/comparing-google-tpuv2-against-nvidia-v100-on-resnet-50-c2bbb6a51e5e. "For the Cloud TPU, Google recommended we use the bfloat16 implementation from the official TPU repository with TensorFlow 1.7.0. Both the TPU and GPU implementations make use of mixed-precision computation on the respective architecture and store most tensors with half-precision."
44. ↑ Tensorflow Authors (February 28, 2018). "ResNet-50 using BFloat16 on TPU". Google. https://github.com/tensorflow/tpu/tree/master/models/experimental/resnet_bfloat16.
45. ↑ Joshua V. Dillon; Ian Langmore; Dustin Tran; Eugene Brevdo; Srinivas Vasudevan; Dave Moore; Brian Patton; Alex Alemi et al. (November 28, 2017). ﻿TensorFlow Distributions﻿ (Report). Accessed May 23, 2018. "All operations in TensorFlow Distributions are numerically stable across half, single, and double floating-point precisions (as TensorFlow dtypes: tf.bfloat16 (truncated floating point), tf.float16, tf.float32, tf.float64). Class constructors have a validate_args flag for numerical asserts"
46. ↑ "Google Reveals a Powerful New AI Chip and Supercomputer" (in en). https://www.technologyreview.com/2017/05/17/151656/google-reveals-a-powerful-new-ai-chip-and-supercomputer/.
47. ↑ "What to Expect From Apple's Neural Engine in the A11 Bionic SoC – ExtremeTech". https://www.extremetech.com/mobile/255780-apple-neural-engine-a11-bionic-soc.
48. ↑ "Facebook has a new job posting calling for chip designers". https://social.techcrunch.com/2018/04/18/facebook-has-a-new-job-posting-calling-for-chip-designers/.
49. ↑ "Facebook joins Amazon and Google in AI chip race". https://www.ft.com/content/1c2aab18-3337-11e9-bd3a-8b2a211d90d5.
50. ↑ Amadeo, Ron (May 11, 2021). "Samsung and AMD will reportedly take on Apple's M1 SoC later this year" (in en-us). https://arstechnica.com/gadgets/2021/05/report-the-samsung-amd-exynos-soc-will-be-out-for-laptops-this-year/.
51. ↑ Smith, Ryan. "The AI Race Expands: Qualcomm Reveals “Cloud AI 100” Family of Datacenter AI Inference Accelerators for 2020". https://www.anandtech.com/show/14187/qualcomm-reveals-cloud-ai-100-family-of-datacenter-ai-inference-accelerators-for-2020.
52. ↑ Abu Sebastian; Tomas Tuma; Nikolaos Papandreou; Manuel Le Gallo; Lukas Kull; Thomas Parnell; Evangelos Eleftheriou (2017). "Temporal correlation detection using computational phase-change memory". Nature Communications 8 (1): 1115. doi:10.1038/s41467-017-01481-9. PMID 29062022.
53. ↑ "A new brain-inspired architecture could improve how computers handle data and advance AI". American Institute of Physics. October 3, 2018. https://phys.org/news/2018-10-brain-inspired-architecture-advance-ai.html.
54. ↑ Carlos Ríos; Nathan Youngblood; Zengguang Cheng; Manuel Le Gallo; Wolfram H.P. Pernice; C. David Wright; Abu Sebastian; Harish Bhaskaran (2018). "In-memory computing on a photonic platform". arXiv:1801.06228 [cs.ET].
55. ↑ Zhong Sun; Giacomo Pedretti; Elia Ambrosi; Alessandro Bricalli; Wei Wang; Daniele Ielmini (2019). "Solving matrix equations in one step with cross-point resistive arrays". Proceedings of the National Academy of Sciences 116 (10): 4123–4128. doi:10.1073/pnas.1815682116. PMID 30782810.
56. ↑ 56.0 56.1 Marega, Guilherme Migliato; Zhao, Yanfei; Avsar, Ahmet; Wang, Zhenyu; Tripati, Mukesh; Radenovic, Aleksandra; Kis, Anras (2020). "Logic-in-memory based on an atomically thin semiconductor". Nature 587 (2): 72–77. doi:10.1038/s41586-020-2861-0. PMID 33149289.
57. ↑ 57.0 57.1 57.2 Feldmann, J.; Youngblood, N.; Karpov, M. et al. (2021). "Parallel convolutional processing using an integrated photonic tensor". Nature 589 (2): 52–58. doi:10.1038/s41586-020-03070-1. PMID 33408373.
58. ↑ "NVIDIA launches the World's First Graphics Processing Unit, the GeForce 256". http://www.nvidia.com/object/IO_20020111_5424.html.
59. ↑ Design of a machine vision system for weed control. https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.7.342&rep=rep1&type=pdf. Retrieved July 29, 2021.
60. ↑ "Self-Driving Cars Technology & Solutions from NVIDIA Automotive". https://www.nvidia.com/en-us/self-driving-cars/.
61. ↑ "movidius powers worlds most intelligent drone". March 16, 2016. https://www.siliconrepublic.com/machines/movidius-dji-drone.
62. ↑ "Qualcomm Research brings server class machine learning to everyday devices–making them smarter [VIDEO"]. October 2015. https://www.qualcomm.com/news/onq/2015/10/01/qualcomm-research-brings-server-class-machine-learning-everyday-devices-making.

## External links

* Nvidia Puts The Accelerator To The Metal With Pascal.htm, The Next Platform
* Eyeriss Project, MIT
* https://alphaics.ai/

* v
* t
* e

Hardware acceleration

Theory|

* Universal Turing machine
* Parallel computing
* Distributed computing

Applications|

* GPU
* GPGPU
* DirectX
* Audio
* Digital signal processing
* Hardware random number generation
* Artificial intelligence
* Cryptography
* TLS
* Machine vision
* Custom hardware attack
* scrypt
* Networking

Implementations|

* High-level synthesis
* C to HDL
* FPGA
* ASIC
* CPLD
* System on Chip
* Network on Chip

Architectures|

* Data flow
* Transport triggered
* Multicore
* Manycore
* Heterogeneous
* In-memory computing
* Systolic array
* Neuromorphic

Related|

* Programmable logic
* Processor
* design
* chronology
* Digital electronics
* Virtualization
* Hardware emulation
* Logic synthesis
* Embedded systems

0.00

(0 votes)

Original source: https://en.wikipedia.orghttps://handwiki.org/wiki/ AI accelerator. Read more

|

Retrieved from "https://handwiki.orghttps://handwiki.org/wiki/index.php?title=AI_accelerator&oldid=2421657"
*[v]: View this template
*[t]: Discuss this template
*[e]: Edit this template