Deep learning processor

Short description: Specially designed circuitry

A deep learning processor (DLP), or a deep learning accelerator, is an electronic circuit designed for deep learning algorithms, usually with separate data memory and dedicated instruction set architecture. Deep learning processors range from mobile devices, such as neural processing units (NPUs) in Huawei cellphones,[1] to cloud computing servers such as tensor processing units (TPU) in the Google Cloud Platform.[2]

The goal of DLPs is to provide higher efficiency and performance for deep learning algorithms than general central processing unit (CPUs) and graphics processing units (GPUs) would. Most DLPs employ a large number of computing components to leverage high data-level parallelism, a relatively larger on-chip buffer/memory to leverage the data reuse patterns, and limited data-width operators for error-resilience of deep learning. Deep learning processors differ from AI accelerators in that they are specialized for running learning algorithms, while AI accelerators are typically more specialized for inference. However, the two terms (DLP vs AI accelerator) are not used rigorously and there is often overlap between the two.

## Contents

* 1 History
* 1.1 The use of CPUs/GPUs
* 1.2 The first DLP
* 1.3 The blooming DLPs
* 2 DLP architecture
* 2.1 Digital DLPs
* 2.2 Hybrid DLPs
* 3 GPUs and FPGAs
* 4 Atomically thin semiconductors for deep learning
* 5 Integrated photonic tensor core
* 6 Benchmarks
* 7 See also
* 8 References

## History

### The use of CPUs/GPUs

At the beginning, general CPUs were adopted to perform deep learning algorithms. Later, GPUs are introduced to the domain of deep learning. For example, in 2012, Alex Krizhevsky adopted two GPUs to train a deep learning network, i.e., AlexNet,[3] which won the champion of the ISLVRC-2012 competition. As the interests in deep learning algorithms and DLPs keep increasing, GPU manufacturers start to add deep learning related features in both hardware (e.g., INT8 operators) and software (e.g., cuDNN Library). For example, Nvidia even released the Turing Tensor Core—a DLP—to accelerate deep learning processing.

### The first DLP

To provide higher efficiency in performance and energy, domain-specific design starts to draw a great attention. In 2014, Chen et al. proposed the first DLP in the world, DianNao (Chinese for "electric brain"),[4] to accelerate deep neural networks especially. DianNao provides the 452 Gop/s peak performance (of key operations in deep neural networks) only in a small footprint of 3.02 mm2 and 485 mW. Later, the successors (DaDianNao,[5] ShiDianNao,[6] PuDianNao[7]) are proposed by the same group, forming the DianNao Family[8]

### The blooming DLPs

Inspired from the pioneer work of DianNao Family, many DLPs are proposed in both academia and industry with design optimized to leverage the features of deep neural networks for high efficiency. Only at ISCA 2016, three sessions, 15% (!) of the accepted papers, are all architecture designs about deep learning. Such efforts include Eyeriss[9] (MIT), EIE[10] (Stanford), Minerva[11] (Harvard), Stripes[12] (University of Toronto) in academia, and TPU[13] (Google), MLU[14] (Cambricon) in industry. We listed several representative works in Table 1.

Table 1. Typical DLPs

Year  | DLPs  | Institution  | Type  | Computation  | Memory Hierarchy  | Control  | Peak Performance
2014  | DianNao[4] | ICT, CAS  | digital  | vector MACs | scratchpad  | VLIW | 452 Gops (16-bit)
DaDianNao[5] | ICT, CAS  | digital  | vector MACs  | scratchpad  | VLIW  | 5.58 Tops (16-bit)
2015  | ShiDianNao[6] | ICT, CAS  | digital  | scalar MACs  | scratchpad  | VLIW  | 194 Gops (16-bit)
PuDianNao[7] | ICT, CAS  | digital  | vector MACs  | scratchpad  | VLIW  | 1,056 Gops (16-bit)
2016  | DnnWeaver  | Georgia Tech  | digital  | Vector MACs  | scratchpad  | \-  | \-
EIE[10] | Stanford  | digital  | scalar MACs  | scratchpad  | \-  | 102 Gops (16-bit)
Eyeriss[9] | MIT  | digital  | scalar MACs  | scratchpad  | \-  | 67.2 Gops (16-bit)
Prime[15] | UCSB  | hybrid  | Process-in-Memory | ReRAM  | \-  | \-
2017  | TPU[13] | Google  | digital  | scalar MACs  | scratchpad  | CISC | 92 Tops (8-bit)
PipeLayer[16] | U of Pittsburgh  | hybrid  | Process-in-Memory  | ReRAM  | \-  |
FlexFlow  | ICT, CAS  | digital  | scalar MACs  | scratchpad  | \-  | 420 Gops ()
2018  | MAERI  | Georgia Tech  | digital  | scalar MACs  | scratchpad  | \-  |
PermDNN  | City University of New York  | digital  | vector MACs  | scratchpad  | \-  | 614.4 Gops (16-bit)
2019  | FPSA  | Tsinghua  | hybrid  | Process-in-Memory  | ReRAM  | \-  |
Cambricon-F  | ICT, CAS  | digital  | vector MACs  | scratchpad  | FISA  | 14.9 Tops (F1, 16-bit)

956 Tops (F100, 16-bit)

## DLP architecture

With the rapid evolution of deep learning algorithms and DLPs, many architectures have been explored. Roughly, DLPs can be classified into three categories based on their implementation: digital circuits, analog circuits, and hybrid circuits. As the pure analog DLPs are rarely seen, we introduce the digital DLPs and hybrid DLPs.

### Digital DLPs

The major components of DLPs architecture usually include a computation component, the on-chip memory hierarchy, and the control logic that manages the data communication and computing flows.

Regarding the computation component, as most operations in deep learning can be aggregated into vector operations, the most common ways for building computation components in digital DLPs are the MAC-based (multiplier-accumulation) organization, either with vector MACs[4][5][7] or scalar MACs.[13][6][9] Rather than SIMD or SIMT in general processing devices, deep learning domain-specific parallelism is better explored on these MAC-based organizations. Regarding the memory hierarchy, as deep learning algorithms require high bandwidth to provide the computation component with sufficient data, DLPs usually employ a relatively larger size (tens of kilobytes or several megabytes) on-chip buffer but with dedicated on-chip data reuse strategy and data exchange strategy to alleviate the burden for memory bandwidth. For example, DianNao, 16 16-in vector MAC, requires 16 × 16 × 2 = 512 16-bit data, i.e., almost 1024GB/s bandwidth requirements between computation components and buffers. With on-chip reuse, such bandwidth requirements are reduced drastically.[4] Instead of the widely used cache in general processing devices, DLPs always use scratchpad memory as it could provide higher data reuse opportunities by leveraging the relatively regular data access pattern in deep learning algorithms. Regarding the control logic, as the deep learning algorithms keep evolving at a dramatic speed, DLPs start to leverage dedicated ISA (instruction set architecture) to support the deep learning domain flexibly. At first, DianNao used a VLIW-style instruction set where each instruction could finish a layer in a DNN. Cambricon[17] introduces the first deep learning domain-specific ISA, which could support more than ten different deep learning algorithms. TPU also reveals five key instructions from the CISC-style ISA.

### Hybrid DLPs

Hybrid DLPs emerge for DNN inference and training acceleration because of their high efficiency. Processing-in-memory (PIM) architectures are one most important type of hybrid DLP. The key design concept of PIM is to bridge the gap between computing and memory, with the following manners: 1) Moving computation components into memory cells, controllers, or memory chips to alleviate the memory wall issue.[16][18][19] Such architectures significantly shorten data paths and leverage much higher internal bandwidth, hence resulting in attractive performance improvement. 2) Build high efficient DNN engines by adopting computational devices. In 2013, HP Lab demonstrated the astonishing capability of adopting ReRAM crossbar structure for computing.[20] Inspiring by this work, tremendous work are proposed to explore the new architecture and system design based on ReRAM,[15][21][22][16] phase change memory,[18][23][24] etc.

## GPUs and FPGAs

Despite the DLPs, GPUs and FPGAs are also being used as accelerators to speed up the execution of deep learning algorithms. For example, Summit, a supercomputer from IBM for Oak Ridge National Laboratory,[25] contains 27,648 Nvidia Tesla V100 cards, which can be used to accelerate deep learning algorithms. Microsoft builds its deep learning platform using FPGAs in its Azure to support real-time deep learning services.[26] In Table 2 we compare the DLPs against GPUs and FPGAs in terms of target, performance, energy efficiency, and flexibility.

Table 2. DLPs vs. GPUs vs. FPGAs  | Target  | Performance  | Energy Efficiency  | Flexibility

|
|
|
|

DLPs  | deep learning  | high  | high  | domain-specific
FPGAs  | all  | low  | moderate  | general
GPUs  | matrix computation  | moderate  | low  | matrix applications

## Atomically thin semiconductors for deep learning

Atomically thin semiconductors are considered promising for energy-efficient deep learning hardware where the same basic device structure is used for both logic operations and data storage. In 2020, Marega et al. published experiments with a large-area active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFETs).[27] They use two-dimensional materials such as semiconducting molybdenum disulphide to precisely tune FGFETs as building blocks in which logic operations can be performed with the memory elements. [27]

## Integrated photonic tensor core

In 2021, J. Feldmann et al. proposed an integrated photonic hardware accelerator for parallel convolutional processing.[28] The authors identify two key advantages of integrated photonics over its electronic counterparts: (1) massively parallel data transfer through wavelength division multiplexing in conjunction with frequency combs, and (2) extremely high data modulation speeds.[28] Their system can execute trillions of multiply-accumulate operations per second, indicating the potential of integrated photonics in data-heavy AI applications.[28]

## Benchmarks

Benchmarking has served long as the foundation of designing new hardware architectures, where both architects and practitioners can compare various architectures, identify their bottlenecks, and conduct the corresponding system/architectural optimization. Table 3 lists several typical benchmarks for DLPs, dating from the year 2012 in time order.

Table 3. Benchmarks.  Year  | NN Benchmark  | Affiliations  | # of microbenchmarks  | # of component benchmarks  | # of application benchmarks

|
|
|
|
|

2012  | BenchNN  | ICT, CAS  | N/A  | 12  | N/A
2016  | Fathom  | Harvard  | N/A  | 8  | N/A
2017  | BenchIP  | ICT, CAS  | 12  | 11  | N/A
2017  | DAWNBench | Stanford  | 8  | N/A  | N/A
2017  | DeepBench | Baidu  | 4  | N/A  | N/A
2018  | MLPerf | Harvard, Intel, and Google, etc.  | N/A  | 7  | N/A
2019  | AIBench | ICT, CAS and Alibaba, etc.  | 12  | 16  | 2
2019  | NNBench-X  | UCSB  | N/A  | 10  | N/A

## See also

* AI accelerator
* Cerebras Systems

## References

1. ↑ "HUAWEI Reveals the Future of Mobile AI at IFA". https://consumer.huawei.com/en/press/news/2017/ifa2017-kirin970.
2. ↑ P, JouppiNorman; YoungCliff; PatilNishant; PattersonDavid; AgrawalGaurav; BajwaRaminder; BatesSarah; BhatiaSuresh et al. (2017-06-24). "In-Datacenter Performance Analysis of a Tensor Processing Unit" (in EN). ACM SIGARCH Computer Architecture News 45 (2): 1–12. doi:10.1145/3140659.3080246.
3. ↑ Krizhevsky, Alex; Sutskever, Ilya; Hinton, Geoffrey E (2017-05-24). "ImageNet classification with deep convolutional neural networks" (in EN). Communications of the ACM 60 (6): 84–90. doi:10.1145/3065386.
4. ↑ 4.0 4.1 4.2 4.3 Chen, Tianshi; Du, Zidong; Sun, Ninghui; Wang, Jia; Wu, Chengyong; Chen, Yunji; Temam, Olivier (2014-04-05). "DianNao". ACM SIGARCH Computer Architecture News 42 (1): 269–284. doi:10.1145/2654822.2541967. ISSN 0163-5964.
5. ↑ 5.0 5.1 5.2 Chen, Yunji; Luo, Tao; Liu, Shaoli; Zhang, Shijin; He, Liqiang; Wang, Jia; Li, Ling; Chen, Tianshi et al. (December 2014). "DaDianNao: A Machine-Learning Supercomputer". 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture (IEEE): 609–622. doi:10.1109/micro.2014.58. ISBN 978-1-4799-6998-2.
6. ↑ 6.0 6.1 6.2 Du, Zidong; Fasthuber, Robert; Chen, Tianshi; Ienne, Paolo; Li, Ling; Luo, Tao; Feng, Xiaobing; Chen, Yunji et al. (2016-01-04). "ShiDianNao". ACM SIGARCH Computer Architecture News 43 (3S): 92–104. doi:10.1145/2872887.2750389. ISSN 0163-5964.
7. ↑ 7.0 7.1 7.2 Liu, Daofu; Chen, Tianshi; Liu, Shaoli; Zhou, Jinhong; Zhou, Shengyuan; Teman, Olivier; Feng, Xiaobing; Zhou, Xuehai et al. (2015-05-29). "PuDianNao". ACM SIGARCH Computer Architecture News 43 (1): 369–381. doi:10.1145/2786763.2694358. ISSN 0163-5964.
8. ↑ Chen, Yunji; Chen, Tianshi; Xu, Zhiwei; Sun, Ninghui; Temam, Olivier (2016-10-28). "DianNao family". Communications of the ACM 59 (11): 105–112. doi:10.1145/2996864. ISSN 0001-0782.
9. ↑ 9.0 9.1 9.2 Chen, Yu-Hsin; Emer, Joel; Sze, Vivienne (2017). "Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks". IEEE Micro: 1. doi:10.1109/mm.2017.265085944. ISSN 0272-1732.
10. ↑ 10.0 10.1 Han, Song; Liu, Xingyu; Mao, Huizi; Pu, Jing; Pedram, Ardavan; Horowitz, Mark A.; Dally, William J. (2016-02-03). EIE: Efficient Inference Engine on Compressed Deep Neural Network. OCLC 1106232247.
11. ↑ Reagen, Brandon; Whatmough, Paul; Adolf, Robert; Rama, Saketh; Lee, Hyunkwang; Lee, Sae Kyu; Hernandez-Lobato, Jose Miguel; Wei, Gu-Yeon et al. (June 2016). "Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators". 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) (Seoul: IEEE): 267–278. doi:10.1109/ISCA.2016.32. ISBN 978-1-4673-8947-1.
12. ↑ Judd, Patrick; Albericio, Jorge; Moshovos, Andreas (2017-01-01). "Stripes: Bit-Serial Deep Neural Network Computing". IEEE Computer Architecture Letters 16 (1): 80–83. doi:10.1109/lca.2016.2597140. ISSN 1556-6056.
13. ↑ 13.0 13.1 13.2 (in EN) In-Datacenter Performance Analysis of a Tensor Processing Unit | Proceedings of the 44th Annual International Symposium on Computer Architecture. doi:10.1145/3079856.3080246.
14. ↑ "MLU 100 intelligence accelerator card". https://www.cambricon.com/index.php?m=content&c=index&a=lists&catid=21.
15. ↑ 15.0 15.1 Chi, Ping; Li, Shuangchen; Xu, Cong; Zhang, Tao; Zhao, Jishen; Liu, Yongpan; Wang, Yu; Xie, Yuan (June 2016). "PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory". 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) (IEEE): 27–39. doi:10.1109/isca.2016.13. ISBN 978-1-4673-8947-1.
16. ↑ 16.0 16.1 16.2 Song, Linghao; Qian, Xuehai; Li, Hai; Chen, Yiran (February 2017). "PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning". 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) (IEEE): 541–552. doi:10.1109/hpca.2017.55. ISBN 978-1-5090-4985-1.
17. ↑ Liu, Shaoli; Du, Zidong; Tao, Jinhua; Han, Dong; Luo, Tao; Xie, Yuan; Chen, Yunji; Chen, Tianshi (June 2016). "Cambricon: An Instruction Set Architecture for Neural Networks". 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) (IEEE): 393–405. doi:10.1109/isca.2016.42. ISBN 978-1-4673-8947-1.
18. ↑ 18.0 18.1 Ambrogio, Stefano; Narayanan, Pritish; Tsai, Hsinyu; Shelby, Robert M.; Boybat, Irem; di Nolfo, Carmelo; Sidler, Severin; Giordano, Massimo et al. (June 2018). "Equivalent-accuracy accelerated neural-network training using analogue memory". Nature 558 (7708): 60–67. doi:10.1038/s41586-018-0180-5. ISSN 0028-0836. PMID 29875487.
19. ↑ Chen, Wei-Hao; Lin, Wen-Jang; Lai, Li-Ya; Li, Shuangchen; Hsu, Chien-Hua; Lin, Huan-Ting; Lee, Heng-Yuan; Su, Jian-Wei et al. (December 2017). "A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme". 2017 IEEE International Electron Devices Meeting (IEDM) (IEEE): 28.2.1–28.2.4. doi:10.1109/iedm.2017.8268468. ISBN 978-1-5386-3559-9.
20. ↑ Yang, J. Joshua; Strukov, Dmitri B.; Stewart, Duncan R. (January 2013). "Memristive devices for computing" (in en). Nature Nanotechnology 8 (1): 13–24. doi:10.1038/nnano.2012.240. ISSN 1748-3395. PMID 23269430. https://www.nature.com/articles/nnano.2012.240.
21. ↑ Shafiee, Ali; Nag, Anirban; Muralimanohar, Naveen; Balasubramonian, Rajeev; Strachan, John Paul; Hu, Miao; Williams, R. Stanley; Srikumar, Vivek (2016-10-12). "ISAAC". ACM SIGARCH Computer Architecture News 44 (3): 14–26. doi:10.1145/3007787.3001139. ISSN 0163-5964.
22. ↑ Ji, Yu Zhang, Youyang Xie, Xinfeng Li, Shuangchen Wang, Peiqi Hu, Xing Zhang, Youhui Xie, Yuan (2019-01-27). FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture. OCLC 1106329050.
23. ↑ Nandakumar, S. R.; Boybat, Irem; Joshi, Vinay; Piveteau, Christophe; Le Gallo, Manuel; Rajendran, Bipin; Sebastian, Abu; Eleftheriou, Evangelos (November 2019). "Phase-Change Memory Models for Deep Learning Training and Inference". 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (IEEE): 727–730. doi:10.1109/icecs46596.2019.8964852. ISBN 978-1-7281-0996-1.
24. ↑ Joshi, Vinay; Le Gallo, Manuel; Haefeli, Simon; Boybat, Irem; Nandakumar, S. R.; Piveteau, Christophe; Dazzi, Martino; Rajendran, Bipin et al. (2020-05-18). "Accurate deep neural network inference using computational phase-change memory". Nature Communications 11 (1): 2473. doi:10.1038/s41467-020-16108-9. ISSN 2041-1723. PMID 32424184.
25. ↑ "Summit: Oak Ridge National Laboratory's 200 petaflop supercomputer". https://www.olcf.ornl.gov/olcf-resources/compute-systems/summit/.
26. ↑ "Microsoft unveils Project Brainwave for real-time AI". https://www.microsoft.com/en-us/research/blog/microsoft-unveils-project-brainwave/.
27. ↑ 27.0 27.1 Marega, Guilherme Migliato; Zhao, Yanfei; Avsar, Ahmet; Wang, Zhenyu; Tripati, Mukesh; Radenovic, Aleksandra; Kis, Anras (2020). "Logic-in-memory based on an atomically thin semiconductor". Nature 587 (2): 72–77. doi:10.1038/s41586-020-2861-0. PMID 33149289.
28. ↑ 28.0 28.1 28.2 Feldmann, J.; Youngblood, N.; Karpov, M. et al. (2021). "Parallel convolutional processing using an integrated photonic tensor". Nature 589 (2): 52–58. doi:10.1038/s41586-020-03070-1. PMID 33408373.

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