Advanced Power Management

Short description: API for power management in IBM-compatible computers

Advanced Power ManagementStatus| Deprecated

|

First published| 1992
Latest version| 1.2
1996
Organization| Intel, Microsoft
Domain| Power management
Abbreviation| APM

Advanced power management (APM) is a technical standard for power management developed by Intel and Microsoft and released in 1992[1] which enables an operating system running an IBM-compatible personal computer to work with the BIOS (part of the computer's firmware) to achieve power management.[2]

Revision 1.2 was the last version of the APM specification, released in 1996. ACPI is the successor to APM. Microsoft dropped support for APM in Windows Vista. The Linux kernel still mostly supports APM, though support for APM CPU idle was dropped in version 3.0.

## Contents

* 1 Overview
* 2 Power management events
* 3 APM functions
* 4 Power states
* 4.1 System power states
* 4.2 Device power states
* 5 Hardware components
* 5.1 CPU
* 5.2 ATA drives
* 6 See also
* 7 References
* 8 External links

## Overview

The layers in APM

APM uses a layered approach to manage devices. APM-aware applications (which include device drivers) talk to an OS-specific APM driver. This driver communicates to the APM-aware BIOS, which controls the hardware. There is the ability to opt out of APM control on a device-by-device basis, which can be used if a driver wants to communicate directly with a hardware device.

Communication occurs both ways; power management events are sent from the BIOS to the APM driver, and the APM driver sends information and requests to the BIOS via function calls. In this way the APM driver is an intermediary between the BIOS and the operating system.

Power management happens in two ways; through the above-mentioned function calls from the APM driver to the BIOS requesting power state changes, and automatically based on device activity.

In APM 1.0 and APM 1.1, power management is almost fully controlled by the BIOS. In APM 1.2, the operating system can control PM time (e.g. suspend timeout).

In 1997, Phoenix Technologies released "APM 2.0" which is a kernel device driver compatible with an APM 1.2 BIOS.[3]

## Power management events

There are 12 power events (such as standby, suspend and resume requests, and low battery notifications), plus OEM-defined events, that can be sent from the APM BIOS to the operating system. The APM driver regularly polls for event change notifications.

Power Management Events:[1]

Name | Code | Comment

|
|

System Standby Request Notification | 0x0001 |
System Suspend Request Notification | 0x0002 |
Normal Resume System Notification | 0x0003 |
Critical Resume System Notification | 0x0004 |
Battery Low Notification | 0x0005 |
Power Status Change Notification | 0x0006 |
Update Time Notification | 0x0007 |
Critical System Suspend Notification | 0x0008 |
User System Standby Request Notification | 0x0009 |
User System Suspend Request Notification | 0x000A |
System Standby Resume Notification | 0x000B |
Capabilities Change Notification | 0x000C | Due to setup or device insertion/removal

## APM functions

There are 21 APM function calls defined that the APM driver can use to query power management statuses, or request power state transitions.[1] Example function calls include letting the BIOS know about current CPU usage (the BIOS may respond to such a call by placing the CPU in a low-power state, or returning it to its full-power state), retrieving the current power state of a device, or requesting a power state change.

Name | Code | Comment

|
|

APM Installation Check | 0x00 |
APM Real Mode Interface Connect | 0x01 |
APM Protected Mode 16-bit Interface Connect | 0x02 | Avoids real or virtual86 mode.
APM Protected Mode 32-bit Interface Connect | 0x03 | Avoids real or virtual86 mode.
APM Interface Disconnect | 0x04 |
CPU Idle | 0x05 | Requests system suspend.
0) Clock halted until timer tick interrupt.
1) Slow clock[1]
CPU Busy | 0x06 | Driver tells system APM to restore clock speed of the CPU.
Set Power State | 0x07 | Set system or device into Suspend/Standby/Off state.
Enable/Disable Power Management | 0x08 |
Restore APM BIOS Power-On Defaults | 0x09 |
Get Power Status | 0x0A | Supports AC status "On backup power". And battery status.
Get PM Event | 0x0B | Checks for APM events. Shall be called once per second.
Get Power State | 0x0C |
Enable/Disable Device Power Management | 0x0D |
APM Driver Version | 0x0E |
Engage/Disengage Power Management | 0x0F | APM management for a specific device.
Get Capabilities | 0x10 |
Get/Set/Disable Resume Timer | 0x11 |
Enable/Disable Resume on Ring Indicator | 0x12 |
Enable/Disable Timer Based Requests | 0x13 |
OEM APM Installation Check | 0x80 | Tells if APM BIOS supports OEM hardware dependent functions.
OEM APM Function | 0x80 | Access to OEM specific functions.

## Power states

The APM specification defines system power states and device power states.

### System power states

APM defines five power states for the computer system:

* Full On: The computer is powered on, and no devices are in a power saving mode.
* APM Enabled: The computer is powered on, and APM is controlling device power management as needed.
* APM Standby: Most devices are in their low-power state, the CPU is slowed or stopped, and the system state is saved. The computer can be returned to its former state quickly (in response to activity such as the user pressing a key on the keyboard).
* APM Suspend: Most devices are powered off, but the system state is saved. The computer can be returned to its former state, but takes a relatively long time. (Hibernation is a special form of the APM Suspend state).
* Off: The computer is turned off.

### Device power states

APM also defines power states that APM-aware hardware can implement. There is no requirement that an APM-aware device implement all states.

The four states are:

* Device On: The device is in full power mode.
* Device Power Managed: The device is still powered on, but some functions may not be available, or may have reduced performance.
* Device Low Power: The device is not working. Power is maintained so that the device may be 'woken up'.
* Device Off: The device is powered off.

## Hardware components

### CPU

The CPU core (defined in APM as the CPU clock, cache, system bus and system timers) is treated specially in APM, as it is the last device to be powered down, and the first device to be powered back up. The CPU core is always controlled through the APM BIOS (there is no option to control it through a driver). Drivers can use APM function calls to notify the BIOS about CPU usage, but it is up to the BIOS to act on this information; a driver cannot directly tell the CPU to go into a power saving state.

### ATA drives

The ATA specification and SATA specification defines APM provisions for hard drives, which specifies a trade-off between spin-down frequency and always-on performance. Unlike the BIOS-side APM, the ATA APM and SATA APM has never been deprecated.[4] An operating system may use ATA STANDBY and ATA IDLE commands to manage ATA APM features.

Aggressive spin-down frequencies may reduce drive lifespan by unnecessarily accumulating load cycles; most modern drives are specified to sustain 300,000 cycles and usually last at least 600,000. On the other hand, not spinning down the drive will cause extra power draw and heat generation; high temperatures also reduce the lifespan of hard drives.[5]

## See also

* Active State Power Management \- hardware power management protocol for PCI Express
* Green computing
* BatteryMAX

## References

1. ↑ 1.0 1.1 1.2 1.3 "Advanced Power Management (APM) BIOS Interface Specification Revision 1.2 February 1996 Intel/Microsoft". http://download.microsoft.com/download/1/6/1/161ba512-40e2-4cc9-843a-923143f3456c/APMV12.rtf. 090429
2. ↑ Intel Corporation, "NewsBit: Microsoft, Intel Develop Power Standard", Microcomputer Solutions, March/April 1992, page 1
3. ↑ "APM 2.0: BIOS independent power management under Windows NT 4.0 or 3.51". Phoenix Technologies. http://www.award.com:80/resources/apm-portables-ds.zip.
4. ↑ "linux - What do different values of hard drive's Advanced Power Management feature (hdparm -B) affect, except spin-down?". https://superuser.com/a/558622. "The ATA Spec turns up this tidbit: Subcommand code 05h allows the host to enable Advanced Power Management. To enable Advanced Power Management, the host writes the Sector Count register with the desired advanced power management level and then executes a SET FEATURES command with subcommand code 05h."
5. ↑ bwDraco. "linux - How much "Load_cycle_count" can my hard drive hypotethically sustain?". https://superuser.com/a/847431/.

## External links

Template:Firmware and booting

* v
* t
* e

Computer processor power management technologies

Standards|

* Advanced Configuration and Power Interface (ACPI)
* Advanced Power Management (APM)

Techniques|

* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Overclocking
* Underclocking

Implementations|

| Power Saving|

* AMD Cool'n'Quiet (desktop)
* AMD PowerNow! (laptop)
* Intel SpeedStep
* Transmeta LongRun
* VIA LongHaul

|

Performance|

* Intel Turbo Boost
* AMD Turbo Core

Graphics|

* AMD PowerPlay
* AMD PowerTune

* v
* t
* e

Processor technologies

Models|

* Turing machine
* Universal
* Post–Turing
* Quantum
* Belt machine
* Stack machine
* Finite-state machine
* with datapath
* Hierarchical
* Queue automaton
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load/store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* comparison
* addressing modes

|

* x86
* ARM
* MIPS
* Power ISA
* SPARC
* Itanium
* Unicore
* MicroBlaze
* RISC-V
* others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Tomasulo algorithm
* Reservation station
* Re-order buffer
* Register renaming

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* SWAR
* SIMT
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Coprocessor
* ASIC
* FPGA
* CPLD
* Multi-chip module (MCM)
* System in package (SiP)

| By application|

* Microprocessor
* Microcontroller
* Mobile
* Notebook
* Ultra-low-voltage
* ASIP

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Programmable (PSoC)
* Network on a chip (NoC)

Hardware
accelerators|

* AI accelerator
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor processing unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 2-bit
* 4-bit
* 8-bit
* 16-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Integrated memory controller (IMC)

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Program counter

Control unit|

* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)
* Race to sleep

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model

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