Chisel (programming language)

Short description: Open-source hardware description language (HDL)

Constructing Hardware in a Scala Embedded Language (Chisel)

Paradigms| Multi-paradigm: concurrent, functional, imperative, object-oriented
Family| Scala
Developer| University of California, Berkeley
First appeared| June 2012; 13 years ago (2012-06)
Stable release|

3.6.0 / April 14, 2023; 3 years ago (2023-04-14)

Typing discipline| Inferred, static, strong, structural
Scope| Lexical (static)
Implementation language| Scala
Platform| Java virtual machine (JVM)
JavaScript (Scala.js)
LLVM (Scala Native) (experimental)
Website| www.chisel-lang.org

The Constructing Hardware in a Scala Embedded Language (Chisel)[1] is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level.[2][3] Chisel is based on Scala as an embedded domain-specific language (DSL). Chisel inherits the object-oriented and functional programming aspects of Scala for describing digital hardware. Using Scala as a basis allows describing circuit generators. High quality, free access documentation exists in several languages.[4]

Circuits described in Chisel can be converted to a description in Verilog for synthesis and simulation.

## Contents

* 1 Code examples
* 2 Use
* 3 See also
* 4 References
* 5 External links

## Code examples

A simple example describing an adder circuit and showing the organization of components in Module with input and output ports:

class Add extends Module {
val io = IO(new Bundle {
val a = Input(UInt(8.W))
val b = Input(UInt(8.W))
val y = Output(UInt(8.W))

io.y := io.a + io.b

A 32-bit register with a reset value of 0:

val reg = RegInit(0.U(32.W))

A multiplexer is part of the Chisel library:

val result = Mux(sel, a, b)

## Use

Although Chisel is not yet a mainstream hardware description language, it has been explored by several companies and institutions. The most prominent use of Chisel is an implementation of the RISC-V instruction set, the open-source Rocket chip.[5] Chisel is mentioned by the Defense Advanced Research Projects Agency (DARPA) as a technology to improve the efficiency of electronic design, where smaller design teams do larger designs.[6] Google has used Chisel to develop a Tensor Processing Unit for edge computing.[7] Some developers prefer Chisel as it requires 5 times lesser code and is much faster to develop than Verilog.[8]

Circuits described in Chisel can be converted to a description in Verilog for synthesis and simulation using a program named FIRRTL.[9][better source needed]

## See also

* VHDL
* Verilog
* SystemC
* SystemVerilog

## References

1. ↑ Bachrach, J.; Vo, H.; Richards, B.; Lee, Y.; Waterman, A.; Avižienis, R.; Wawrzynek, J.; Asanović, K. (June 2012). "Chisel: constructing hardware in a Scala embedded language". San Francisco, California, USA: Association for Computing Machinery (ACM). pp. 1216–25. doi:10.1145/2228360.2228584. ISBN 978-1-4503-1199-1. https://dl.acm.org/doi/abs/10.1145/2228360.2228584.
2. ↑ "Chisel". California, U.S.: University of California, Berkeley. https://people.eecs.berkeley.edu/~jrb/Projects/chisel/chisel.htm.
3. ↑ Bachrach, Jonathan, ed. "Chisel: Accelerating Hardware Design". California, U.S.: RISC-V International. https://riscv.org/wp-content/uploads/2015/01/riscv-chisel-tutorial-bootcamp-jan2015.pdf.
4. ↑ Schoeberl, Martin (August 30, 2019) (in en, zh, ja, vi). Digital Design with Chisel (2nd ed.). Kindle Direct Publishing. ISBN 978-1689336031. http://www.imm.dtu.dk/~masca/chisel-book.html.
5. ↑ Asanović, Krste. "rocket-chip". RISC-V International. https://github.com/ucb-bar/rocket-chip.
6. ↑ Moore, Samuel K. (2018-07-16). "DARPA Plans a Major Remake of U.S. Electronics". IEEE Spectrum (Institute of Electrical and Electronics Engineers (IEEE)). https://spectrum.ieee.org/tech-talk/computing/hardware/darpas-planning-a-major-remake-of-us-electronics-pay-attention.
7. ↑ Derek Lockhart, Stephen Twigg, Ravi Narayanaswami, Jeremy Coriell, Uday Dasari, Richard Ho, Doug Hogberg, George Huang, Anand Kane, Chintan Kaur, Tao Liu, Adriana Maggiore, Kevin Townsend, Emre Tuncer (2018-11-16). Experiences Building Edge TPU with Chisel. Retrieved 2020-06-10.
8. ↑ "XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76 - CNX Software" (in en-US). 2021-07-05. https://www.cnx-software.com/2021/07/05/xiangshan-open-source-64-bit-risc-v-processor-rival-arm-cortex-a76/.
9. ↑ "Chisel/FIRRTL Hardware Compiler Framework". https://www.chisel-lang.org/.

## External links

* on GitHub

* v
* t
* e

Programmable logic

Concepts|

* ASIC
* SoC
* FPGA
* Logic block
* CPLD
* EPLD
* PLA
* PAL
* GAL
* PSoC
* Reconfigurable computing
* Xputer
* Soft microprocessor
* Circuit underutilization
* High-level synthesis
* Hardware acceleration

Languages|

* Verilog
* A
* AMS
* VHDL
* AMS
* VITAL
* SystemVerilog
* DPI
* SystemC
* AHDL
* Handel-C
* PSL
* UPF
* PALASM
* ABEL
* CUPL
* OpenVera
* C to HDL
* Flow to HDL
* MyHDL
* JHDL
* ELLA

Companies|

* Accellera
* Actel
* Achronix
* AMD
* Aldec
* Atmel
* Cadence
* Cypress
* Duolog
* Forte
* Intel
* Altera
* Lattice
* National
* Mentor Graphics
* Microsemi
* Signetics
* Synopsys
* Magma
* Virage Logic
* Texas Instruments
* Tabula
* Xilinx

Products|

| Hardware|

* iCE
* Stratix
* Virtex

|

Software|

* Intel Quartus Prime
* Xilinx ISE
* Xilinx Vivado
* ModelSim
* VTR
* Simulators

IP|

| Proprietary|

* ARC
* ARM Cortex-M
* LEON
* LatticeMico8
* MicroBlaze
* PicoBlaze
* Nios
* Nios II

|

Open-source|

* JOP
* LatticeMico32
* OpenCores
* OpenRISC
* 1200
* RISC-V
* Zet

0.00

(0 votes)

Original source: https://en.wikipedia.org/wiki/Chisel (programming language). Read more

|

Retrieved from "https://handwiki.org/wiki/index.php?title=Chisel_(programming_language)&oldid=313281"
*[v]: View this template
*[t]: Discuss this template
*[e]: Edit this template