Altos Design Automation

Altos Design AutomationType| Private

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Fate| Acquired (May 10, 2011)
Successor| Cadence Design Systems
Headquarters| San Jose, California, United States

Key people

| Jim McCanny, CEO and Co-founder

Ken Tseng, CTO and Co-founder

Kevin Chou, VP R&D and Co-founder

Wenkung Chu, R&D Architech and Co-founder
Website| www.altos-da.com

Altos Design Automation, Inc. was an electronic design automation software company. Altos developed and marketed cell and semiconductor intellectual property (IP) characterization tools that created library views for timing, signal integrity and power analysis and optimization.[1][2] The Altos tools were fully automated and the company claimed that its tools are extremely fast. The Altos tools were used by engineers employing both corner-based and statistical-based design implementation flows to reduce time-to -market and improve yield.[3][4]

Altos was founded in January 2005 in Santa Clara, California by former employees of Cadence Design Systems. All members of the team worked at CadMOS where they were responsible for the development of Signal Integrity analysis tools for both cell- and transistor-level digital IC designers. In May 2011 Altos was acquired by Cadence.[5]

## Contents

* 1 Products
* 2 Footnotes
* 3 References
* 4 External links

## Products

Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints, and pin capacitances. Variety generates statistical static timing analysis (SSTA) models for a number of commercial SSTA products from a single characterization run.

Liberate is an automated library characterization tool for standard cells and I/Os that serves existing static timing analyzers. Liberate takes in a Spice netlist and Spice subcircuits, and automatically generates a characterized cell library. It supports both Composite Current Source (CCS) model backed by Synopsys and the Effective Current Source Model (ECSM) backed by Cadence Design Systems.

## Footnotes

1. ↑ "Statistical timing gets modeling boost", EE Times, 2007-01-15.
2. ↑ "Characterization tool aids SSTA-library creation" , EDN, 2007-01-15.
3. ↑ "Statistical timing revs for 45-nm era", EE Times, 2006-07-03.
4. ↑ "Altos Targets Statistical Timing Models" , Electronic News, 2006-07-03.
5. ↑ Cadence Acquires Altos Design Automation

## References

* "Fireside Chat: Rick Lucier and Jim McCanny", EDACafe, 2008-01-28.
* "The 'Inconvenient Truth' of statistical design", SCDsource, 2007-12-05.
* "Where's the value in DFM? D or M?", Chip Design, 2007-03-01.
* "Altos closes $1.5M, signs Jim Hogan", EE Times, 2007-01-05.
* "Firms partner on standard statistical analysis library format", EE Times, 2006-07-25.
* "What's Hot at DAC?", EE Times, 2006-07-17.
* "Startup to 'Liberate' library characterization", EE Times, 2006-07-03.

## External links

* http://www.altos-da.com

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