Data processing unit

Short description: Programmable electronic component

SolidRun's SolidNet OCP-8K SmartNIC

A data processing unit (DPU) is a programmable computer processor that tightly integrates a general-purpose CPU with network interface hardware.[1] Sometimes they are called "IPUs" (for "infrastructure processing unit") or "SmartNICs".[2] They can be used in place of traditional NICs to relieve the main CPU of complex networking responsibilities and other "infrastructural" duties; although their features vary, they may be used to perform encryption/decryption, serve as a firewall, handle TCP/IP, process HTTP requests, or even function as a hypervisor or storage controller.[1][3] These devices can be attractive to cloud computing providers whose servers might otherwise spend a significant amount of CPU time on these tasks, cutting into the cycles they can provide to guests.[1]

AI factories are an emerging use case for DPUs. In these environments, massive amounts of data must be moved rapidly among CPUs, GPUs, and storage systems to handle complex AI workloads. By offloading tasks such as packet processing, encryption, and traffic management, DPUs help reduce latency and improve energy efficiency, enabling these AI factories to maintain the high throughput and scalability needed for advanced machine learning operations.[4]

Alongside their role in accelerating network and storage functions, DPUs are increasingly viewed as the “third pillar of computing,” complementing both CPUs and GPUs. Unlike traditional processors, a DPU typically resides on a network interface card, allowing data to be processed at the network’s line rate before it reaches the CPU. This approach offloads critical but lower-level system duties—such as security, load balancing, and data routing—from the central processor, thus freeing CPUs and GPUs to focus on application logic and AI-specific computations.[5]

## Contents

* 1 Examples of DPUs
* 1.1 Azure Boost DPU
* 1.1.1 Key Features
* 1.1.2 Industry Context
* 2 Impact on Cloud Computing
* 3 See also
* 4 References

## Examples of DPUs

### Azure Boost DPU

In 2024, Microsoft introduced the Azure Boost DPU, a custom-designed data processing unit aimed at optimizing network and infrastructure efficiency across its Azure cloud platform. This DPU offloads network-related tasks such as packet processing, security enforcement, and traffic management from central CPUs, enabling better performance for application workloads.[6][7]

#### Key Features

* Network Optimization: The Azure Boost DPU enhances network throughput and reduces latency by processing data packets and offloading these tasks from traditional CPUs.[8]
* Security Capabilities: It integrates advanced isolation techniques to secure multi-tenant environments, protecting sensitive workloads.[7]
* Hyperscale Adaptability: Designed for large-scale data centers, the DPU supports Azure’s hyperscale infrastructure, ensuring scalability for modern cloud applications.[6]

#### Industry Context

The Azure Boost DPU aligns with the trend of custom silicon development in hyperscale cloud environments. Similar to AWS’s Nitro System and NVIDIA’s BlueField DPUs, Microsoft’s DPU focuses on enhancing cloud efficiency while addressing rising energy and security demands.[7] This innovation positions Microsoft alongside other cloud leaders leveraging DPUs to optimize data center operations and provide cost-effective, high-performance solutions for customers.[8]

## Impact on Cloud Computing

The introduction of DPUs like Azure Boost reflects a broader shift in the cloud computing industry toward offloading specific functions from general-purpose processors to specialized hardware. Microsoft’s Azure Boost DPU represents its strategy to reduce costs, enhance security, and achieve sustainability goals while improving infrastructure efficiency.[6][7]

## See also

* Compute Express Link (CXL)

## References

1. ↑ 1.0 1.1 1.2 Davie, Bruce (November 24, 2021). "SmartNICs, IPUs, DPUs de-hyped: Why and how cloud giants are offloading work from server CPUs". The Register. https://www.theregister.com/AMP/2021/11/24/infrastructure_processing_units/.
2. ↑ Sharwood, Simon (May 23, 2023). "Google Cloud upgrades with next-gen accelerator that embiggens its VMs". The Register. https://www.theregister.com/2023/05/23/google_cloud_c3_ipu/. "…Infrastructure Processing Unit – the same kind of kit that others call SmartNICs or Data Processing Units…"
3. ↑ "Definition of SmartNIC". Ziff Davis. https://www.pcmag.com/encyclopedia/term/smartnic.
4. ↑ "DPUs, the New Heroes Powering AI Factories" (in en-US). 2025-01-29. https://techstrong.ai/articles/dpus-the-new-heroes-powering-ai-factories/.
5. ↑ "The Power and Meaning of the NVIDIA BlueField DPU for AI Factories" (in en-US). https://www.f5.com/company/blog/dpu-ai-factory.
6. ↑ 6.0 6.1 6.2 "Enhancing Infrastructure Efficiency with Azure Boost DPU". November 19, 2024. https://techcommunity.microsoft.com/blog/azureinfrastructureblog/enhancing-infrastructure-efficiency-with-azure-boost-dpu/4298901.
7. ↑ 7.0 7.1 7.2 7.3 "Microsoft debuts custom chips to boost data center security and power efficiency". November 19, 2024. https://venturebeat.com/data-infrastructure/microsoft-debuts-custom-chips-to-boost-data-center-security-and-power-efficiency/.
8. ↑ 8.0 8.1 "New in-house chips round out Microsoft's portfolio". November 19, 2024. https://techcrunch.com/2024/11/19/new-in-house-chips-round-out-microsofts-portfolio/.

* v
* t
* e

Hardware acceleration

Theory|

* Universal Turing machine
* Parallel computing
* Distributed computing

Applications|

* GPU
* GPGPU
* DirectX
* Audio
* Digital signal processing
* Hardware random number generation
* Artificial intelligence
* Cryptography
* TLS
* Machine vision
* Custom hardware attack
* scrypt
* Networking

Implementations|

* High-level synthesis
* C to HDL
* FPGA
* ASIC
* CPLD
* System on Chip
* Network on Chip

Architectures|

* Data flow
* Transport triggered
* Multicore
* Manycore
* Heterogeneous
* In-memory computing
* Systolic array
* Neuromorphic

Related|

* Programmable logic
* Processor
* design
* chronology
* Digital electronics
* Virtualization
* Hardware emulation
* Logic synthesis
* Embedded systems

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