Bus encoding

Bus encoding refers to converting/encoding a piece of data to another form before launching on the bus. While bus encoding can be used to serve various purposes like reducing the number of pins, compressing the data to be transmitted, reducing cross-talk between bit lines, etc., it is one of the popular techniques used in system design to reduce dynamic power consumed by the system bus.[1][2] Bus encoding aims to reduce the Hamming distance between 2 consecutive values on the bus. Since the activity is directly proportional to the Hamming distance, bus encoding proves to be effective in reducing the overall activity factor thereby reducing the dynamic power consumption in the system. In the context of this article, a system can refer to anything where data is transferred from one element to another over bus (viz. System on a Chip (SoC), a computer system, an embedded system on board, etc.).

## Contents

* 1 Motivation
* 2 Examples of bus encoding to achieve low power
* 3 Other examples of bus encoding
* 4 Implementation method
* 5 Properties of the encoding function
* 6 Trade-off / analysis
* 7 See also
* 8 References
* 9 Further reading

## Motivation

Power consumption in electronic systems is a matter of concern today for the below reasons:

1. Battery-operated devices: Due to ubiquity of battery operated devices and the need to maximize the duration between two subsequent charging of the battery, it is necessary that the system consumes as less power (and energy) as possible.
2. Environmental constraints: In an attempt to protect the environment, we need to conserve the usable energy. Since the energy consumed by electronic systems is increasing drastically, minimizing the energy consumption of electronic systems is critical to save the environment.
3. Power dissipation: As per the Moore's law, semiconductor devices have been packing more and more transistors in smaller amount of area. This leads to higher power dissipation per unit area and makes packaging and thermal cooling system design complex and costly. Hence, low power electronic systems are needed to tackle this issue.

The dynamic power dissipated by an electronic circuit is directly proportional to the activity factor and the load capacitance as seen by the output of the logic gate. In case of a bus, the load capacitance is usually high since bus needs to be connected to multiple modules and routed longer and the activity factor is also high. Due to higher value of load capacitance and activity factor, in a typical system, bus power consumption can contribute up to 50% of the total power consumption. Bus encoding aims to reduce this power by reducing the amount of activity (number of toggles) in the bus lines. While the kind of bus encoding to be used for a particular system can be best determined when the target application and environmental constraints about the system are known apriori, described below are some bus encoding techniques which can help reduce bus power for most systems.

Hence bus encoding is important for any electronic system design.[citation needed]

## Examples of bus encoding to achieve low power

Following are some of the implementations to use bus encoding for reducing dynamic power consumption in different scenarios:

1. Gray code addressing:[3] The address lines of a bus in most of the computing systems increase in consecutive numerical values due to spatial locality. If we use regular binary coding for the bus, we are not assured of minimal Hamming distance between 2 consecutive addresses. Using Gray codes for encoding the address lines will lead to a Hamming distance of 1 between any 2 consecutive address bus values (as long as spatial locality holds). There are variations to this scheme named Shifted Gray encoding to reduce the delay overhead.[4]
2. Sequential addressing or T0 codes:[5] In case of address bus, due to spatial locality that exists in programs, most of the transitions involve changing the address to the next consecutive value. A possible encoding scheme is to use an additional line, INC, in the bus indicating whether the current transition is the next increment address or not. If it is not a consecutive address, then the receiver can use the value on the bus. But if it is a consecutive address, the transmitter need not change the value in the bus, but just assert the INC line to 1. In such case, for a continuous addressing scheme, there is no transition at all on the bus, leading to a bus activity factor of 0.
3. Number representation: Consider an example of a system which gets one of its data from a sensor. Most of the times, the sensor may be measuring some noise and for this example, consider that the values being measured are (0) and (-1) alternatively. For a 32-bit data bus, value 0 translates to 0x00000000 (0000 0000 0000 0000 0000 0000 0000 0000) while (-1) translates to 0xFFFFFFFF (1111 1111 1111 1111 1111 1111 1111 1111) in a 2’s complement representation. We see that the Hamming distance in this case is 32 (since all 32-bits are changing their state). Instead, if we encode the bus to use signed integer representation (MSB is sign bit), we can represent 0 as 0x00000000 (0000 0000 0000 0000 0000 0000 0000 0000) and -1 as 0x80000001 (1000 0000 0000 0000 0000 0000 0000 0001) . In this case, we see that the Hamming distance between the numbers is just 2. Hence by using a 2’s complement to signed arithmetic encoding, we are able to reduce the activity from a factor of 32 to 2.
4. Inversion encoding:[6][7] This is another implementation of bus encoding where an additional line named INV is added to the bus lines. Depending on the value of the INV line, the other lines will be used with or without inversion. e.g. if INV line is 0, the data on the bus is sampled as it is but if INV line is 1, the data on the bus is inverted before any processing on it. Referring to the example used in 3, instead of using a signed integer representation, we could continue using 2’s complement and achieve the same activity reduction using inversion encoding. So, 0 will be represented as 0x00000000 with INV=0 and -1 will be represented as 0x00000000 with INV=1. Since INV=1, receiver will invert the data before consuming it, thereby converting it to 0xFFFFFFFF internally. In this case, only 1 bit (INV bit) is changed over bus leading to an activity of factor 1. In general, in inversion encoding, the encoder computes the Hamming distance between the current value and next value and based on that, determines whether to use INV=0 or INV=1.
5. Value cache encoding:[8] This is another form of Bus encoding, primarily used for external (off-chip) Busses. A dictionary (value cache) is maintained at both the sender and receiver end about some of the commonly shared data patterns. Instead of passing the data patterns each time, the sender just toggles one bit indicating which entry from value cache to be used at the receiver end. Only for values which are not present in the value cache, the complete data is sent over the bus. There has been various modified implementations of this technique with an intent to maximize the hits for the value cache, but the underlying idea is the same.[9][10]
6. Other techniques like sector-based encoding,[11] variations of inversion coding, have also been proposed. There has been work on using bus encodings which lower the leakage power consumption as well along with reducing the crosstalk with minimal impact on path delays.[12][13]

## Other examples of bus encoding

Many other types of bus encoding have been developed for a variety of reasons:

* improved EMC: differential signaling used in many buses, and the more general constant-weight code used in the MIPI C-PHY Camera Serial Interface[14] are both more immune to outside interference, and emit less interference to other devices.
* bus multiplexing: Many early microprocessors and many early DRAM chips reduced costs by using bus multiplexing, rather than dedicate a pin to every address bit and data bit of the system bus. One approach re-uses the address bus pins at different times for data bus pins,[15] an approach used by conventional PCI. Another approach re-uses the same pins at different times for the upper half and for the lower half of the address bus, an approach used by many dynamic random-access memory chips, adding 2 pins to the control bus -- a row-address strobe (RAS) and the column-address strobe (CAS).

## Implementation method

In case of SoC designs, bus encoding schemes can be best implemented in RTL by instantiating dedicated encoders and decoders over the bus. Another way it could be implemented is by passing hint to the synthesis tool either as a trace of the simulation[16] or by using synthesis pragma to define the type of encoding needed.

On board, a small low power IC can be deployed in between the master and slave modules on the bus to implement the encoding and decoding functions.

## Properties of the encoding function

The bus encoding/decoding function must be a bijection. This essentially requires encoding function to possess below behavior:[3]

1. Every data to be launched on the bus must have a unique encoded value and every encoded value must uniquely decode to the same original value.
2. It must be possible to encode and decode all the values which can be generated by the source.

## Trade-off / analysis

* While adding of bus encoding reduces the activity factor over the bus and leads to reduction in dynamic power, addition of encoders and decoders around the bus causes additional circuitry to be added to the design, which also consume certain amount of dynamic power. We must factor this while computing the power savings.
* The additional circuitry will also increase the leakage power of the design/circuit/system/SoC. If the base activity factor of the system bus is not very high, bus encoding may not be a very viable option since it will degrade overall energy consumption due to higher leakage power.
* If the bus timing is in the critical data path, adding of additional circuitry in the path will degrade the timing path and may prove detrimental. This analysis needs to be done carefully to determine what kind of bus encoding to use.

## See also

* Gray code addressing
* Power dissipation
* Low power electronics
* Glitch removal
* Green computing

## References

1. ↑ Low Power RT-Level Synthesis Techniques: A Tutorial, http://sportlab.usc.edu/~massoud/Papers/low-power-RTL-review-journal.pdf
2. ↑ "A Survey of Optimization Techniques targeting Low Power VLSI Circuits", DAC 32: 242–247, 1995
3. ↑ 3.0 3.1 Memory Bus Encoding for Low Power: A Tutorial, http://sportlab.usc.edu/~massoud/Papers/isqed-tut.pdf
4. ↑ "Shifted Gray encoding to reduce instruction memory address bus switching for low-power embedded systems". Journal of Systems Architecture 56 (4–6): 180–190. April–June 2010. doi:10.1016/j.sysarc.2010.03.003.
5. ↑ "Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems". Proceedings Seventh Great Lakes Symposium on VLSI: 77–82. March 1997.
6. ↑ "Bus-Invert Coding for Low-Power I/O". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3 (1): 49–58. March 1995. doi:10.1109/92.365453. 1063-8210/95$04.00.
7. ↑ "Error: no `|title=` specified when using {{Cite web}}". http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Fall07/PROJECT/JIANG/Low power 32-bit bus with inversion encoding.ppt.Error:+no+`|title=`+specified when+using+{{[[Template:Cite+web|Cite+web]]}}&rft.atitle=&rft_id=http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Fall07/PROJECT/JIANG/Low%20power%2032-bit%20bus%20with%20inversion%20encoding.ppt&rfr_id=info:sid/en.wikibooks.org:Engineering:Bus_encoding">
8. ↑ "FV encoding for low power data I/O". Islped 2001: 84–87. August 2001.
9. ↑ "Power protocol: reducing power dissipation on off-chip data buses". Micro. 2002.
10. ↑ "Hierarchical Value Cache Encoding for Off-Chip Data Bus". ISLPED. 2006.
11. ↑ "Transition Reduction in Memory Buses Using Sector-based Encoding Techniques". http://sportlab.usc.edu/~massoud/Papers/sector-based-encoding-journal.pdf.
12. ↑ "Leakage- and crosstalk-aware bus encoding for total power reduction". Proceedings of the 41st Design Automation Conference: 779–782. June 2004.
13. ↑ "A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systems". Proceedings of the 18th International Conference on VLSI Design: 751–756. January 2005.
14. ↑ "Demystifying MIPI C-PHY / DPHY Subsystem - Tradeoffs, Challenges, and Adoption" (mirror)
15. ↑ Don Lancaster. "TV Typewriter Cookbook". (TV Typewriter). Section "Bus Organization". p. 82.
16. ↑ "Power Optimization of Core-Based Systems by Address Bus Encoding". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6 (4). December 1998. http://si2.epfl.ch/~demichel/publications/archive/1998/VLSISvol4iss4Dec98pg554.pdf.

## Further reading

* ﻿Low Power Architecture Design and Compilation Techniques for High-Performance Processors﻿ (Report). Advanced Computer Architecture Laboratory. 1994. ACAL-TR-94-01. http://www.scarpaz.com/2100-papers/Power Estimation/su94-low power architecture and compilation.pdf.

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