Clock gating

Short description: Power management technique for synchronous digital circuits

For other uses, see Clock incident (disambiguation).

In computer architecture, clock gating is a popular power management technique used in many synchronous circuits for reducing dynamic power dissipation (a significant source of power dissipation in digital designs), by removing the clock signal when the circuit, or a subpart of it, is idle. Clock gating saves power by pruning part of the clock tree distribution, at the cost of adding more logic to a circuit.

Pruning the clock turns off portions of the circuitry so that the flip-flops in them do not switch state, as switching the state consumes power. When not switched, the switching power consumption is reduced. This technique is particularly effective in systems with significant idle time or predictable periods of inactivity within specific modules.[1]

## Contents

* 1 Essential details
* 2 Clock-gating techniques
* 2.1 Glitch-free clock gating
* 3 Other considerations
* 4 See also
* 5 References

## Essential details

Digital circuits consume power through multiple mechanisms, typically categorised into dynamic and static components. The equation can describe the average power dissipation in a CMOS circuit:

Pavg=Pdynamic+Pshort+Pleakage+Pstatic

* Pdynamic results from charging and discharging capacitive loads during logic transitions. It is proportional to the switching activity, capacitance, supply voltage squared, and clock frequency.
* Pshort arises during signal transitions, when both PMOS and NMOS transistors momentarily conduct simultaneously, creating a brief short-circuit current path between power and ground.
* Pleakage is due to subthreshold and gate leakage currents, which occur even when transistors are off. This component becomes increasingly relevant in deep submicron technologies.
* Pstatic includes the power consumed by always-on blocks, such as biasing circuits or reference generators, and is present even in standby conditions.

These components collectively define the total power profile of a digital system, and their optimisation is crucial for low-power design.[1]

These components become increasingly critical in modern integrated circuits, especially with technology scaling, where leakage and short-circuit power can constitute a significant portion of the total power budget.[1]

Clock gating is one of several techniques used to reduce the power consumption of digital circuits. It specifically targets the dynamic power component, Pdynamic, by lowering unnecessary switching activity in clock signals. The following equation can approximate the dynamic power:

Pdynamic=α⋅CL⋅Vdd2⋅f

Where:

* α is the switching activity factor,
* CL is the load capacitance,
* Vdd is the supply voltage,
* f is the clock frequency.

By turning off the clock signal to portions of the circuit when not in use, clock gating reduces α, thus decreasing overall dynamic power consumption. This differs from the power-gating technique, which cuts the power supply entirely and simultaneously reduces multiple sources of power dissipation.

## Clock-gating techniques

Clock-gating techniques typically operate by targeting specific clock regions. To apply these techniques, it is often necessary to modify the registers/(flip-flops) in the circuit so that they can be controlled and disconnected from the clock distribution network, effectively isolating blocks of combinational logic.

Illustration of the enabled flip-flops technique used to isolate an internal logic block. The clock is selectively enabled, allowing controlled activation of the logic while reducing unnecessary switching activity.

External circuits can control clock and activation signals through a technique known as Enabled Flip-Flops, or they can be generated internally using traditional clock-gating methods.

Timing diagram illustrating the gated clock (Gclock) behaviour in a clock gating circuit. When the control signal (CNTRL) is high, the clock is disabled and GCLK is held at a constant logic level (typically logic 0).

When the control signal (CNTRL) is set to 1, the clock-gating circuit turns off the clock by holding it at a fixed logic level, either 0 or 1. One typical implementation uses a CMOS pass-transistor controlled by the inverted control signal.

Clock-gating logic can be added to a design in a variety of ways:

1. It can be coded into the register-transfer level (RTL) code as enable conditions that can be automatically translated into clock-gating logic by synthesis tools (fine-grained clock gating).
2. It can be inserted into the design manually by the RTL designers (typically as module-level clock gating) by instantiating library-specific integrated clock gating (ICG) cells to gate the clocks of specific modules or registers.
3. It can be semi-automatically inserted into the RTL by automated clock-gating tools. These tools either insert ICG cells into the RTL or add enable conditions into the RTL code. These typically also offer sequential clock-gating optimisations.

### Glitch-free clock gating

In general, clock gating applied at a coarser granularity leads to reduced resource overhead and greater power savings.[2]

Any RTL modifications to improve clock gating will result in functional changes to the design (since the registers will now hold different values), which need to be verified.

## Other considerations

Sequential clock gating is the process of propagating enable conditions through upstream and downstream sequential elements, allowing additional registers to be clock-gated.[3] This technique extends clock gating beyond individual flip-flops to optimise power savings across larger circuit portions.

Chips designed for battery-powered or ultra-low-power applications—such as mobile phones, wearable devices, and embedded systems—typically simultaneously implement multiple clock gating strategies. Manual clock gating involves software drivers that enable or disable clocks to various idle controllers. In contrast, automatic clock gating uses hardware mechanisms to detect when a clock is unnecessary and dynamically turns it off. These approaches often operate together within the same enable tree. For example, an internal bus or bridge may employ automatic gating, keeping the clock disabled until accessed by the CPU or a DMA engine. In contrast, peripherals on that bus might be permanently gated off if unused in a particular board design.

Clock gating may also be used to reduce area. If many registers have the same enable, clock gating them at a higher point in the clock tree may cost only one integrated clock gate worth of area, but would save a 2:1 multiplexer (the "feedback mux" normally used to implement the enable) worth of area per register that has that enable.

## See also

* Power gating
* Glitch removal
* Dynamic frequency scaling
* Autonomous peripheral operation

## References

1. ↑ 1.0 1.1 Benini, Luca; DeMicheli, Giovanni (2012). Dynamic Power Management: Design Techniques and CAD Tools. Springer. ISBN 9781461554554. https://books.google.com/books?id=sDrSBwAAQBAJ&dq=DYNAMIC+POWER+MANAGEMENT+Design+Techniques+and+CAD+Tools&pg=PR13.
2. ↑ "Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators". Electronics 73: 73. 2021-01-05. doi:10.3390/electronics10010073.
3. ↑ Weste, Neil H. E.; Harris, David (1992). CMOS VLSI Design: A Circuits and Systems Perspective (2nd ed.). Addison-Wesley. ISBN 978-0-201-53376-7.

* v
* t
* e

Computer processor power management technologies

Standards|

* Advanced Configuration and Power Interface (ACPI)
* Advanced Power Management (APM)

Techniques|

* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Overclocking
* Underclocking

Implementations|

| Power Saving|

* AMD Cool'n'Quiet (desktop)
* AMD PowerNow! (laptop)
* Intel SpeedStep
* Transmeta LongRun
* VIA LongHaul

|

Performance|

* Intel Turbo Boost
* AMD Turbo Core

Graphics|

* AMD PowerPlay
* AMD PowerTune

* v
* t
* e

Processor technologies

Models|

* Turing machine
* Universal
* Post–Turing
* Quantum
* Belt machine
* Stack machine
* Finite-state machine
* with datapath
* Hierarchical
* Queue automaton
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load/store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* comparison
* addressing modes

|

* x86
* ARM
* MIPS
* Power ISA
* SPARC
* Itanium
* Unicore
* MicroBlaze
* RISC-V
* others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Tomasulo algorithm
* Reservation station
* Re-order buffer
* Register renaming

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* SWAR
* SIMT
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Coprocessor
* ASIC
* FPGA
* CPLD
* Multi-chip module (MCM)
* System in package (SiP)

| By application|

* Microprocessor
* Microcontroller
* Mobile
* Notebook
* Ultra-low-voltage
* ASIP

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Programmable (PSoC)
* Network on a chip (NoC)

Hardware
accelerators|

* AI accelerator
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor processing unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 2-bit
* 4-bit
* 8-bit
* 16-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Integrated memory controller (IMC)

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Program counter

Control unit|

* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)
* Race to sleep

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model

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