Goldmont

Short description: CPU microarchitecture used in Intel SoCs

GoldmontGeneral Info

Product code|

* 80668 (Apollo Lake)
* 80765 (Denverton)

Architecture and classification
Min. feature size| 14 nm
Instructions| x86-64, Intel 64
Extensions|

* MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
* AES-NI, RDRAND, CLMUL, SHA
* VT-x, VT-d

Physical specifications
Cores|

* 2–4

Products, models, variants
Brand name(s)|

* Atom
* Celeron
* Pentium

History
Predecessor| Airmont (die shrink)
Successor| Goldmont Plus (optimization)

Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. They allow only one thread per core.

The Apollo Lake platform with 14 nm Goldmont core was unveiled at the Intel Developer Forum (IDF) in Shenzhen, China, April 2016.[1] The Goldmont architecture borrows heavily from the Skylake Core processors, so it offers a more than 30 percent performance boost compared to the previous Braswell platform, and it can be used to implement power-efficient low-end devices including Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems.[2][3]

## Contents

* 1 Design
* 2 Technology
* 3 Erratum
* 4 List of Goldmont processors
* 4.1 Desktop processors (Apollo Lake)
* 4.2 Server processors (Denverton)
* 4.3 Mobile processors (Apollo Lake)
* 4.4 Embedded processors (Apollo Lake)
* 4.5 Automotive processors (Apollo Lake)
* 4.6 Tablet processors (Willow Trail)
* 5 See also
* 6 References

## Design

Goldmont is the 2nd generation out-of-order low-power Atom microarchitecture designed for the entry level desktop and notebook computers.[4] Goldmont is built on the 14 nm manufacturing process and supports up to four cores for the consumer devices. It includes the Intel Gen9 graphics architecture introduced with the Skylake.

The Goldmont microarchitecture builds on the success of the Silvermont microarchitecture, and provides the following enhancements:

* An out-of-order execution engine with a 3-wide superscalar pipeline.[5] Specifically:
* The decoder can decode 3 instructions per cycle.
* The microcode sequencer can send 3 µops per cycle for allocation into the reservation stations.
* Retirement supports a peak rate of 3 per cycle.
* Enhancement in branch prediction which de-couples the fetch pipeline from the instruction decoder.
* Larger out-of-order execution window and buffers that enable deeper out-of-order execution across integer, FP/SIMD, and memory instruction types.
* Fully out-of-order memory execution and disambiguation. The Goldmont microarchitecture can execute one load and one store per cycle (compared to one load or one store per cycle in the Silvermont microarchitecture). The memory execution pipeline also includes a second level TLB enhancement with 512 entries for 4KB pages.
* Integer execution cluster in the Goldmont microarchitecture provides three pipelines and can execute up to three simple integer ALU operations per cycle.
* SIMD integer and floating-point instructions execute in a 128-bit wide engine. Throughput and latency of many instructions have improved, including PSHUFB with 1-cycle throughput (versus 5 cycles for Silvermont microarchitecture) and many other SIMD instructions with doubled throughput.
* Throughput and latency of instructions for accelerating encryption/decryption (AES) and carry-less multiplication (PCLMULQDQ) have been improved significantly in the Goldmont microarchitecture.
* The Goldmont microarchitecture provides new instructions with hardware accelerated secure hashing algorithm, SHA1 and SHA256.
* The Goldmont microarchitecture also adds support for the RDSEED instruction for random number generation meeting the NIST SP800-90C standard.
* PAUSE instruction latency is optimized to enable better power efficiency.

## Technology

* A 14 nm manufacturing process
* System on chip architecture
* 3D tri-gate transistors
* Consumer chips up to quad-cores
* Supports SSE4.2 instruction set
* Supports Intel AESNI and PCLMUL instructions
* Supports Intel RDRAND and RDSEED instructions
* Supports Intel SHA extensions
* Supports Intel MPX (Memory Protection Extensions)
* Gen 9 Intel HD Graphics with DirectX 12, OpenGL 4.6 with latest Windows 10 driver update[6] (OpenGL 4.5 on Linux[7]), OpenGL ES 3.2 and OpenCL 2.0 support.
* HEVC Main10 & VP9 Profile0 hardware decoding support
* 10 W thermal design power (TDP) Desktop or Server processors
* 4.0 to 6.0 W TDP mobile processors
* eMMC 5.0 technology to connect to NAND flash storage
* USB 3.1 & USB-C specification
* Support for DDR3L, LPDDR3, and LPDDR4 memory
* Integrated Sensor Hub (ISH) which can sample and combine data from individual sensors and operate independently when the host platform is in a low power state
* Image Signal Processor (ISP) supporting four concurrent camera streams
* Audio controller supporting HD Audio and LPE Audio
* Trusted Execution Engine 3.0 security subsystem

## Erratum

Similar to the previous Silvermont generation, design flaws were found in processor circuitry, resulting in cease of operation when processors are actively used for several years. An Erratum named APL46 "System May Experience Inability to Boot or May Cease Operation"[8] was added to documentation in June 2017, stating that low pin count (LPC), real time clock (RTC), SD card and GPIO interfaces may stop functioning.

Mitigations[9] were found to limit impact on systems. A firmware update for the LPC bus called LPC_CLKRUN# reduces the utilization of the LPC interface, which in turn decreases (but does not eliminate) LPC bus degradation – some systems are however not compatible with this new firmware. It is recommended not to use SD cards as boot devices, and to remove the card from the system when not in use; other possible solutions being using only UHS-I cards and operating them at 1.8 V.

Congatec also states the issues impacts USB buses and eMMC, although those are not mentioned in Intel's public documentation. USB should have a maximum of 12% active time and there is a 60TB transmit traffic life expectancy over the lifetime of the port. eMMC should have a maximum of 33% active time and should be set to D3 device low power state by the operating system when not in use. Newer designs such as Atom C3000 Denverton do not seem to be affected.[10]

## List of Goldmont processors

### Desktop processors (Apollo Lake)

List of desktop processors as follows:[3][11]

Target
segment  | Cores
(threads = cores)  | Processor
branding & model  | GPU model  | TDP

(W)

| CPU freq.

(GHz)

| GPU freq.

(MHz)

| L2
cache | Release
date  | Price
(USD)

|
|
|
|
|
|
|
|
|

Brand name &
model number  | EU  | Base  | Turbo  | Base  | Turbo
Desktop  | 4 (4)  | Pentium  | J4205 | HD Graphics 505 | 18  | 10  | 1.5  | 2.6  | 250  | 800  | 2 MB  | Q3 2016  | $161
Celeron  | J3455 | HD Graphics 500 | 12  | 2.3  | 750  | $107
2 (2)  | J3355 | 2.0  | 2.5  | 700

### Server processors (Denverton)

Target
segment  | Cores

(threads)

| Processor
branding & model  | TDP

(W)

| CPU freq.

(GHz)

| L2
cache | DDR4 speed  | Release
date  | Price
(USD)

|
|
|
|
|
|
|
|

Base  | Turbo
Server  | 16 (16)  | Atom  | C3958[12][13] | 31  | 2.0  | 16 MB  | 2400  | Q3 2017  | $449
16 (16)  | C3955[12] | 32  | 2.1  | 2.4  | $434
12 (12)  | C3858[12] | 25  | 2.0  | 12 MB  | $332
12 (12)  | C3850[12] | 2.1  | 2.4  | $323
12 (12)  | C3830[12] | 21  | 1.9  | 2.3  | 2133  | $289
12 (12)  | C3808[12] | 25  | 2.0  | $369
8 (8)  | C3758[12] | 2.2  | 16 MB  | 2400  | $193
8 (8)  | C3750[12] | 21  | 2.2  | 2.4  | $171
8 (8)  | C3708[12] | 17  | 1.7  | 2133  | $209
4 (4)  | C3558[12] | 16  | 2.2  | 8 MB  | $86
4 (4)  | C3538[12] | 15  | 2.1  | $75
4 (4)  | C3508[12] | 11.25  | 1.6  | 1866  | $86
2 (2)  | C3338[12] | 9  | 1.5  | 2.2  | 4 MB  | Q1 2017  | $27
2 (2)  | C3308[12] | 9.5  | 1.6  | 2.1  | Q3 2017  | $32

### Mobile processors (Apollo Lake)

List of mobile processors as follows:[3][11]

Target
segment  | Cores
(Threads)  | Processor
branding & model  | GPU model  | TDP

(W)

| CPU freq.

(GHz)

| GPU freq.

(MHz)

| L2
cache | Release
date  | Price
(USD)

|
|
|
|
|
|
|
|
|

Brand name &
model number  | EU  | Base  | Turbo  | Base  | Turbo
Mobile  | 4 (4)  | Pentium  | N4200 | HD Graphics 505 | 18  | 6  | 1.1  | 2.5  | 200  | 750  | 2 MB  | Q3 2016  | $161
Celeron  | N3450 | HD Graphics 500 | 12  | 2.2  | 700  | $107
2 (2)  | N3350 | 2.4  | 650

### Embedded processors (Apollo Lake)

List of embedded processors as follows:

Target
segment  | Cores
(threads)  | Processor
branding & model  | GPU model  | TDP

(W)

| CPU freq.

(GHz)

| GPU freq.

(MHz)

| L2
cache | Release
date  | Price
(USD)

|
|
|
|
|
|
|
|
|

Brand name &
model number  | EU  | Base  | Turbo  | Base  | Turbo
Embedded  | 4 (4)  | Atom x7  | E3950 | HD Graphics 505 | 18  | 12  | 1.6  | 2.0  | 500  | 650  | 2 MB  | Q3 2016  | ?
Atom x5  | E3940 | HD Graphics 500 | 12  | 9.5  | 1.8  | 400  | 600
2 (2)  | E3930 | 6.5  | 1.3  | 550

### Automotive processors (Apollo Lake)

There is also an Atom A3900 series exclusively for automotive customers with AEC-Q100 qualification:[14]

Target
segment  | Cores
(threads)  | Processor
branding & model  | GPU model  | TDP

(W)

| CPU freq.

(GHz)

| GPU freq.

(MHz)

| L2
cache | Release
date  | Price
(USD)

|
|
|
|
|
|
|
|
|

Brand name &
model number  | EU  | Base  | Turbo  | Normal  | Turbo
Automotive  | 4 (4)  | Atom x7  | A3960  | HD Graphics 505 | 18  | 12.5  | 1.9  | 2.4  | 600  | 750  | 2 MB  | ?
A3950  | 9.5  | 1.6  | 2.0  | 500  | 650
Atom x5  | A3940  | HD Graphics 500 | 12  | 8  | 1.8  | 400  | 600
2 (2)  | A3930  | 6  | 1.3  | 550

### Tablet processors (Willow Trail)

Willow Trail platform was canceled. Apollo Lake will be offered instead.[15]

## See also

* List of Intel CPU microarchitectures
* List of Intel Pentium microprocessors
* List of Intel Celeron microprocessors
* List of Intel Atom microprocessors
* Atom (system on chip)

## References

1. ↑ Eric Brown (2016-04-18). ""Apollo Lake" Atoms to offer graphics-rich Goldmont cores". Hackerboards.com. http://hackerboards.com/apollo-lake-atoms-to-offer-graphics-rich-goldmont-cores/.
2. ↑ Anton Shilov (2016-04-15). "Intel Unveils New Low-Cost PC Platform: Apollo Lake with 14nm Goldmont Cores". Anandtech.com. http://www.anandtech.com/show/10256/intel-unveils-apollo-lake-14nm-goldmont.
3. ↑ 3.0 3.1 3.2 Alexander Fagot/ Allen Ngo (2016-06-07). "Intel claims Apollo Lake will be 30 percent faster than Braswell". Notebookcheck.net. http://www.notebookcheck.net/Intel-claims-Apollo-Lake-will-be-30-percent-faster-than-Braswell.167380.0.html.
4. ↑ Anton Shilov (2015-06-10). "Intel preps 'Apollo Lake' CPUs with 'Goldmont' cores, Gen9 graphics". http://www.kitguru.net/components/cpu/anton-shilov/intel-readies-apollo-lake-cpus-with-goldmont-architecture-gen9-graphics/.
5. ↑ Kanter, David. "Goldmont Takes Atom to 14nm". The Linley Group. http://www.linleygroup.com/newsletters/newsletter_detail.php?num=5665.
6. ↑ "Release Notes : DRIVER VERSION: 31.0.101.2115" (PDF). https://downloadmirror.intel.com/764512/ReleaseNotes_101.2115_WHQL.pdf.
7. ↑ "Mesa 13.0 Released With Intel OpenGL 4.5, RADV Radeon Vulkan Driver - Phoronix". http://www.phoronix.com/scan.php?page=article&item=mesa-13.
8. ↑ "Intel® Pentium® and Celeron® Processor N- and J- Series Specification Update". https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf.
9. ↑ "Errata sheet - congatec Apollo Lake designs". 2017-07-26. https://www.congatec.com/fileadmin/user_upload/Documents/Technical_Documents/APL_xA50_Errata_LPC_USB_SD_Card_eMMC_Hot_Plug.pdf.
10. ↑ "Intel® Atom® Processor C3000 Product Family Specification Update". https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/atom-c3000-family-spec-update.pdf.
11. ↑ 11.0 11.1 Gennadiy Shvets (2016-06-09). "Model numbers of Apollo Lake processors revealed". cpu-world.com. http://www.cpu-world.com/news_2016/2016060901_Model_numbers_of_Apollo_Lake_processors_revealed.html.
12. ↑ 12.00 12.01 12.02 12.03 12.04 12.05 12.06 12.07 12.08 12.09 12.10 12.11 12.12 12.13 Kennedy, Patrick (15 August 2017). "Intel Atom C3000 Series Launch SKUs and Differentiation". Serve the Home. https://www.servethehome.com/intel-atom-c3000-series-launch-skus-differentiation/.
13. ↑ Cutress, Ian (15 August 2017). "More Denverton Noise: Gigabyte's MA1-ST0 Features Unannounced 16-Core C3958". Anandtech. http://www.anandtech.com/show/11720/more-denverton-noise-gigabytes-ma10st0-features-unannounced-16core-c3958.
14. ↑ "Intel Atom® Processor E3900 and A3900 Series Datasheet Addendum". Intel. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-processor-e3900-a3900-series-datasheet-addendum.pdf?asset=14689.
15. ↑ Ryan Smith & Ian Cutress (2016-04-29). "Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Cancelled". Anandtech.com. http://www.anandtech.com/show/10288/intel-broxton-sofia-smartphone-socs-cancelled.

* v
* t
* e

Intel processors

Discontinued

BCD oriented (4-bit)|

* 4004 (1971)
* 4040 (1974)

pre-x86 (8-bit)|

* 8008 (1972)
* 8080 (1974)
* 8085 (1977)

Early x86 (16-bit)|

* 8086 (1978)
* 8088 (1979)
* 80186 (1982)
* 80188 (1982)
* 80286 (1982)

x87 (external FPUs)|

8/16-bit databus
8087 (1980)
16-bit databus
80187
80287
80387SX
32-bit databus
80387DX
80487

IA-32 (32-bit)|

* 80386
* SX
* 376
* EX
* 80486
* SX
* DX2
* DX4
* SL
* RapidCAD
* OverDrive
* A100/A110
* Celeron (1998)
* M
* D (2004)
* Pentium
* Original P5
* OverDrive
* Pro
* II
* II OverDrive
* III
* 4
* M
* Dual-Core
* some Core
* Solo
* Duo
* Tolapai

x86-64 (64-bit)|

* Celeron
* D
* Dual-Core
* Pentium
* 4
* D
* Extreme Edition
* Dual-Core
* some Core
* 2
* some i7

Other|

CISC
iAPX 432
Itanium
RISC
i860
i960
StrongARM
XScale

Current

IA-32 (32-bit)|

* Atom
* CE
* SoC
* Quark

x86-64 (64-bit)|

* Atom
* CE
* SoC
* Celeron
* Pentium
* Core
* i3
* i5
* i7
* i9
* M
* Xeon
* E3
* E5
* E7
* D
* Phi

Lists

* Celeron
* Pentium
* Pro
* II
* III
* 4
* D
* M
* Core
* Core
* 2
* i3
* i5
* i7
* i9
* M
* Atom
* Xeon
* Itanium

Related

* Tick–tock model
* Chipsets
* GPUs
* GMA
* HD and Iris Graphics
* PCHs
* SCHs
* ICHs
* PIIXs
* Stratix
* Codenames

Microarchitectures

x86|

| P5|

800 nm

600 nm
P54C
350 nm
P54CS
P55C
250 nm
Tillamook

|

P6, Pentium M,
Enhanced Pentium M|

500 nm

350 nm

Klamath
250 nm
Mendocino
Dixon
Tonga
Covington
Deschutes
Katmai
Drake
Tanner
180 nm
Coppermine
Coppermine T
Timna
Cascades
130 nm
Tualatin
Banias
90 nm
Dothan
Stealey
Tolapai
Canmore
65 nm
Yonah
Sossaman

NetBurst|

180 nm
Willamette
Foster
130 nm
Northwood
Gallatin
Prestonia
90 nm
Tejas and Jayhawk
Prescott
Smithfield
Nocona
Irwindale
Cranford
Potomac
Paxville
65 nm
Cedar Mill
Presler
Dempsey
Tulsa

Core|

65 nm
Merom-L
Merom
Conroe-L
Allendale
Conroe
Kentsfield
Woodcrest
Clovertown
Tigerton

45 nm
Penryn
Penryn-QC
Wolfdale
Yorkfield
Wolfdale-DP
Harpertown
Dunnington

Nehalem|

45 nm
Auburndale
Beckton (Nehalem-EX)
Bloomfield
Clarksfield
Gainestown (Nehalem-EP)
Havendale
Jasper Forest
Lynnfield

32 nm
Arrandale
Clarkdale
Gulftown (Westmere-EP)
Westmere-EX

Sandy Bridge|

32 nm
Sandy Bridge
Sandy Bridge-E
Gladden

22 nm
Ivy Bridge
Ivy Bridge-EP
Ivy Bridge-EX

Haswell|

22 nm
Haswell

14 nm
Broadwell

Skylake|

14 nm
Skylake
Kaby Lake (Amber Lake • Whiskey Lake)
Coffee Lake
Cascade Lake
Comet Lake

Palm Cove|

10 nm
Cannon Lake

Sunny Cove|

14 nm
Cooper Lake

10 nm
Ice Lake

Willow Cove|

14 nm
Rocket Lake

10 nm
Tiger Lake
Sapphire Rapids

Golden Cove|

7 nm
Alder Lake
Granite Rapids

Atom|

| Bonnell
Saltwell|

45 nm
Silverthorne
Diamondville
Pineview
Lincroft
Tunnel Creek
Stellarton
Sodaville
Groveland

32 nm
Cedarview
Penwell
Cloverview
Berryville
Centerton

|

Silvermont
Airmont|

22 nm
Valleyview
Tangier
Anniedale

14 nm
Cherryview

Goldmont|

14 nm
Goldmont
Goldmont Plus

Tremont|

10 nm
Tremont
Gracemont

* v
* t
* e

Intel CPU core roadmaps from P6 to Tiger Lake

| Atom (ULV) |  | Feature size |  | x86 |

|
|
|
|
|

Microarchi. | Step | Microarchi. | Step
| 600 nm | P6 | Pentium Pro
(133 MHz)
500 nm | Pentium Pro
(150 MHz)
350 nm | Pentium Pro
(166–200 MHz)
Klamath
250 nm | Deschutes
Katmai |  | NetBurst |
180 nm | Coppermine | Willamette
130 nm | Tualatin | Northwood
Banias |  | NetBurst(HT) |  | NetBurst(×2)
90 nm | Dothan | Prescott | ⇨ | Prescott‑2M | ⇨ | Smithfield
~~Tejas~~ | -> | ⇩ | -> | ~~Cedarmill (Tejas)~~
65 nm | Yonah | ~~Nehalem (NetBurst)~~ |  | Cedar Mill | ⇨ | Presler
Core | Merom | (x86-64) DDR2 \+ DDR3, 4 cores on mainstream desktop
Bonnell | Bonnell | 45 nm | Penryn |
Nehalem | Nehalem | HT reintroduced, integrated MC, PCH,
L3-cache introduced, 256KiB L2-cache/core, DDR3
Saltwell | 32 nm | Westmere | GPU on same package in 45nm, AES-NI introduced
Sandy Bridge | Sandy Bridge | on-die ring bus, GPU on die, no more non-UEFI motherboards, DDR3
Silvermont | Silvermont | 22 nm | Ivy Bridge |
Haswell | Haswell | FIVR, DDR3 \+ DDR3L
Airmont | 14 nm | Broadwell |
Skylake | Skylake | DDR3L \+ DDR4
Goldmont | Goldmont | Kaby Lake |
Coffee Lake | DDR4, 6 cores on mainstream desktop
Amber Lake |
Goldmont Plus | Whiskey Lake |
Coffee Lake Refresh | 8 cores on mainstream desktop
Comet Lake | 10 cores on mainstream desktop
Rocket Lake |
Tremont | Tremont | 10 nm | Cannon Lake |  | Hybrid
Sunny Cove | Ice Lake | 512KiB L2-cache/core | Lakefield
Gracemont | Willow Cove | Tiger Lake | Xe graphics engine |
Golden Cove | ? |  |

* ~~Strike-through~~ indicates cancelled processors
* Bold names are the microarchitecture names
* Italic names are future processors

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