List of ARM microarchitectures

Short description: Wikipedia list article

This is a list of microarchitectures based on the ARM family of instruction sets designed by ARM Holdings and 3rd parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.[1] Keil also provides a somewhat newer summary of vendors of ARM based processors.[2] ARM further provides a chart[3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

## Contents

* 1 ARM cores
* 1.1 Designed by ARM
* 1.2 Designed by third parties
* 2 ARM core timeline
* 3 See also
* 4 References
* 5 Further reading

## ARM cores

### Designed by ARM

ARM family  | ARM architecture  | ARM core  | Feature  | Cache (I / D), MMU | Typical MIPS @ MHz  | Reference

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ARM1  | ARMv1  | ARM1  | First implementation  | None  |  |
ARM2  | ARMv2  | ARM2  | ARMv2 added the MUL (multiply) instruction  | None  | 4 MIPS @ 8 MHz
0.33 DMIPS/MHz  |
ARMv2a  | ARM250  | Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructions  | None, MEMC1a  | 7 MIPS @ 12 MHz  |
ARM3  | ARMv2a  | ARM3  | First integrated memory cache  | 4 KB unified  | 12 MIPS @ 25 MHz
0.50 DMIPS/MHz  |
ARM6  | ARMv3  | ARM60  | ARMv3 first to support 32-bit memory address space (previously 26-bit).
ARMv3M first added long multiply instructions (32x32=64).  | None  | 10 MIPS @ 12 MHz  |
ARM600  | As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)  | 4 KB unified  | 28 MIPS @ 33 MHz  |
ARM610  | As ARM60, cache, no coprocessor bus  | 4 KB unified  | 17 MIPS @ 20 MHz
0.65 DMIPS/MHz  | [4]
ARM7 | ARMv3  | ARM700  |  | 8 KB unified  | 40 MHz  |
ARM710  | As ARM700, no coprocessor bus  | 8 KB unified  | 40 MHz  | [5]
ARM710a  | As ARM710  | 8 KB unified  | 40 MHz
0.68 DMIPS/MHz  |
ARM7T  | ARMv4T  | ARM7TDMI(-S)  | 3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressing | None  | 15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz  |
ARM710T  | As ARM7TDMI, cache  | 8 KB unified, MMU  | 36 MIPS @ 40 MHz  |
ARM720T  | As ARM7TDMI, cache  | 8 KB unified, MMU with FCSE (Fast Context Switch Extension)  | 60 MIPS @ 59.8 MHz  |
ARM740T  | As ARM7TDMI, cache  | MPU |  |
ARM7EJ  | ARMv5TEJ  | ARM7EJ-S  | 5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructions  | None  |  |
ARM8  | ARMv4  | ARM810  | 5-stage pipeline, static branch prediction, double-bandwidth memory  | 8 KB unified, MMU  | 84 MIPS @ 72 MHz
1.16 DMIPS/MHz  | [6][7]
ARM9T  | ARMv4T  | ARM9TDMI  | 5-stage pipeline, Thumb  | None  |  |
ARM920T  | As ARM9TDMI, cache  | 16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)  | 200 MIPS @ 180 MHz  | [8]
ARM922T  | As ARM9TDMI, caches  | 8 KB / 8 KB, MMU  |  |
ARM940T  | As ARM9TDMI, caches  | 4 KB / 4 KB, MPU  |  |
ARM9E  | ARMv5TE  | ARM946E-S  | Thumb, enhanced DSP instructions, caches  | Variable, tightly coupled memories, MPU  |  |
ARM966E-S  | Thumb, enhanced DSP instructions  | No cache, TCMs  |  |
ARM968E-S  | As ARM966E-S  | No cache, TCMs  |  |
ARMv5TEJ  | ARM926EJ-S  | Thumb, Jazelle DBX, enhanced DSP instructions  | Variable, TCMs, MMU  | 220 MIPS @ 200 MHz  |
ARMv5TE  | ARM996HS  | Clockless processor, as ARM966E-S  | No caches, TCMs, MPU  |  |
ARM10E  | ARMv5TE  | ARM1020E  | 6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)  | 32 KB / 32 KB, MMU  |  |
ARM1022E  | As ARM1020E  | 16 KB / 16 KB, MMU  |  |
ARMv5TEJ  | ARM1026EJ-S  | Thumb, Jazelle DBX, enhanced DSP instructions, (VFP)  | Variable, MMU or MPU  |  |
ARM11 | ARMv6  | ARM1136J(F)-S  | 8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory access | Variable, MMU  | 740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz  | [9]
ARMv6T2  | ARM1156T2(F)-S  | 9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructions  | Variable, MPU  |  | [10]
ARMv6Z  | ARM1176JZ(F)-S  | As ARM1136EJ(F)-S  | Variable, MMU + TrustZone  | 965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors  | [11]
ARMv6K  | ARM11MPCore  | As ARM1136EJ(F)-S, 1–4 core SMP  | Variable, MMU  |  |
SecurCore  | ARMv6-M  | SC000  | As Cortex-M0  |  | 0.9 DMIPS/MHz  |
ARMv4T  | SC100  | As ARM7TDMI  |  |  |
ARMv7-M  | SC300  | As Cortex-M3  |  | 1.25 DMIPS/MHz  |
Cortex-M | ARMv6-M  | Cortex-M0  | Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory  | Optional cache, no TCM, no MPU  | 0.84 DMIPS/MHz  | [13]
Cortex-M0+  | Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory  | Optional cache, no TCM, optional MPU with 8 regions  | 0.93 DMIPS/MHz  | [14]
Cortex-M1  | Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory  | Optional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU  | 136 DMIPS @ 170 MHz,[15] (0.8 DMIPS/MHz FPGA-dependent)[16] | [17]
ARMv7-M  | Cortex-M3 | Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory  | Optional cache, no TCM, optional MPU with 8 regions  | 1.25 DMIPS/MHz  | [18]
ARMv7E-M  | Cortex-M4  | Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory  | Optional cache, no TCM, optional MPU with 8 regions  | 1.25 DMIPS/MHz (1.27 w/FPU)  | [19]
Cortex-M7  | Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions  | 0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions  | 2.14 DMIPS/MHz  | [20]
ARMv8-M Baseline  | Cortex-M23  | Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZone  | Optional cache, no TCM, optional MPU with 16 regions  | 0.99 DMIPS/MHz  | [21]
ARMv8-M Mainline  | Cortex-M33  | Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor  | Optional cache, no TCM, optional MPU with 16 regions  | 1.50 DMIPS/MHz  | [22]
Cortex-M35P  | Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor  | Built-in cache (with option 2–16 KB), I-cache, no TCM, optional MPU with 16 regions  | 1.50 DMIPS/MHz  | [23]
ARMv8.1-M Mainline  | Cortex-M55  |  |  |  | [24]
Cortex-R | ARMv7-R  | Cortex-R4  | Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic  | 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 8/12 regions  | 1.67 DMIPS/MHz[25] | [26]
Cortex-R5  | Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)[27] | 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 12/16 regions  | 1.67 DMIPS/MHz[25] | [28]
Cortex-R7  | Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP[27] | 0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt. MPU with 16 regions  | 2.50 DMIPS/MHz[25] | [29]
Cortex-R8  | TBD  | 0–64 KB / 0–64 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24 regions  | 2.50 DMIPS/MHz[25] | [30]
ARMv8-R  | Cortex-R52  | TBD  | 0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions  | 2.16 DMIPS/MHz[31] | [32]
Cortex-R82  | TBD  | 16–128 KB /16–64 KB L1, 64K–1MB L2, 0.16–1 / 0.16–1 MB TCM,

opt MPU with 32+32 regions

| 3.41 DMIPS/MHz[33] | [34]
Cortex-A
(32-bit) | ARMv7-A  | Cortex-A5  | Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)  | 4−64 KB / 4−64 KB L1, MMU + TrustZone  | 1.57 DMIPS/MHz per core  | [35]
Cortex-A7  | Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design[36] | 8−64 KB / 8−64 KB L1, 0–1 MB L2, MMU + TrustZone  | 1.9 DMIPS/MHz per core  | [37]
Cortex-A8  | Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline  | 16–32 KB / 16–32 KB L1, 0–1 MB L2 opt. ECC, MMU + TrustZone  | Up to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)  | [38]
Cortex-A9  | Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)  | 16–64 KB / 16–64 KB L1, 0–8 MB L2 opt. parity, MMU + TrustZone  | 2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual-core)  | [39]
Cortex-A12  | Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)  | 32−64 KB  | 3.0 DMIPS/MHz per core  | [40]
Cortex-A15  | Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[36] | 32 KB w/parity / 32 KB w/ECC L1, 0–4 MB L2, L2 has ECC, MMU + TrustZone  | At least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation)[41] | [42]
Cortex-A17  | Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP  | 32 KB L1, 256 KB–8 MB L2 w/optional ECC  | 2.8 DMIPS/MHz  | [43]
ARMv8-A  | Cortex-A32  | Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline  | 8–64 KB w/optional parity / 8−64 KB w/optional ECC L1 per core, 128 KB–1 MB L2 w/optional ECC shared  |  | [44]
Cortex-A
(64-bit) | ARMv8-A  | Cortex-A34  | Application profile, AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline  | 8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses  |  | [45]
Cortex-A35  | Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline  | 8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses  | 1.78 DMIPS/MHz  | [46]
Cortex-A53 | Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline  | 8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–2 MB L2 shared, 40-bit physical addresses  | 2.3 DMIPS/MHz  | [47]
Cortex-A57 | Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline  | 48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses  | 4.1–4.5 DMIPS/MHz[48][49] | [50]
Cortex-A72 | Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width superscalar, deeply out-of-order pipeline  | 48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses  | 4.7 DMIPS/MHz  | [51]
Cortex-A73 | Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width superscalar, deeply out-of-order pipeline  | 64 KB / 32−64 KB L1 per core, 256 KB–8 MB L2 shared w/ optional ECC, 44-bit physical addresses  | 4.8 DMIPS/MHz[52] | [53]
ARMv8.2-A  | Cortex-A55 | Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline[54] | 16−64 KB / 16−64 KB L1, 256 KB L2 per core, 4 MB L3 shared  |  | [55]
Cortex-A65  | Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, out-of-order pipeline, SMT |  |  | [56]
Cortex-A65AE  | As ARM Cortex-A65, adds dual core lockstep for safety applications  | 64 / 64 KB L1, 256 KB L2 per core, 4 MB L3 shared  |  | [57]
Cortex-A75 | Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline[58] | 64 / 64 KB L1, 512 KB L2 per core, 4 MB L3 shared  |  | [59]
Cortex-A76 | Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way issue, 13 stage pipeline, deeply out-of-order pipeline[60] | 64 / 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared  |  | [61]
Cortex-A76AE  | As ARM Cortex-A76, adds dual core lockstep for safety applications  |  |  | [62]
Cortex-A77 | Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 6-width instruction fetch, 12-way issue, 13 stage pipeline, deeply out-of-order pipeline[60] | 1.5K L0 MOPs cache, 64 / 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared  |  | [63]
Cortex-A78 |  |  |  | [64]
Cortex-A78AE  | As ARM Cortex-A78, adds dual core lockstep for safety applications  |  |  | [65]
Cortex-X1 | Performance-tuned variant of Cortex-A78  |  |  |
Cortex-A78C  |  |  |  | [66]
ARMv9-A  | Cortex-A710 | First Armv9 generation “big” CPU[67] |  |  | [67]
Neoverse  |  | Neoverse N1  | Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way dispatch/issue, 13 stage pipeline, deeply out-of-order pipeline[60] | 64 / 64 KB L1, 512−1024 KB L2 per core, 2−128 MB L3 shared, 128 MB system level cache  |  | [68]
Neoverse E1  | Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, 10 stage pipeline, out-of-order pipeline, SMT | 32−64 KB / 32−64 KB L1, 256 KB L2 per core, 4 MB L3 shared  |  | [69]
ARM family  | ARM architecture  | ARM core  | Feature  | Cache (I / D), MMU | Typical MIPS @ MHz  | Reference

### Designed by third parties

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

Core Family  | Instruction set  | Microarchitecture | Feature  | Cache (I / D), MMU | Typical MIPS @ MHz

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StrongARM
(Digital)  | ARMv4  | SA-110  | 5-stage pipeline  | 16 KB / 16 KB, MMU  | 100–233 MHz
1.0 DMIPS/MHz
SA-1100  | derivative of the SA-110  | 16 KB / 8 KB, MMU  |
Faraday[70]
(Faraday Technology)  | ARMv4 | FA510 | 6-stage pipeline | Up to 32 KB / 32 KB cache, MPU | 1.26 DMIPS/MHz
100–200 MHz
FA526 | Up to 32 KB / 32 KB cache, MMU | 1.26 MIPS/MHz
166–300 MHz
FA626 | 8-stage pipeline | 32 KB / 32 KB cache, MMU | 1.35 DMIPS/MHz
500 MHz
ARMv5TE | FA606TE | 5-stage pipeline | No cache, no MMU | 1.22 DMIPS/MHz
200 MHz
FA626TE | 8-stage pipeline | 32 KB / 32 KB cache, MMU | 1.43 MIPS/MHz
800 MHz
FMP626TE | 8-stage pipeline, SMP | 1.43 MIPS/MHz
500 MHz
FA726TE | 13 stage pipeline, dual issue | 2.4 DMIPS/MHz
1000 MHz
XScale
(Intel / Marvell)  | ARMv5TE  | XScale  | 7-stage pipeline, Thumb, enhanced DSP instructions  | 32 KB / 32 KB, MMU  | 133–400 MHz
Bulverde  | Wireless MMX, wireless SpeedStep added  | 32 KB / 32 KB, MMU  | 312–624 MHz
Monahans[71] | Wireless MMX2 added  | 32 KB / 32 KB L1, optional L2 cache up to 512 KB, MMU  | Up to 1.25 GHz
Sheeva
(Marvell)  | ARMv5 | Feroceon | 5–8 stage pipeline, single-issue | 16 KB / 16 KB, MMU | 600–2000 MHz
Jolteon | 5–8 stage pipeline, dual-issue | 32 KB / 32 KB, MMU
PJ1 (Mohawk) | 5–8 stage pipeline, single-issue, Wireless MMX2 | 32 KB / 32 KB, MMU | 1.46 DMIPS/MHz
1.06 GHz
ARMv6 / ARMv7-A | PJ4 | 6–9 stage pipeline, dual-issue, Wireless MMX2, SMP | 32 KB / 32 KB, MMU | 2.41 DMIPS/MHz
1.6 GHz
Snapdragon
(Qualcomm)  | ARMv7-A  | Scorpion[72] | 1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)  | 256 KB L2 per core  | 2.1 DMIPS/MHz per core
Krait[72] | 1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)  | 4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core  | 3.3 DMIPS/MHz per core
ARMv8-A  | Kryo[73] | 4 cores. | ? | Up to 2.2 GHz

(6.3 DMIPS/MHz)

(Apple)  | ARMv7-A  | Swift[74] | 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON  | L1: 32 KB / 32 KB, L2: 1 MB shared  | 3.5 DMIPS/MHz per core
ARMv8-A | Cyclone[75] | 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64. Out-of-order, superscalar. | L1: 64 KB / 64 KB, L2: 1 MB shared
SLC: 4 MB | 1.3 or 1.4 GHz
ARMv8-A | Typhoon[75][76] | 2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64 | L1: 64 KB / 64 KB, L2: 1 MB or 2 MB shared
SLC: 4 MB | 1.4 or 1.5 GHz
ARMv8-A | Twister[77] | 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64 | L1: 64 KB / 64 KB, L2: 2 MB shared
SLC: 4 MB or 0 MB | 1.85 or 2.26 GHz
ARMv8-A | Hurricane and Zephyr[78] | Hurricane: 2 or 3 cores. AArch64, out-of-order, superscalar, 6-decode, 6-issue, 9-wide
Zephyr: 2 or 3 cores. AArch64, out-of-order, superscalar. | L1: 64 KB / 64 KB, L2: 3 MB or 8 MB shared
L1: 32 KB / 32 KB. L2: none
SLC: 4 MB or 0 MB | 2.34 or 2.38 GHz
1.05 GHz
ARMv8.2-A | Monsoon and Mistral[79] | Monsoon: 2 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Mistral: 4 cores. AArch64, out-of-order, superscalar. Based on Swift. | L1I: 128 KB, L1D: 64 KB, L2: 8 MB shared
L1: 32 KB / 32 KB, L2: 1 MB shared
SLC: 4 MB | 2.39 GHz
1.70 GHz
ARMv8.3-A | Vortex and Tempest[80] | Vortex: 2 or 4 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Tempest: 4 cores. AArch64, out-of-order, superscalar, 3-decode. Based on Swift. | L1: 128 KB / 128 KB, L2: 8 MB shared
L1: 32 KB / 32 KB, L2: 2 MB shared
SLC: 8 MB | 2.49 GHz
1.59 GHz
ARMv8.4-A | Lightning and Thunder[81] | Lightning: 2 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Thunder: 4 cores. AArch64, out-of-order, superscalar. | L1: 128 KB / 128 KB, L2: 8 MB shared
L1: 32 KB / 48 KB, L2: 4 MB shared
SLC: 16 MB | 2.66 GHz
1.73 GHz
ARMv8.4-A | Firestorm and Icestorm[82] | Firestorm: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Icestorm: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 7-wide. | L1: 192 KB / 128 KB, L2: 8 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 16 MB | 2.99 GHz
1.82 GHz
X-Gene
(Applied Micro)  | ARMv8-A | X-Gene | 64-bit, quad issue, SMP, 64 cores[83] | Cache, MMU, virtualization | 3 GHz (4.2 DMIPS/MHz per core)
Denver
(Nvidia)  | ARMv8-A | Denver[84][85] | 2 cores. AArch64, 7-wide superscalar, in-order, dynamic code optimization, 128 MB optimization cache,
Denver1: 28nm, Denver2:16nm | 128 KB I-cache / 64 KB D-cache | Up to 2.5 GHz
Carmel
(Nvidia)  | ARMv8.2-A | Carmel[86][87] | 2 cores. AArch64, 10-wide superscalar, in-order, dynamic code optimization, ? MB optimization cache,
functional safety, dual execution, parity & ECC | ? KB I-cache / ? KB D-cache | Up to ? GHz
ThunderX
(Cavium)  | ARMv8-A | ThunderX | 64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips) | ? | Up to 2.2 GHz
K12
(AMD)  | ARMv8-A | K12[88] | ? | ? | ?
Exynos
(Samsung)  | ARMv8-A | M1/M2 ("Mongoose")[89] | 4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order | 64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB | 5.1 DMIPS/MHz

(2.6 GHz)

ARMv8-A  | M3 ("Meerkat")[90] | 4 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order | 64 KB I-cache / 32 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared 4 MB | ?
ARMv8.2-A  | M4 ("Cheetah")[91] | 2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order  | 64 KB I-cache / 32 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared 4 MB  | ?

## ARM core timeline

The following table lists each core by the year it was announced.[92][93]

Year  | Classic cores  | Cortex cores  | Neoverse cores

|
|
|

ARM1-6 | ARM7 | ARM8 | ARM9 | ARM10 | ARM11 | Microcontroller | Real-time | Application
(32-bit) | Application
(64-bit) | Application
(64-bit)
1985  | ARM1 |  |  |  |  |  |  |  |  |  |
1986  | ARM2 |  |  |  |  |  |  |  |  |  |
1989  | ARM3 |  |  |  |  |  |  |  |  |  |
1992  | ARM250 |  |  |  |  |  |  |  |  |  |
1993  | ARM60
ARM610 | ARM700 |  |  |  |  |  |  |  |  |
1994  |  | ARM710
ARM7DI
ARM7TDMI |  |  |  |  |  |  |  |  |
1995  |  | ARM710a |  |  |  |  |  |  |  |  |
1996  |  |  | ARM810 |  |  |  |  |  |  |  |
1997  |  | ARM710T
ARM720T
ARM740T |  |  |  |  |  |  |  |  |
1998  |  |  |  | ARM9TDMI
ARM940T |  |  |  |  |  |  |
1999  |  |  |  | ARM9E-S
ARM966E-S |  |  |  |  |  |  |
2000  |  |  |  | ARM920T
ARM922T
ARM946E-S | ARM1020T |  |  |  |  |  |
2001  |  | ARM7TDMI-S
ARM7EJ-S |  | ARM9EJ-S
ARM926EJ-S | ARM1020E
ARM1022E |  |  |  |  |  |
2002  |  |  |  |  | ARM1026EJ-S | ARM1136J(F)-S |  |  |  |  |
2003  |  |  |  | ARM968E-S |  | ARM1156T2(F)-S
ARM1176JZ(F)-S |  |  |  |  |
2004  |  |  |  |  |  |  | Cortex-M3 |  |  |  |
2005  |  |  |  |  |  | ARM11MPCore |  |  | Cortex-A8 |  |
2006  |  |  |  | ARM996HS |  |  |  |  |  |  |
2007  |  |  |  |  |  |  | Cortex-M1 |  | Cortex-A9 |  |
2008  |  |  |  |  |  |  |  |  |  |  |
2009  |  |  |  |  |  |  | Cortex-M0 |  | Cortex-A5 |  |
2010  |  |  |  |  |  |  | Cortex-M4(F) |  | Cortex-A15 |  |
2011  |  |  |  |  |  |  |  | Cortex-R4
Cortex-R5
Cortex-R7 | Cortex-A7 |  |
2012  |  |  |  |  |  |  | Cortex-M0+ |  |  | Cortex-A53
Cortex-A57 |
2013  |  |  |  |  |  |  |  |  | Cortex-A12 |  |
2014  |  |  |  |  |  |  | Cortex-M7(F) |  | Cortex-A17 |  |
2015  |  |  |  |  |  |  |  |  |  | Cortex-A35
Cortex-A72 |
2016  |  |  |  |  |  |  | Cortex-M23
Cortex-M33(F) | Cortex-R8
Cortex-R52 | Cortex-A32 | Cortex-A73 |
2017  |  |  |  |  |  |  |  |  |  | Cortex-A55
Cortex-A75 |
2018  |  |  |  |  |  |  | Cortex-M35P(F) |  |  | Cortex-A65AE
Cortex-A76
Cortex-A76AE |
2019  |  |  |  |  |  |  |  |  |  | Cortex-A77 | Neoverse E1
Neoverse N1
2020  |  |  |  |  |  |  | Cortex-M55(F) | Cortex-R82  |  | Cortex-A78
Cortex-X1[94] | Neoverse V1[95]
2021  |  |  |  |  |  |  |  |  |  | Cortex-A510
Cortex-A710
Cortex-X2 | Neoverse N2

## See also

* Comparison of ARMv7-A cores
* Comparison of ARMv8-A cores
* List of applications of ARM cores
* ARM architecture

## References

1. ↑ "ARM Powered Standard Products". 2005. http://infocenter.arm.com/help/topic/com.arm.doc.faqs/attached/6745/0141_5linecard.pdf.
2. ↑ ARM Ltd and ARM Germany GmbH. "Device Database". Keil. http://www.keil.com/dd/parms/arm.htm.
3. ↑ "Processors". ARM. 2011. http://www.arm.com/products/processors/.
4. ↑ "ARM610 Datasheet". August 1993. http://bitsavers.org/pdf/acorn/ARM_DDI_0004D_ARM610_Data_Sheet_Aug93.pdf.
5. ↑ "ARM710 Datasheet". July 1994. http://bitsavers.org/pdf/acorn/ARM_DDI_0024C_ARM710_Data_Sheet_Jul94.pdf.
6. ↑ ARM Holdings (7 August 1996). "ARM810 – Dancing to the Beat of a Different Drum". Hot Chips. https://www.hotchips.org/wp-content/uploads/hc_archives/hc08/2_Mon/HC8.S4/HC8.4.1.pdf.
7. ↑ "VLSI Technology Now Shipping ARM810". EE Times. 26 August 1996. http://www.eetimes.com/document.asp?doc_id=1208831.
8. ↑ Register 13, FCSE PID register ARM920T Technical Reference Manual
9. ↑ "ARM1136J(F)-S – ARM Processor". Arm.com. http://www.arm.com/products/CPUs/ARM1136JF-S.html.
10. ↑ "ARM1156 Processor". https://www.arm.com/products/processors/classic/arm11/arm1156.php.
11. ↑ "ARM11 Processor Family". ARM. http://www.arm.com/products/processors/classic/arm11/.
12. ↑ 12.0 12.1 12.2 "Cortex-M0/M0+/M1 Instruction set; ARM Holding.". http://archive.electronicdesign.com/files/29/20719/fig_01.gif.
13. ↑ "Cortex-M0". https://developer.arm.com/ip-products/processors/cortex-m/cortex-m0.
14. ↑ "Cortex-M0+". https://developer.arm.com/ip-products/processors/cortex-m/cortex-m0-plus.
15. ↑ "ARM Extends Cortex Family with First Processor Optimized for FPGA" (Press release). ARM Holdings. 19 March 2007. Archived from the original on 5 May 2007. Retrieved 11 April 2007.
16. ↑ "ARM Cortex-M1". ARM product website. http://www.arm.com/products/CPUs/ARM_Cortex-M1.html.
17. ↑ "Cortex-M1". https://developer.arm.com/ip-products/processors/cortex-m/cortex-m1.
18. ↑ "Cortex-M3". https://developer.arm.com/ip-products/processors/cortex-m/cortex-m3.
19. ↑ "Cortex-M4". https://developer.arm.com/ip-products/processors/cortex-m/cortex-m4.
20. ↑ "Cortex-M7". https://developer.arm.com/ip-products/processors/cortex-m/cortex-m7.
21. ↑ "Cortex-M23". https://developer.arm.com/ip-products/processors/cortex-m/cortex-m23.
22. ↑ "Cortex-M33". https://developer.arm.com/ip-products/processors/cortex-m/cortex-m33.
23. ↑ "Cortex-M35P". https://developer.arm.com/ip-products/processors/cortex-m/cortex-m35p.
24. ↑ "Cortex-M55". https://developer.arm.com/ip-products/processors/cortex-m/cortex-m55.
25. ↑ 25.0 25.1 25.2 25.3 "Cortex-R – Arm Developer" (in en). Arm Ltd.. https://developer.arm.com/products/processors/cortex-r.
26. ↑ "Cortex-R4". https://developer.arm.com/ip-products/processors/cortex-r/cortex-r4.
27. ↑ 27.0 27.1 "Cortex-R5 & Cortex-R7 Press Release; ARM Holdings; 31 January 2011.". http://arm.com/products/arm-expands-unmatched-real-time-cortex-processor-portfolio.php.
28. ↑ "Cortex-R5". https://developer.arm.com/ip-products/processors/cortex-r/cortex-r5.
29. ↑ "Cortex-R7". https://developer.arm.com/ip-products/processors/cortex-r/cortex-r7.
30. ↑ "Cortex-R8". https://developer.arm.com/ip-products/processors/cortex-r/cortex-r8.
31. ↑ "Cortex-R". https://developer.arm.com/products/processors/cortex-r.
32. ↑ "Cortex-R52". https://developer.arm.com/products/processors/cortex-r/cortex-r52.
33. ↑ "Cortex-R82" (in en). https://developer.arm.com/ip-products/processors/cortex-r/cortex-r82.
34. ↑ "Arm Cortex-R comparison Table_v2". 2020. https://developer.arm.com/-/media/Arm Developer Community/PDF/Cortex-A R M datasheets/Arm Cortex-R Comparison Table_v2.pdf.
35. ↑ "Cortex-A5". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a5.
36. ↑ 36.0 36.1 "Deep inside ARM's new Intel killer". The Register. 20 October 2011. https://www.theregister.co.uk/2011/10/20/details_on_big_little_processing/.
37. ↑ "Cortex-A7". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a7.
38. ↑ "Cortex-A8". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a8.
39. ↑ "Cortex-A9". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a9.
40. ↑ "Cortex-A12 Summary; ARM Holdings.". http://www.arm.com/products/processors/cortex-a/cortex-a12-processor.php.
41. ↑ "Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 | ITProPortal.com". http://www.itproportal.com/2011/03/14/exclusive-arm-cortex-a15-40-cent-faster-cortex-a9/.
42. ↑ "Cortex-A15". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a15.
43. ↑ "Cortex-A17". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a17.
44. ↑ "Cortex-A32". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a32.
45. ↑ "Cortex-A34". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a34.
46. ↑ "Cortex-A35". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a35.
47. ↑ "Cortex-A53". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a53.
48. ↑ "Cortex-Ax vs performance". http://www.bitkistl.com/2015/03/cortex-ax-vs-performnace.html.
49. ↑ "Relative Performance of ARM Cortex-A 32-bit and 64-bit Cores". http://www.cnx-software.com/2015/04/09/relative-performance-of-arm-cortex-a-32-bit-and-64-bit-cores.
50. ↑ "Cortex-A57". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a57.
51. ↑ "Cortex-A72". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a72.
52. ↑ "Cortex-Ax vs performance". http://www.bitkistl.com/2015/03/cortex-ax-vs-performnace.html.
53. ↑ "Cortex-A73". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a73.
54. ↑ "Hardware.Info Nederland" (in nl). https://nl.hardware.info/reviews/7394/4/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a55-efficientie.
55. ↑ "Cortex-A55". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55.
56. ↑ "Cortex-A65". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65.
57. ↑ "Cortex-A65AE". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae.
58. ↑ "Hardware.Info Nederland" (in nl). https://nl.hardware.info/reviews/7394/5/preview-arms-nieuwe-cpu--en-gpu-architecturen-cortex-a75-high-performancen.
59. ↑ "Cortex-A75". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a75.
60. ↑ 60.0 60.1 60.2 "Arm's Cortex-A76 CPU Unveiled: Taking Aim at the Top for 7nm". https://anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse/2.
61. ↑ "Cortex-A76". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a76.
62. ↑ "Cortex-A76AE". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a76ae.
63. ↑ "Cortex-A77". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a77.
64. ↑ "Cortex-A78". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78.
65. ↑ "Cortex-A78AE". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78ae.
66. ↑ "Cortex-A78C". https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c.
67. ↑ 67.0 67.1 "First Armv9 Cortex CPUs for Consumer Compute" (in en). https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/first-armv9-cpu-cores.
68. ↑ "Neoverse N1". https://developer.arm.com/ip-products/processors/neoverse/neoverse-n1.
69. ↑ "Neoverse E1". https://developer.arm.com/ip-products/processors/neoverse/neoverse-e1.
70. ↑ "Processor Cores". Faraday Technology. http://www.faraday-tech.com/html/Product/IPProduct/ProcessorCores/index.htm.
71. ↑ "3rd Generation Intel XScale Microarchitecture: Developer's Manual". download.intel.com. Intel. May 2007. http://download.intel.com/design/intelxscale/31628302.pdf.
72. ↑ 72.0 72.1 "Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored". https://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture.
73. ↑ "Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute". Qualcomm. 2015-09-02. https://www.qualcomm.com/news/snapdragon/2015/09/02/snapdragon-820-and-kryo-cpu-heterogeneous-computing-and-role-custom.
74. ↑ Lal Shimpi, Anand (15 September 2012). "The iPhone 5's A6 SoC: Not A15 or A9, a Custom Apple Core Instead". AnandTech. http://www.anandtech.com/show/6292/iphone-5-a6-not-a15-custom-core.
75. ↑ 75.0 75.1 Smith, Ryan (November 11, 2014). "Apple A8X's GPU - GAX6850, Even Better Than I Thought". http://www.anandtech.com/show/8716/apple-a8xs-gpu-gxa6850-even-better-than-i-thought.
76. ↑ Chester, Brandon (July 15, 2015). "Apple Refreshes The iPod Touch With A8 SoC And New Cameras". http://www.anandtech.com/show/9443/apple-refreshes-the-ipod-touch-with-a8-soc-and-new-camera.
77. ↑ Ho, Joshua (September 28, 2015). "iPhone 6s and iPhone 6s Plus Preliminary Results". http://www.anandtech.com/show/9662/iphone-6s-and-iphone-6s-plus-preliminary-results.
78. ↑ Ho, Joshua (September 28, 2015). "The iPhone 7 and iPhone 7 Plus Review". http://www.anandtech.com/show/10685/the-iphone-7-and-iphone-7-plus-review.
79. ↑ "A11 Bionic - Apple". WikiChip. https://en.wikichip.org/wiki/apple/ax/a11.
80. ↑ "The iPhone XS & XS Max Review: Unveiling the Silicon Secrets". https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets/.
81. ↑ Frumusanu, Andrei. "The Apple iPhone 11, 11 Pro & 11 Pro Max Review: Performance, Battery, & Camera Elevated". https://www.anandtech.com/show/14892/the-apple-iphone-11-pro-and-max-review.
82. ↑ Frumusanu, Andrei. "The iPhone 12 & 12 Pro Review: New Design and Diminishing Returns". https://www.anandtech.com/show/16192/the-iphone-12-review.
83. ↑ "AppliedMicro's 64-core chip could spark off ARM core war copy". 12 August 2014. http://www.pcworld.com/article/2464600/appliedmicros-64core-chip-could-spark-off-arm-core-war.html.
84. ↑ "NVIDIA Denver Hot Chips Disclosure". http://www.anandtech.com/Gallery/Album/3847.
85. ↑ "Mile High Milestone: Tegra K1 "Denver" Will Be First 64-bit ARM Processor for Android". http://blogs.nvidia.com/blog/2014/08/11/tegra-k1-denver-64-bit-for-android/.
86. ↑ "Drive Xavier für autonome Autos wird ausgeliefert" (in de). https://www.golem.de/news/nvidia-drive-xavier-fuer-autonome-autos-wird-ausgeliefert-1801-132035.html.
87. ↑ "NVIDIA Drive Xavier SOC Detailed – A Marvel of Engineering, Biggest and Most Complex SOC Design To Date With 9 Billion Transistors". 8 January 2018. https://wccftech.com/nvidia-drive-xavier-soc-detailed/.
88. ↑ "AMD Announces K12 Core: Custom 64-bit ARM Design in 2016". http://www.anandtech.com/show/7990/amd-announces-k12-core-custom-64bit-arm-design-in-2016.
89. ↑ "Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU". https://www.anandtech.com/show/9781/samsung-announces-exynos-8890-with-cat1213-modem-and-custom-cpu.
90. ↑ "Hot Chips 2018: Samsung's Exynos-M3 CPU Architecture Deep Dive". AnandTech. https://www.anandtech.com/show/13199/hot-chips-2018-samsungs-exynosm3-cpu-architecture-deep-dive.
91. ↑ "Evolution of the Samsung Exynos CPU Microarchitecture". https://conferences.computer.org/isca/pdfs/ISCA2020-4QlDegUf3fKiwUXfV0KdCm/466100a040/466100a040.pdf.
92. ↑ "ARM Company Milestones.". http://www.arm.com/about/company-profile/milestones.php.
93. ↑ "ARM Press Releases.". http://www.arm.com/about/newsroom/index.php.
94. ↑ "Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence". https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging.
95. ↑ "Arm Announces Neoverse V1 & N2 Infrastructure CPUs: +50% IPC, SVE Server Cores". 2020-09-22. https://www.anandtech.com/show/16073/arm-announces-neoverse-v1-n2.

## Further reading

* v
* t
* e

Application ARM-based chips

* ARM Holdings
* ARM architecture
* List of ARM microarchitectures
* List of applications of ARM cores
* ARM Cortex-A
* ARM Cortex-R
* ARM Cortex-M
* Comparison of ARMv7-A cores
* Comparison of ARMv8-A cores

Application
processors
(32-bit)|

| Cortex-A5|

* Actions ATM702x
* Amlogic M805/S805, T82x
* Atmel SAMA5D3
* InfoTM iMAPx820, iMAPx15
* Qualcomm Snapdragon S4 Play, 200
* RDA RDA8810PL
* Telechips TCC892x

|

Cortex-A7|

* Allwinner A2x, A3x, A83T, H3, H8
* NXP i.MX7, QorIQ LS10xx, NXP i.MX6UL
* Broadcom VideoCore BCM2836, BCM23550
* Leadcore LC1813, LC1860/C, LC1913, LC1960
* Marvell Armada PXA1920, 1500 mini plus
* MediaTek MT65xx
* Qualcomm Snapdragon 200, 400

Cortex-A8|

* Allwinner A1x
* Apple A4
* Freescale i.MX5
* Rockchip RK291x
* Samsung Exynos 3110(S5PC110), S5PV210
* Texas Instruments OMAP 3
* Texas Instruments Sitara AM3xxx
* Texas Instruments DM38x
* ZiiLABS ZMS-08

Cortex-A9|

* Actions ATM702x, ATM703x
* Altera Cyclone V, Arria V/10
* Amlogic AML8726, MX, M6x, M801, M802/S802, S812, T86x
* Apple A5, A5X
* Broadcom VideoCore BCM21xxx, BCM28xxx
* Freescale i.MX6
* HiSilicon K3V2, 910's
* InfoTM iMAPx912
* Leadcore LC1810, LC1811
* Marvell Armada 1500 mini
* MediaTek MT65xx
* Nvidia Tegra, 2, 3, 4i
* Nufront NuSmart 2816M, NS115, NS115M
* Renesas EMMA EV2, R-Car H1, RZ/A
* Rockchip RK292x, RK30xx, RK31xx
* Samsung Exynos 4 421x, 441x
* ST-Ericsson NovaThor
* Telechips TCC8803
* Texas Instruments OMAP 4
* Texas Instruments Sitara AM4xxx
* VIA WonderMedia WM88x0, 89x0
* Xilinx Zynq-7000
* ZiiLABS ZMS-20, ZMS-40

Cortex-A15|

* Allwinner A80
* HiSilicon K3V3
* MediaTek MT8135/V
* Nvidia Tegra 4, K1
* Renesas R-Car H2
* Samsung Exynos 5 52xx, 54xx
* Texas Instruments OMAP 5, DRA7xx, AM57xx
* Texas Instruments Sitara AM5xxx

Cortex-A17|

* MediaTek MT6595, MT5595
* MStar 6A928
* Rockchip RK3288

ARMv7-A
compatible|

* Apple A6, A6X, S1, S1P, S2, S3
* Broadcom Brahma-B15
* Marvell P4J
* Qualcomm Snapdragon S1, S2, S3, S4 Plus, S4 Pro, 600, 800 (Scorpion, Krait)

Others|

* Enhanced Cortex-A8
* Enhanced Cortex-A9
* Cortex-A12
* Cortex-A32

Application
processors
(64-bit)|

| Cortex-A35|

* NXP i.MX8X
* MediaTek MT8516
* Rockchip RK3308

|

Cortex-A53|

* Actions GT7, S900, V700
* Allwinner A64, H5, H64, R18
* Altera Stratix 10
* Amlogic S9 Family, T96x
* Broadcom BCM2837
* EZchip TILE-Mx100
* HiSilicon Kirin 620, 65x, 93x
* Marvell Armada PXA1928, Mobile PXA1908/PXA1936
* MediaTek MT673x, MT675x, MT6795, MT873x, MT8752, MT8163
* NXP ARM S32, QorIQ LS1088, i.MX8M
* Qualcomm Snapdragon 41x, 42x, 43x, 61x, 62x
* Rockchip RK3328, RK3368
* Samsung Exynos 7 75xx, 78xx
* Spreadtrum SC9860/GV, SC9836
* Texas Instruments Sitara AM6xxx
* Xilinx ZynqMP

Cortex-A55|

* Samsung Exynos 9 Series 98xx
* Unisoc SC9863A

Cortex-A57|

* AMD Opteron A1100-series
* NXP QorIQ LS20xx
* Nvidia Tegra X1 and Tegra X2
* Qualcomm Snapdragon 808, 810
* Samsung Exynos 7 5433, 7420
* HiSilicon Kirin Hi1610 and Hi1612

Cortex-A72|

* HiSilicon Kirin 95x, Kunpeng 916
* MediaTek Helio X2x, MT817x
* MStar 6A938
* Qualcomm Snapdragon 65x
* Rockchip RK3399
* NXP QorIQ LS2088, QorIQ LS1046A, i.MX8

Cortex-A73|

* HiSilicon Kirin 960, Kirin 970
* MediaTek Helio X30
* Amlogic S922X

Cortex-A75|

* Qualcomm Snapdragon 71x, Snapdragon 845 and 850
* Samsung Exynos 9820, Exynos 9825

Cortex-A76|

* HiSilicon Kirin 980, Kirin 990
* Qualcomm Snapdragon 855 and 8cx, Snapdragon 675, Snapdragon 730 and 730G
* MediaTek Helio G90

Cortex-A77|

* MediaTek Dimensity 1000

ARMv8-A
compatible|

* Apple A7, A8, A8X, A9, A9X, A10, A10X, A11, A12, A12X, A13
* Applied Micro X-Gene
* Cavium ThunderX, ThunderX2
* HiSilicon TaiShan v110
* Nvidia Tegra K1 (Denver), Tegra X2 (Denver2), Tegra Xavier (Carmel),
* Qualcomm Kryo, Falkor
* Samsung Mongoose

* v
* t
* e

Classic ARM-based chips

* ARM Holdings
* ARM architecture
* List of ARM cores
* ARM Cortex-A
* ARM Cortex-R
* ARM Cortex-M
* List of ARM Cortex-M development tools

Classic
processors|

| ARM7|

* Atmel SAM7L, SAM7S, SAM7SE, SAM7X, SAM7XC, AT91CAP7, AT91M, AT91R
* Cirrus Logic PS7xxx, EP7xxx
* Mediatek MT62xx
* NXP LPC2100, LPC2200, LPC2300, LPC2400, LH7
* STMicroelectronics STR7

|

ARM9|

* Aspeed AST2400
* Atmel SAM9G, SAM9M, SAM9N, SAM9R, SAM9X, SAM9XE, SAM926x, AT91CAP9
* Cirrus Logic EP9xxx
* Freescale i.MX1x, i.MX2x
* Nuvoton NUC900
* NXP LPC2900, LPC3000, LH7A
* Rockchip RK27xx, RK28xx
* Samsung S3C24xx
* ST-Ericsson Nomadik STn881x
* STMicroelectronics STR9
* Texas Instruments OMAP 1, AM1x, DaVinci
* VIA WonderMedia WM8505/8650
* ZiiLABS ZMS-05

ARM11|

* Broadcom BCM2835
* Cavium CNS3xxx
* Freescale i.MX3x
* Infotmic IMAPX210/220
* Mindspeed Comcerto 1000
* Nvidia Tegra APX, 6xx
* Qualcomm MSM7000, Snapdragon S1
* Samsung S3C64xx, S5P64xx
* ST-Ericsson Nomadik STn882x
* Telechips TCC8902
* Texas Instruments OMAP 2
* VIA WonderMedia WM87x0

ARMv2a
compatible|

* Amber (open FPGA core)

ARMv4
compatible|

* Faraday FA526, FA626
* DEC/Intel StrongARM

ARMv5TE
compatible|

* Intel/Marvell XScale
* Marvell Sheeva, Feroceon, Jolteon, Mohawk
* Faraday FA606TE, FA616TE, FA626TE, FA726TE

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