Montecito (processor)

Short description: Microprocessor from Intel

Montecito is the code-name of a major release of Intel's Itanium 2 Processor Family (IPF), which implements the Intel Itanium architecture on a dual-core processor. It was officially launched by Intel on July 18, 2006 as the "Dual-Core Intel Itanium 2 processor". According to Intel, Montecito doubles performance versus the previous, single-core Itanium 2 processor, and reduces power consumption by about 20%.[1] It also adds multi-threading capabilities (two threads per core), a greatly expanded cache subsystem (12 MB per core), and silicon support for virtualization.

## Architectural features and attributes

* Two cores per die
* 2-way coarse-grained multithreading per core (not simultaneous). Montecito-flavour of multi-threading is dubbed temporal, or TMT. This is also known as switch-on-event multithreading, or SoEMT. The two separate threads do not run simultaneously, but the core switches thread in case of a high latency event, like an L3 cache miss which would otherwise stall execution. By this technique, multi-threaded workloads, including database-like workloads, should improve by 15-35%.[citation needed]
* a total of 4 threads per die
* separate 16 KB Instruction L1 and 16 KB Data L1 cache per core
* separate 1 MB Instruction L2 and 256 KB Data L2 cache per core, improved hierarchy
* 12 MB L3 cache per core, 24 MB L3 per die
* 1.72 billion transistors per die, which is added up from:
* core logic — 57M, or 28.5M per core
* core caches — 106.5M
* 24 MB L3 cache — 1550M
* bus logic & I/O — 6.7M
* Die size is 27.72 mm × 21.5 mm, or 596 mm2
* 90 nanometer design
* Lower power consumption and thermal dissipation than earlier flagship Itaniums, despite the high transistor count; 75-104 W. This is mainly achieved by applying different types of transistors. By default, slower and low-leakage transistors were used, while high-speed, thus high-leakage ones where it was necessary.
* Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This was code-named Pellston technology during development, and has recently been renamed Intel Cache Safe Technology.
* Virtualization technology allowing multiple OS instances per chip. This was known as Silvervale technology during development, and is now called Intel Virtualization Technology.
* Improved, higher bandwidth front side bus (FSB), with three times the capacity of the existing bus design. It is meant to be at system level (per node, with 4 dies). System throughput per node should be at least 21 GB/s, which suggest dual 333.333 MHz (double pumped, resulting 2×667 effective MHz) front side bus. However, it is up to system integrators how they organize their bus topology.
* All Montecito processors support 533 MHz / 400 MHz FSB speed.
* Also available with legacy FSB for upgrading existing system designs.
* Eliminates the hardware-based x86 instruction emulation circuitry, in favor of the more efficient software-based IA-32 Execution Layer.[2]

On October 25, 2005 Intel announced that the first dual-core Itanium processor would be delayed until "the middle of next year." [3] Montecito was launched on July 18, 2006. Due to unspecified issues, Intel's Foxton power management technology was disabled in the first release of Montecito, and the front-side bus frequency was reduced to 267 MHz (533.333 MHz effective) instead of the 333 MHz speed originally scheduled for the design [3].

At the time of launch, the following models and pricing were available:

* Itanium 2 9050 1.60 GHz / 24 MB L3 -- $3,692
* Itanium 2 9040 1.60 GHz / 16 MB L3 -- $1,980
* Itanium 2 9030 1.60 GHz / 8 MB L3 -- $1,552
* Itanium 2 9020 1.42 GHz / 12 MB L3 -- $910
* Itanium 2 9015 1.40 GHz / 12 MB L3 -- $749
* Itanium 2 9010 1.60 GHz / 6 MB L3 / single core -- $696

There are no plans for additional Montecito processors; the successor, Montvale was released in late 2007.

## Successors

See Itanium future processors

## External links

* Willard Ph.D., Christopher G.; Eastwood, Matthew; Wu, Jie; Snell, Addison (July 2006). "Intel Brings Dual-Core Capabilities to Itanium 2 with Montecito Processor". Manufacturing Insights. http://www.manufacturing-insights.com/MI/getdoc.jsp?containerId=202865.

* v
* t
* e

Intel processors

Discontinued

BCD oriented (4-bit)|

* 4004 (1971)
* 4040 (1974)

pre-x86 (8-bit)|

* 8008 (1972)
* 8080 (1974)
* 8085 (1977)

Early x86 (16-bit)|

* 8086 (1978)
* 8088 (1979)
* 80186 (1982)
* 80188 (1982)
* 80286 (1982)

x87 (external FPUs)|

8/16-bit databus
8087 (1980)
16-bit databus
80187
80287
80387SX
32-bit databus
80387DX
80487

IA-32 (32-bit)|

* 80386
* SX
* 376
* EX
* 80486
* SX
* DX2
* DX4
* SL
* RapidCAD
* OverDrive
* A100/A110
* Celeron (1998)
* M
* D (2004)
* Pentium
* Original P5
* OverDrive
* Pro
* II
* II OverDrive
* III
* 4
* M
* Dual-Core
* some Core
* Solo
* Duo
* Tolapai

x86-64 (64-bit)|

* Celeron
* D
* Dual-Core
* Pentium
* 4
* D
* Extreme Edition
* Dual-Core
* some Core
* 2
* some i7

Other|

CISC
iAPX 432
Itanium
RISC
i860
i960
StrongARM
XScale

Current

IA-32 (32-bit)|

* Atom
* CE
* SoC
* Quark

x86-64 (64-bit)|

* Atom
* CE
* SoC
* Celeron
* Pentium
* Core
* i3
* i5
* i7
* i9
* M
* Xeon
* E3
* E5
* E7
* D
* Phi

Lists

* Celeron
* Pentium
* Pro
* II
* III
* 4
* D
* M
* Core
* Core
* 2
* i3
* i5
* i7
* i9
* M
* Atom
* Xeon
* Itanium

Related

* Tick–tock model
* Chipsets
* GPUs
* GMA
* HD and Iris Graphics
* PCHs
* SCHs
* ICHs
* PIIXs
* Stratix
* Codenames

Microarchitectures

x86|

| P5|

800 nm

600 nm
P54C
350 nm
P54CS
P55C
250 nm
Tillamook

|

P6, Pentium M,
Enhanced Pentium M|

500 nm

350 nm

Klamath
250 nm
Mendocino
Dixon
Tonga
Covington
Deschutes
Katmai
Drake
Tanner
180 nm
Coppermine
Coppermine T
Timna
Cascades
130 nm
Tualatin
Banias
90 nm
Dothan
Stealey
Tolapai
Canmore
65 nm
Yonah
Sossaman

NetBurst|

180 nm
Willamette
Foster
130 nm
Northwood
Gallatin
Prestonia
90 nm
Tejas and Jayhawk
Prescott
Smithfield
Nocona
Irwindale
Cranford
Potomac
Paxville
65 nm
Cedar Mill
Presler
Dempsey
Tulsa

Core|

65 nm
Merom-L
Merom
Conroe-L
Allendale
Conroe
Kentsfield
Woodcrest
Clovertown
Tigerton

45 nm
Penryn
Penryn-QC
Wolfdale
Yorkfield
Wolfdale-DP
Harpertown
Dunnington

Nehalem|

45 nm
Auburndale
Beckton (Nehalem-EX)
Bloomfield
Clarksfield
Gainestown (Nehalem-EP)
Havendale
Jasper Forest
Lynnfield

32 nm
Arrandale
Clarkdale
Gulftown (Westmere-EP)
Westmere-EX

Sandy Bridge|

32 nm
Sandy Bridge
Sandy Bridge-E
Gladden

22 nm
Ivy Bridge
Ivy Bridge-EP
Ivy Bridge-EX

Haswell|

22 nm
Haswell

14 nm
Broadwell

Skylake|

14 nm
Skylake
Kaby Lake (Amber Lake • Whiskey Lake)
Coffee Lake
Cascade Lake
Comet Lake

Palm Cove|

10 nm
Cannon Lake

Sunny Cove|

14 nm
Cooper Lake

10 nm
Ice Lake

Willow Cove|

14 nm
Rocket Lake

10 nm
Tiger Lake
Sapphire Rapids

Golden Cove|

7 nm
Alder Lake
Granite Rapids

Atom|

| Bonnell
Saltwell|

45 nm
Silverthorne
Diamondville
Pineview
Lincroft
Tunnel Creek
Stellarton
Sodaville
Groveland

32 nm
Cedarview
Penwell
Cloverview
Berryville
Centerton

|

Silvermont
Airmont|

22 nm
Valleyview
Tangier
Anniedale

14 nm
Cherryview

Goldmont|

14 nm
Goldmont
Goldmont Plus

Tremont|

10 nm
Tremont
Gracemont

0.00

(0 votes)

Original source: https://en.wikipedia.org/wiki/Montecito (processor). Read more

|

Retrieved from "https://handwiki.org/wiki/index.php?title=Engineering:Montecito_(processor)&oldid=232625"
*[v]: View this template
*[t]: Discuss this template
*[e]: Edit this template