Socket FM1

Type| PGA-ZIF
Chip form factors| PGA
Contacts| 905
FSB protocol| Unified Media Interface (UMI)
FSB frequency| 100 MHz System clock
UMI up to 5,2 GT/s
Processors| early A-series APUs
Successor| FM2

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This article is part of the CPU socket series

Short description: CPU socket for AMD CPUs

Socket FM1 is a CPU socket for desktop computers used by AMD early A-series APUs ("Llano") processors and Llano-derived Athlon II processors. It was released in July 2011. Its direct successors are Socket FM2 (September 2012) and Socket FM2+ (January 2014), while Socket AM1 (January 2014) is targeting low-power SoCs.

## Contents

* 1 Chipsets
* 2 Available APUs
* 3 Feature overview for AMD APUs
* 4 See also
* 5 References

## Chipsets

For available chipsets consult Fusion controller hubs (FCH).

## Available APUs

APU's using Socket FM1 are AMD's Lynx platform.

Please consult List of AMD accelerated processing units for concrete product denominations.

## Feature overview for AMD APUs

The following table shows features of AMD's APUs (see also: List of AMD accelerated processing units).

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Codename | Server  | Basic  |  | Toronto |  |  |

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Micro  |  |  | Kyoto |
Desktop | Mainstream  |  | Carrizo | Bristol Ridge | Raven Ridge | Picasso |  |
Entry  | Llano | Trinity | Richland | Kaveri |
Basic  |  |  | Kabini |
Mobile | Performance  |  | Renoir |
Mainstream  | Llano | Trinity | Richland | Kaveri | Carrizo | Bristol Ridge | Raven Ridge | Picasso
Entry  |  |  | Dalí
Basic  |  | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge
Embedded  |  | Trinity |  | Bald Eagle | Merlin Falcon,
Brown Falcon |  | Great Horned Owl |  | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle,
LX-Family |  | Prairie Falcon | Banded Kestrel
Platform | High, standard and low power | Low and ultra-low power
Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019
CPU microarchitecture | K10 | Piledriver | Steamroller | Excavator | "Excavator+"[1] | Zen | Zen+ | Zen 2 | Bobcat | Jaguar | Puma | Puma+[2] | "Excavator+" | Zen
ISA | x86-64 | x86-64
Socket | Desktop | High-end | N/A | N/A
Mainstream | N/A | AM4
Entry | FM1 | FM2 | FM2+[lower-alpha 1] | N/A
Basic | N/A | N/A | AM1 | N/A
Other | FS1 | FS1+, FP2 | FP3 | FP4 | FP5 | FP6 | FT1 | FT3 | FT3b | FP4 | FP5
PCI Express version | 2.0 | 3.0 | 2.0 | 3.0
[[Engineering:Semiconductor device fabricatFab. (Nanometre|nm]]) | GF 32SHP
(HKMG SOI) | GF 28SHP
(HKMG bulk) | GF 14LPP
(FinFET bulk) | GF 12LP
(FinFET bulk) | TSMC N7
(FinFET bulk) | TSMC N40
(bulk) | TSMC N28
(HKMG bulk) | GF 28SHP
(HKMG bulk) | GF 14LPP
(FinFET bulk)
Die area (mm2) | 228 | 246 | 245 | 245 | 250 | 210[3] | 156 | 75 (+ 28 FCH) | 107 | ? | 125 |
Min TDP (W) | 35 | 17 | 12 | 10 | 4.5 | 4 | 3.95 | 10 | 6
Max APU TDP (W) | 100 | 95 | 65 | 54 | 18 | 25
Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.3 | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 3.3
Max APUs per node[lower-alpha 2] | 1 | 1
Max CPU[lower-alpha 3] cores per APU | 4 | 8 | 2 | 4 | 2
Max threads per CPU core | 1 | 2 | 1 | 2
Integer structure | 3+3 | 2+2 | 4+2 | 4+2+1 | 1+1+1+1 | 2+2 | 4+2
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF |  |
IOMMU[lower-alpha 4] | N/A |
BMI1, AES-NI, CLMUL, and F16C | N/A |
MOVBE | N/A |
AVIC, BMI2 and RDRAND | N/A |
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO | N/A |  | N/A |
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT | N/A |  | N/A
FPUs per core | 1 | 0.5 | 1 | 1 | 0.5 | 1
Pipes per FPU | 2 | 2
FPU pipe width | 128-bit | 256-bit | 80-bit | 128-bit
CPU instruction set SIMD level | SSE4a[lower-alpha 5] | AVX | AVX2 | SSSE3 | AVX | AVX2
3DNow! | 3DNow!+ | N/A | N/A
PREFETCH/PREFETCHW |  |
FMA4, LWP, TBM, and XOP | N/A |  | N/A | N/A |  | N/A
FMA3 |  |
L1 data cache per core (KiB) | 64 | 16 | 32 | 32
L1 data cache associativity (ways) | 2 | 4 | 8 | 8
L1 instruction caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1
Max APU total L1 instruction cache (KiB) | 256 | 128 | 192 | 256 | 64 | 128 | 96 | 128
L1 instruction cache associativity (ways) | 2 | 3 | 4 | 8 | 2 | 3 | 4
L2 caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1
Max APU total L2 cache (MiB) | 4 | 2 | 4 | 1 | 2 | 1
L2 cache associativity (ways) | 16 | 8 | 16 | 8
APU total L3 cache (MiB) | N/A | 4 | 8 | N/A | 4
APU L3 cache associativity (ways) | 16 | 16
L3 cache scheme | Victim | N/A | Victim | Victim
Max stock DRAM support | DDR3-1866 | DDR3-2133 | DDR3-2133, DDR4-2400 | DDR4-2400 | DDR4-2933 | DDR4-3200, LPDDR4-4266 | DDR3L-1333 | DDR3L-1600 | DDR3L-1866 | DDR3-1866, DDR4-2400 | DDR4-2400
Max DRAM channels per APU | 2 | 1 | 2
Max stock DRAM bandwidth (GB/s) per APU | 29.866 | 34.132 | 38.400 | 46.932 | 68.256 | 10.666 | 12.800 | 14.933 | 19.200 | 38.400
GPU microarchitecture | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | GCN 2nd gen | GCN 3rd gen | GCN 5th gen[4] | TeraScale 2 (VLIW5) | GCN 2nd gen | GCN 3rd gen[4] | GCN 5th gen
GPU instruction set | TeraScale instruction set | GCN instruction set | TeraScale instruction set | GCN instruction set
Max stock GPU base clock (MHz) | 600 | 800 | 844 | 866 | 1108 | 1250 | 1400 | 1750 | 538 | 600 | ? | 847 | 900 | 1200
Max stock GPU base GFLOPS[lower-alpha 6] | 480 | 614.4 | 648.1 | 886.7 | 1134.5 | 1760 | 1971.2 | 1792 | 86 | ? | ? | ? | 345.6 | 460.8
3D engine[lower-alpha 7] | Up to 400:20:8 | Up to 384:24:6 | Up to 512:32:8 | Up to 704:44:16[5] | Up to 512:?:? | 80:8:4 | 128:8:4 | Up to 192:?:? | Up to 192:?:?
IOMMUv1 | IOMMUv2 |  | IOMMUv1 | ? | IOMMUv2
Video decoder | UVD 3.0 | UVD 4.2 | UVD 6.0 | VCN 1.0[6] |  | UVD 3.0 | UVD 4.0 | UVD 4.2 | UVD 6.0 | UVD 6.3 | VCN 1.0
Video encoder | N/A | VCE 1.0 | VCE 2.0 | VCE 3.1 |  | N/A | VCE 2.0 | VCE 3.1
GPU power saving | PowerPlay | PowerTune |  | PowerPlay | PowerTune[7]
TrueAudio | N/A | [8] | N/A |
FreeSync | 1
2 | 1

HDCP[lower-alpha 8] | ? | 1.4 | 1.4
2.2 | ? | 1.4 | 1.4
2.2
PlayReady[lower-alpha 8] | N/A | 3.0 not yet |  | N/A | 3.0 not yet
Supported displays[lower-alpha 9] | 2–3 | 2–4 | 3 | 3 (desktop)
4 (mobile, embedded) | 4 | 2 | 3 | 4
`/drm/radeon`[lower-alpha 10][10][11] |  | N/A |  | N/A
`/drm/amdgpu`[lower-alpha 10][12] | N/A | [13] |  | N/A | [13] |

1. ↑ APU models: A8-7680, A6-7480. CPU only: Athlon X4 845.
2. ↑ A PC would be one node.
3. ↑ An APU combines a CPU and a GPU. Both have cores.
4. ↑ Requires firmware support.
5. ↑ No SSE4. No SSSE3.
6. ↑ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
7. ↑ Unified shaders : texture mapping units : render output units
8. ↑ 8.0 8.1 To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
9. ↑ To feed more than two displays, the additional panels must have native DisplayPort support.[9] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
10. ↑ 10.0 10.1 DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

## See also

* Family 12h microarchitecture
* Comparison of AMD chipsets#Fusion controller hubs (FCH)
* List of FM1 Processors

## References

1. ↑ "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks. Retrieved 3 January 2020.
2. ↑ "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
3. ↑ "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/. Retrieved 13 December 2017.
4. ↑ 4.0 4.1 "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/. Retrieved 6 June 2017.
5. ↑ Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3. Retrieved 7 February 2018.
6. ↑ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands. Retrieved 20 November 2017.
7. ↑ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture", AMD, http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf, retrieved 13 August 2016
8. ↑ "A technical look at AMD's Kaveri architecture". Semi Accurate. http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/. Retrieved 6 July 2014.
9. ↑ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. http://support.amd.com/en-us/search/faq/154. Retrieved 8 December 2014.
10. ↑ Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". http://airlied.livejournal.com/68805.html. Retrieved 16 January 2016.
11. ↑ "Radeon feature matrix". freedesktop.org. http://xorg.freedesktop.org/wiki/RadeonFeature/. Retrieved 10 January 2016.
12. ↑ Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU". http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf. Retrieved 16 January 2016.
13. ↑ 13.0 13.1 Michel Dänzer (17 November 2016). "[ANNOUNCE xf86-video-amdgpu 1.2.0"]. lists.x.org. https://lists.x.org/archives/xorg-announce/2016-November/002741.html.

* http://www.tomshardware.com/news/amd-llano-socket-fm1-sample,12549.html
* https://www.amd.com/us/products/desktop/processors/a-series/Pages/a-series-model-number-comparison.aspx

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AMD sockets and chipsets

AMD sockets

| Desktop sockets|

* Super Socket 7
* Slot A (1999)
* Socket A (2000)
* 754 (2003)
* 939 (2004)
* 940 (2003)
* AM2 (2006)
* AM2+ (2007)
* AM3 (2009)
* AM3+ (2011)
* FM1 (2011)
* FM2 (2012)
* FM2+ (2014)
* AM1 (2014)
* AM4 (2016)
* TR4 (2017)
* sTRX4 (2019)

|

Mobile sockets|

* Socket A
* 563
* 754
* S1 (2006)
* FT1 (2011)
* FP2 (2012)
* FS1
* FT3
* FP3 (2014)
* FP4 (2015)
* FP5 (2019)
* FP6 (2020)

Server sockets|

* Socket A
* 940
* F (2006)
* F+
* G3 (never)
* G34 (2010)
* C32 (2010)
* SP3 (2017)

Motherboard chipsets List of AMD chipsets

| ATI chipsets|

* IGP 300 series/RX380
* Radeon Xpress 200
* CrossFire Xpress 3200
* Radeon Xpress 1250

|

AMD chipsets|

* 480X/570X/580X
* 690 Series
* 7-Series
* 8-Series
* 9-Series
* Fusion Controller Hubs
* AM4 chipsets
* TR4 chipsets
* sTRX4 chipsets

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