Structured ASIC platform

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Structured ASIC is an intermediate technology between ASIC and FPGA, offering high performance, a characteristic of ASIC, and low NRE cost, a characteristic of FPGA. Using Structured ASIC allows products to be introduced quickly to market, to have lower cost and to be designed with ease.

In a FPGA, interconnects and logic blocks are programmable after fabrication, offering high flexibility of design and ease of debugging in prototyping. However, the capability of FPGAs to implement large circuits is limited, in both size and speed, due to complexity in programmable routing, and significant space occupied by programming elements, e.g. SRAMs, MUXes. On the other hand, ASIC design flow is expensive. Every different design needs a complete different set of masks. The Structured ASIC is a solution between these two. It has basically the same structure as a FPGA, but being mask-programmable instead of field-programmable, by configuring one or several via layers between metal layers. Every SRAM configuration bit can be replaced by a choice of putting a via or not between metal contacts.

A number of commercial vendors have introduced structured ASIC products. They have a wide range of configurability, from a single via layer to 6 metal and 6 via layers. Altera's Hardcopy-II, eASIC's Nextreme are examples of commercial structured ASICs.

## See also

* Gate array
* Altera Corp - "HardCopy II Structured ASICs"
* eASIC Corp - "Nextreme Structured ASIC"

## References

* Chun Hok Ho et al. - "Floating Point FPGA: Architecture and Modelling"
* Chun Hok Ho et al. - "DOMAIN-SPECIFIC HYBRID FPGA: ARCHITECTURE AND FLOATING POINT APPLICATIONS"
* Steve Wilton et al. - "A Synthesizable Datapath-Oriented Embedded FPGA Fabric"
* Steve Wilton et al. - "A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications"
* Andy Ye and Jonathan Rose - "Using Bus-Based Connections to Improve Field-Programmable Gate Array Density for Implementing Datapath Circuits"
* Ian Kuon, Aaron Egier and Jonathan Rose - "Design, Layout and Verification of an FPGA using Automated Tools"
* Ian Kuon, Russell Tessier and Jonathan Rose - "FPGA Architecture: Survey and Challenges"
* Ian Kuon and Jonathan Rose - "Measuring the Gap Between FPGAs and ASICs"
* Stephane Badel and Elizabeth J. Brauer - "Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells"
* Kanupriya Gulati, Nikhil Jayakumar and Sunil P. Khatri - "A Structured ASIC Design Approach Using Pass Transistor Logic"
* Hee Kong Phoon, Matthew Yap and Chuan Khye Chai - "A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration"
* Yajun Ran and Malgorzata Marek-Sadowska - "Designing Via-Configurable Logic Blocks for Regular Fabric"
* R. Reed Taylor and Herman Schrnit - "Creating a Power-aware Structured ASIC"
* Jennifer L. Wong, Farinaz Kourshanfar and Miodrag Potkonjak - "Flexible ASIC: Shared Masking for Multiple Media Processors"

External Links: eda.ee.ucla.edu/EE201A-04Spring/ASICslides.ppt

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