Titan (microprocessor)

POWER, PowerPC, and Power ISA architectures

NXP (formerly Freescale and Motorola)

* PowerPC e series (2006)
* e200
* e300
* e500
* e600
* e5500
* e6500

* Qor series (2008)
* QorIQ
* Qorivva

IBM

* POWER series (1990)
* POWER1
* POWER2
* POWER3
* POWER4
* POWER5
* POWER6
* POWER7
* POWER8
* POWER9
* POWER10

* PowerPC series (1992)
* 6xx
* 4xx
* 7xx
* 74xx
* 970
* A2 (2010)
* A2I
* A2O
* RAD series (1997)
* RAD6000
* RAD750
* RAD5500

* RS64 series (1996)

IBM/Nintendo

* Gekko
* Broadway
* Espresso

Other

* #808080">Titan
* PWRficient
* Cell
* Xenon
* X704

Related links

* OpenPOWER Foundation
* AIM alliance
* RISC
* Blue Gene
* Power.org
* PAPR
* PReP
* CHRP
* AltiVec

Cancelled in gray, historic in italic

* v
* t
* e

Titan was a planned family of 32-bit Power ISA-based microprocessor cores designed by Applied Micro Circuits Corporation (AMCC), but was scrapped in 2010.[1] Applied Micro chose to continue development of the PowerPC 400 core instead, on a 40 nm fabrication process.

## Contents

* 1 Details
* 2 Implementations
* 3 References
* 4 External links

## Details

It was designed to be the foundation of embedded processors and system-on-a-chip (SoC) solutions. While being high performance, reaching speeds up to 2 GHz, it would remain extremely power efficient, drawing just 2.5 W per core. Where there usually is a trade-off between performance and power, AMCC used the Fast14 technology from Intrinsity to build an extremely efficient microprocessor design leveraging high performance combined with low power and comparably cheap bulk 90 nm CMOS manufacturing. By using NMOS transistors and no latches, the design results in a chip with fewer transistors than traditional design, thus reducing cost. The design allows for dual core SoC implementations consuming less than 15 W. There were plans for single, dual and quad-core versions.

The Titan had a new superscalar, out of order 8-9 stage core with a novel three-stage CPU cache design. Small 4/4 KiB instruction and data caches at "level 0" sit before the traditional 32/32 KiB L1 caches up to 1 MB L2 cache that will be shared between all cores (supporting up to four). The Titan was compliant with the Power ISA v.2.04.

## Implementations

* APM 83290 – The first implementations of the Titan core design, codenamed Gemeni.[2] Two 1.5 GHz cores with FPU, 512 kB shared L2 cache, DDR2 controller, security engine, multi-channel DMA and I/O engine for gigabit Ethernet, PCIe, USB, RapidIO and SATA. It began sampling in October 2009 [1]. The processor is aimed at telecom and control plane applications. It is built using TSMC's 90 nm bulk CMOS fabrication to reduce cost.[2]

## References

1. ↑ "AMCC takes another shot at multicore". EETimes. 2010-09-27. http://www.eetimes.com/electronics-news/4208848/AMCC-takes-another-shot-at-multicore-semiconductor. Retrieved 2011-07-14.
2. ↑ "AMCC, TSMC put new MPU spin on IBM technology". EETimes. 2009-09-25. http://www.eetimes.com/electronics-news/4084868/AMCC-TSMC-put-new-MPU-spin-on-IBM-technology. Retrieved 2011-07-14.

## External links

* AMCC's pressrelease
* AMCC Next Generation Power Architecture Processor – Titan – Power.org
* AMCC drives to high end of embedded PowerPC market – EETimes
* Intrinsity Nets 2 GHz, 4000 DMIPS PowerPC FastCore – Market Wire

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