Execution unit

Short description: Part of a CPU which performs the operations instructed by the program

This article has multiple issues. Please help improve it or discuss these issues on the talk page. (Learn how and when to remove these template messages)

This article includes a list of references, but its sources remain unclear because it has insufficient inline citations. Please help to improve this article by introducing more precise citations. (December 2014) (Learn how and when to remove this template message)

|

This article's factual accuracy may be compromised due to out-of-date information. Please update this article to reflect recent events or newly available information. (December 2016)

|

(Learn how and when to remove this template message)

In computer engineering, an execution unit (E-unit or EU) is a part of a processing unit that performs the operations and calculations forwarded from the instruction unit.[1] It may have its own internal control sequence unit (not to be confused with a CPU's main control unit), some registers,[2] and other internal units such as an arithmetic logic unit,[3] address generation unit, floating-point unit, load–store unit, branch execution unit[4] or other smaller and more specific components, and can be tailored to support a certain datatype, such as integers or floating-points.[5]

It is common for modern processing units to have multiple parallel functional units within its execution units, which is referred to as superscalar design.[6] The simplest arrangement is to use a single bus manager unit to manage the memory interface and the others to perform calculations. Additionally, modern execution units are usually pipelined.

## References

1. ↑ "Execution Model Overview" (in en). https://www.intel.com/content/www/us/en/docs/oneapi/optimization-guide-gpu/2024-1/execution-model.html.
2. ↑ "AMD Instinct™ MI100 microarchitecture — ROCm Documentation". https://rocm.docs.amd.com/en/docs-6.0.0/conceptual/gpu-arch/mi100.html#microarchitecture.
3. ↑ "Intel® Iris® Xe GPU Architecture" (in en). https://www.intel.com/content/www/us/en/docs/oneapi/optimization-guide-gpu/2023-0/intel-iris-xe-gpu-architecture.html.
4. ↑ Kanter, David (November 13, 2012). "Intel's Haswell CPU Microarchitecture". https://www.realworldtech.com/haswell-cpu/4/.
5. ↑ "Execution Unit" discussion from the University of Massachusetts Amherst, archived on the Wayback Machine
6. ↑ Cohen, William (2016-03-14). "Superscalar Execution" (in en). https://developers.redhat.com/blog/2016/03/14/superscalar-execution.

* v
* t
* e

Processor technologies

Models|

* Turing machine
* Universal
* Post–Turing
* Quantum
* Belt machine
* Stack machine
* Finite-state machine
* with datapath
* Hierarchical
* Queue automaton
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load/store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* comparison
* addressing modes

|

* x86
* ARM
* MIPS
* Power ISA
* SPARC
* Itanium
* Unicore
* MicroBlaze
* RISC-V
* others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Tomasulo algorithm
* Reservation station
* Re-order buffer
* Register renaming

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* SWAR
* SIMT
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Coprocessor
* ASIC
* FPGA
* CPLD
* Multi-chip module (MCM)
* System in package (SiP)

| By application|

* Microprocessor
* Microcontroller
* Mobile
* Notebook
* Ultra-low-voltage
* ASIP

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Programmable (PSoC)
* Network on a chip (NoC)

Hardware
accelerators|

* AI accelerator
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor processing unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 2-bit
* 4-bit
* 8-bit
* 16-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Integrated memory controller (IMC)

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Program counter

Control unit|

* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)
* Race to sleep

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model

* v
* t
* e

Basic computer components

Input devices|

* Keyboard
* Image scanner
* Microphone
* Pointing device
* Graphics tablet
* Game controller
* Light pen
* Mouse
* Optical
* Pointing stick
* Touchpad
* Touchscreen
* Trackball
* Refreshable braille display
* Sound card
* Sound chip
* Webcam
* Softcam
* Video card
* GPU

Output devices|

* Monitor
* Screen
* Refreshable braille display
* Printer
* Plotter
* Speakers
* Sound card
* Video card

Removable
data storage|

* Disk pack
* Floppy disk
* Optical disc
* CD
* DVD
* Blu-ray
* Flash memory
* Memory card
* USB flash drive

Computer case|

* Central processing unit
* Microprocessor
* Motherboard
* Memory
* RAM
* BIOS
* Data storage
* HDD
* SSD
* SSHD
* Power supply
* SMPS
* MOSFET
* Power MOSFET
* VRM
* Network interface controller
* Fax modem
* Expansion card

Ports|

* Ethernet
* FireWire (IEEE 1394)
* Parallel port
* Serial port
* PS/2 port
* USB
* Thunderbolt
* DisplayPort / HDMI / DVI / VGA
* eSATA
* Audio jack

0.00

(0 votes)

Original source: https://en.wikipedia.org/wiki/Execution unit. Read more

|

Retrieved from "https://handwiki.org/wiki/index.php?title=Execution_unit&oldid=3873973"
*[v]: View this template
*[t]: Discuss this template
*[e]: Edit this template