Explicitly parallel instruction computing

Short description: Instruction set architecture

Explicitly parallel instruction computing (EPIC) is a term coined in 1997 by the HP–Intel alliance[1] to describe a computing paradigm that researchers had been investigating since the early 1980s.[2] This paradigm is also called Independence architectures. It was the basis for Intel and HP development of the Intel Itanium architecture,[3] and HP later asserted that "EPIC" was merely an old term for the Itanium architecture.[4] EPIC permits microprocessors to execute software instructions in parallel by using the compiler, rather than complex on-die circuitry, to control parallel instruction execution. This was intended to allow simple performance scaling without resorting to higher clock frequencies.

## Contents

* 1 Roots in VLIW
* 2 Moving beyond VLIW
* 3 Other research and development
* 4 See also
* 5 References
* 6 External links

## Roots in VLIW

By 1989, researchers at HP recognized that reduced instruction set computer (RISC) architectures were reaching a limit at one instruction per cycle.[clarification needed] They began an investigation into a new architecture, later named EPIC.[3] The basis for the research was VLIW, in which multiple operations are encoded in every instruction, and then processed by multiple execution units.

One goal of EPIC was to move the complexity of instruction scheduling from the CPU hardware to the software compiler, which can do the instruction scheduling statically (with help of trace feedback information). This eliminates the need for complex scheduling circuitry in the CPU, which frees up space and power for other functions, including additional execution resources. An equally important goal was to further exploit instruction-level parallelism (ILP) by using the compiler to find and exploit additional opportunities for parallel execution.

VLIW (at least the original forms) has several short-comings that precluded it from becoming mainstream:

* VLIW instruction sets are not backward compatible between implementations. When wider implementations (more execution units) are built, the instruction set for the wider machines is not backward compatible with older, narrower implementations.
* Load responses from a memory hierarchy which includes CPU caches and DRAM do not have a deterministic delay, because the compiler can't predict ahead of time how high in the hierarchy a piece of data is going to be available (more specifically when data will be missing from all cache and need to be fetched from main memory). This makes static scheduling of load instructions by the compiler very difficult.

EPIC architecture evolved from VLIW architecture, but retained many concepts of the superscalar architecture.

## Moving beyond VLIW

EPIC architectures add several features to get around the deficiencies of VLIW:

* Each group of multiple software instructions is called a bundle. Each of the bundles has a stop bit indicating if this set of operations is depended upon by the subsequent bundle. With this capability, future implementations can be built to issue multiple bundles in parallel. The dependency information is calculated by the compiler, so the hardware does not have to perform operand dependency checking.
* A software prefetch instruction is used as a type of data prefetch. This prefetch increases the chances for a cache hit for loads, and can indicate the degree of temporal locality needed in various levels of the cache.
* A speculative load instruction is used to speculatively load data before it is known whether it will be used (bypassing control dependencies), or whether it will be modified before it is used (bypassing data dependencies).
* A check load instruction aids speculative loads by checking whether a speculative load was dependent on a later store, and thus must be reloaded.

The EPIC architecture also includes a grab-bag of architectural concepts to increase ILP:

* Predicated execution is used to decrease the occurrence of branches and to increase the speculative execution of instructions. In this feature, branch conditions are converted to predicate registers which are used to kill results of executed instructions from the side of the branch which is not taken.
* Delayed exceptions, using a not a thing bit within the general purpose registers, allow speculative execution past possible exceptions.
* Very large architectural register files avoid the need for register renaming.
* Multi-way branch instructions improve branch prediction by combining many alternative branches into one bundle.

The Itanium architecture also added rotating register files, a tool useful for software pipelining since it avoids having to manually unroll and rename registers.

## Other research and development

There have been other investigations into EPIC architectures that are not directly tied to the development of the Itanium architecture:

* The IMPACT project at University of Illinois at Urbana–Champaign, led by Wen-mei Hwu, was the source of much influential research on this topic.
* The PlayDoh architecture from HP-labs was another major research project.
* Gelato was an open source development community in which academic and commercial researchers worked to develop more effective compilers for Linux applications running on Itanium servers.

## See also

* Complex instruction set computer (CISC)
* Reduced instruction set computer (RISC)
* Minimal instruction set computer (MISC)
* Very long instruction word (VLIW)
* No instruction set computing
* One-instruction set computer
* Computer architecture
* Superscalar
* Wide-issue

## References

1. ↑ Schlansker and Rau (February 2000). "EPIC: An Architecture for Instruction-Level Parallel Processors" (PDF). HP Laboratories Palo Alto, HPL-1999-111. http://www.hpl.hp.com/techreports/1999/HPL-1999-111.pdf.
2. ↑ Morrison, Gordon E.; Christopher B. Brooks & Frederick G. Gluck, "Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies", US patent 4847755, published 1989-07-11, assigned to MCC Development Ltd.
3. ↑ 3.0 3.1 "Inventing Itanium: How HP Labs Helped Create the Next-Generation Chip Architecture". HP Labs. June 2001. http://www.hpl.hp.com/news/2001/apr-jun/itanium.html.
4. ↑ De Gelas, Johan (November 9, 2005). "Itanium-Is there light at the end of the tunnel?". AnandTech. http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2598.

## External links

* Historical background for EPIC
* Mark Smotherman (2002) "Understanding EPIC Architectures and Implementations"

* v
* t
* e

Processor technologies

Models|

* Turing machine
* Universal
* Post–Turing
* Quantum
* Belt machine
* Stack machine
* Finite-state machine
* with datapath
* Hierarchical
* Queue automaton
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load/store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* comparison
* addressing modes

|

* x86
* ARM
* MIPS
* Power ISA
* SPARC
* Itanium
* Unicore
* MicroBlaze
* RISC-V
* others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Tomasulo algorithm
* Reservation station
* Re-order buffer
* Register renaming

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* SWAR
* SIMT
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Coprocessor
* ASIC
* FPGA
* CPLD
* Multi-chip module (MCM)
* System in package (SiP)

| By application|

* Microprocessor
* Microcontroller
* Mobile
* Notebook
* Ultra-low-voltage
* ASIP

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Programmable (PSoC)
* Network on a chip (NoC)

Hardware
accelerators|

* AI accelerator
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor processing unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 2-bit
* 4-bit
* 8-bit
* 16-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Integrated memory controller (IMC)

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Program counter

Control unit|

* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)
* Race to sleep

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model

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