Hardware acceleration

Short description: Specialized computer hardware

A cryptographic accelerator card allows cryptographic operations to be performed at a faster rate.

Hardware acceleration is the use of computer hardware, known as a hardware accelerator, to perform specific functions faster than can be done by software running on a general-purpose central processing unit (CPU). Any transformation of data that can be calculated by software running on a CPU can also be calculated by an appropriate hardware accelerator, or by a combination of both.

To perform computing tasks more efficiently, generally one can invest time and money in improving the software, improving the hardware, or both. There are various approaches with advantages and disadvantages in terms of decreased latency, increased throughput, and reduced energy consumption.

Typical advantages of focusing on software may include greater versatility, more rapid development, lower non-recurring engineering costs, heightened portability, and ease of updating features or patching bugs, at the cost of overhead to compute general operations.

Advantages of focusing on hardware may include speedup, reduced power consumption,[1] lower latency, increased parallelism[2] and bandwidth, and better utilization of area and functional components available on an integrated circuit; at the cost of lower ability to update designs once etched onto silicon and higher costs of functional verification, times to market, and the need for more parts.

In the hierarchy of digital computing systems ranging from general-purpose processors to fully customized hardware, there is a tradeoff between flexibility and efficiency, with efficiency increasing by orders of magnitude when any given application is implemented higher up that hierarchy (that is, towards the more customized end).[3] This hierarchy includes general-purpose processors such as CPUs,[4] more specialized processors such as programmable shaders in a GPU,[5] applications implemented on field-programmable gate arrays (FPGAs),[6] and fixed-function implemented on application-specific integrated circuits (ASICs).[7]

Hardware acceleration is advantageous for performance, and practical when the functions are fixed, so updates are not as needed as in software solutions. With the advent of reprogrammable logic devices such as FPGAs, the restriction of hardware acceleration to fully fixed algorithms has eased since 2010, allowing hardware acceleration to be applied to problem domains requiring modification to algorithms and processing control flow.[8][9] The disadvantage, however, is that in many open source projects, it requires proprietary libraries that not all vendors are keen to distribute or expose, making it difficult to integrate in such projects.

## Contents

* 1 Overview
* 1.1 Computational equivalence of hardware and software
* 1.2 Stored-program computers
* 1.3 Hardware execution units
* 1.4 Emerging hardware architectures
* 1.5 Implementation metrics
* 2 Applications
* 3 Hardware acceleration units by application
* 4 See also
* 5 References
* 6 External links

## Overview

Integrated circuits are designed to handle various operations on both analog and digital signals. In computing, digital signals are the most common and are typically represented as binary numbers. Computer hardware and software use this binary representation to perform computations. This is done by processing Boolean functions on the binary input, and then outputting the results for storage or further processing by other devices.

### Computational equivalence of hardware and software

Because all Turing machines can run any computable function, it is always possible to design custom hardware that performs the same function as a given piece of software. Conversely, software can always be used to emulate the function of a given piece of hardware. Custom hardware may offer higher performance per watt for the same functions that can be specified in software. Hardware description languages (HDLs) such as Verilog and VHDL can model the same semantics as software and synthesize the design into a netlist that can be programmed to an FPGA or composed into the logic gates of an ASIC.

### Stored-program computers

The vast majority of software-based computing occurs on machines implementing the von Neumann architecture, collectively known as stored-program computers. Computer programs are stored as data and executed by processors. Such processors must fetch and decode instructions, as well as load data operands from memory (as part of the instruction cycle), to execute the instructions constituting the software program. Relying on a common cache for code and data leads to the "von Neumann bottleneck", a fundamental limitation on the throughput of software on processors implementing the von Neumann architecture. Even in the modified Harvard architecture, where instructions and data have separate caches in the memory hierarchy, there is overhead to decoding instruction opcodes and multiplexing available execution units on a microprocessor or microcontroller, leading to low circuit utilization. Modern processors that provide simultaneous multithreading exploit under-utilization of available processor functional units and instruction level parallelism between different hardware threads.

### Hardware execution units

Hardware execution units do not in general rely on the von Neumann or modified Harvard architectures and do not need to perform the instruction fetch and decode steps of an instruction cycle and incur those stages' overhead. If needed calculations are specified in a register transfer level (RTL) hardware design, the time and circuit area costs that would be incurred by instruction fetch and decoding stages can be reclaimed and put to other uses.

This reclamation saves time, power, and circuit area in computation. The reclaimed resources can be used for increased parallel computation, other functions, communication, or memory, as well as increased input/output capabilities. This comes at the cost of general-purpose utility.

### Emerging hardware architectures

Greater RTL customization of hardware designs allows emerging architectures such as in-memory computing, transport triggered architectures (TTA) and networks-on-chip (NoC) to further benefit from increased locality of data to execution context, thereby reducing computing and communication latency between modules and functional units.

Custom hardware is limited in parallel processing capability only by the area and logic blocks available on the integrated circuit die.[10] Therefore, hardware is much more free to offer massive parallelism than software on general-purpose processors, offering a possibility of implementing the parallel random-access machine (PRAM) model.

It is common to build multicore and manycore processing units out of microprocessor IP core schematics on a single FPGA or ASIC.[11][12][13][14][15] Similarly, specialized functional units can be composed in parallel, as in digital signal processing, without being embedded in a processor IP core. Therefore, hardware acceleration is often employed for repetitive, fixed tasks involving little conditional branching, especially on large amounts of data. This is how Nvidia's CUDA line of GPUs are implemented.

### Implementation metrics

As device mobility has increased, new metrics have been developed that measure the relative performance of specific acceleration protocols, considering characteristics such as physical hardware dimensions, power consumption, and operations throughput. These can be summarized into three categories: task efficiency, implementation efficiency, and flexibility. Appropriate metrics consider the area of the hardware along with both the corresponding operations throughput and energy consumed.[16]

## Applications

Examples of hardware acceleration include bit blit acceleration functionality in graphics processing units (GPUs), use of memristors for accelerating neural networks, and regular expression hardware acceleration for spam control in the server industry, intended to prevent regular expression denial of service (ReDoS) attacks.[17] The hardware that performs the acceleration may be part of a general-purpose CPU, or a separate unit called a hardware accelerator, though they are usually referred to with a more specific term, such as 3D accelerator, or cryptographic accelerator.

Traditionally, processors were sequential (instructions are executed one by one), and were designed to run general purpose algorithms controlled by instruction fetch (for example, moving temporary results to and from a register file). Hardware accelerators improve the execution of a specific algorithm by allowing greater concurrency, having specific datapaths for their temporary variables, and reducing the overhead of instruction control in the fetch-decode-execute cycle.

Modern processors are multi-core and often feature parallel "single-instruction; multiple data" (SIMD) units. Such units can be integrated withint the CPU or offered by additional components as the AMD AI engines.[18] Even so, hardware acceleration still yields benefits. Hardware acceleration is suitable for any computation-intensive algorithm which is executed frequently in a task or program. Depending upon the granularity, hardware acceleration can vary from a small functional unit, to a large functional block (like motion estimation in MPEG-2).

## Hardware acceleration units by application

Application  | Hardware accelerator  | Acronym

|
|

|  |
Computer graphics

* General-purpose computing
* GP computing, on Nvidia graphics cards
* Ray tracing
* Video codec

| Graphics processing unit

* General-purpose computing on GPU
* CUDA architecture
* Ray-tracing hardware

| GPU

* GPGPU
* CUDA
* RTX
* N/A

|  |
Digital signal processing | Digital signal processor | DSP
Analog signal processing | Field-programmable analog array

* Field-programmable RF

| FPAA

* FPRF

Image processing | Webcam or image processor | IPU
Sound processing | Sound card and sound card mixer  | N/A
Computer networking

* on a chip
* TCP
* Input/output

| Network processor and network interface controller

* Network on a chip
* TCP offload engine
* IPsec offload[19]
* I/O Acceleration Technology

| NPU and NIC

* NoC
* TCPOE or TOE
* I/OAT or IOAT

Cryptography

* Encryption
* ISA
* SSL/TLS
* Attack
* Random number generation

| Cryptographic accelerator and secure cryptoprocessor

* Hardware-based encryption
* AES instruction set
* SSL acceleration
* Custom hardware attack
* Hardware random number generator

| N/A
Artificial intelligence

* Machine vision/computer vision
* Neural networks
* Brain simulation

| AI accelerator

* Vision processing unit
* Physical neural network
* Neuromorphic engineering

| N/A

* VPU
* PNN
* N/A

Multilinear algebra | Tensor processing unit | TPU
Physics simulation | Physics processing unit | PPU
Regular expressions[17] | Regular expression coprocessor  | N/A
Data compression[20] | Data compression accelerator  | N/A
In-memory processing  | Network on a chip and Systolic array | NoC; N/A
Data processing | Data processing unit | DPU
Any computing task  | Computer hardware

* Field-programmable gate arrays[21]
* Application-specific integrated circuits[21]
* Complex programmable logic devices
* Systems-on-Chip
* Multi-processor system-on-chip
* Programmable system-on-chip

| HW (sometimes)

* FPGA
* ASIC
* CPLD
* SoC
* MPSoC
* PSoC

## See also

* Computer for operations with functions
* Coprocessor
* DirectX Video Acceleration (DXVA)
* Direct memory access (DMA)
* Flynn's taxonomy of parallel computer architectures
* Single instruction, multiple data (SIMD)
* Single instruction, multiple threads (SIMT)
* Multiple instructions, multiple data (MIMD)
* High-level synthesis
* C to HDL
* Flow to HDL
* Soft microprocessor
* Timeline of early 3D computer graphics hardware

## References

1. ↑ "Microsoft Supercharges Bing Search With Programmable Chips". WIRED. 16 June 2014. https://www.wired.com/2014/06/microsoft-fpga/.
2. ↑ "Embedded". http://www.embedded.com/columns/showArticle.jhtml?articleID=192700615. "FPGA Architectures from 'A' to 'Z'" by Clive Maxfield 2006
3. ↑ Sinan, Kufeoglu; Mahmut, Ozkuran (2019). "Figure 5. CPU, GPU, FPGA, and ASIC minimum energy consumption between difficulty recalculation.". Energy Consumption of Bitcoin Mining. doi:10.17863/CAM.41230. https://www.researchgate.net/figure/CPU-GPU-FPGA-and-ASIC-minimum-energy-consumption-between-difficulty-recalculation_fig5_337886683.
4. ↑ Kim, Yeongmin; Kong, Joonho; Munir, Arslan (2020). "CPU-Accelerator Co-Scheduling for CNN Acceleration at the Edge". IEEE Access 8: 211422–211433. doi:10.1109/ACCESS.2020.3039278. ISSN 2169-3536. Bibcode: 2020IEEEA...8u1422K.
5. ↑ Lin, Yibo; Jiang, Zixuan; Gu, Jiaqi; Li, Wuxi; Dhar, Shounak; Ren, Haoxing; Khailany, Brucek; Pan, David Z. (April 2021). "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40 (4): 748–761. doi:10.1109/TCAD.2020.3003843. ISSN 1937-4151. Bibcode: 2021ITCAD..40..748L.
6. ↑ Lyakhov, Pavel; Valueva, Maria; Valuev, Georgii; Nagornov, Nikolai (2020-12-18). "A Method of Increasing Digital Filter Performance Based on Truncated Multiply-Accumulate Units" (in en). Applied Sciences 10 (24): 9052. doi:10.3390/app10249052. ISSN 2076-3417. "Hardware simulation on FPGA increased the digital filter performance.".
7. ↑ Mohan, Prashanth; Wang, Wen; Jungk, Bernhard; Niederhagen, Ruben; Szefer, Jakub; Mai, Ken (October 2020). "ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS". 2020 IEEE 38th International Conference on Computer Design (ICCD). Hartford, CT, USA: IEEE. pp. 656–662. doi:10.1109/ICCD50377.2020.00112. ISBN 978-1-7281-9710-4.
8. ↑ Morgan, Timothy Pricket (2014-09-03). "How Microsoft Is Using FPGAs To Speed Up Bing Search". Enterprise Tech. https://www.enterprisetech.com/2014/09/03/microsoft-using-fpgas-speed-bing-search/.
9. ↑ "Project Catapult". https://www.microsoft.com/en-us/research/project/project-catapult/.
10. ↑ MicroBlaze Soft Processor: Frequently Asked Questions
11. ↑ Vassányi, István (1998). "Implementing processor arrays on FPGAs". Field-Programmable Logic and Applications from FPGAs to Computing Paradigm. Lecture Notes in Computer Science. 1482. pp. 446–450. doi:10.1007/BFb0055278. ISBN 978-3-540-64948-9. https://doi.org/10.1007/BFb0055278.
12. ↑ Zhoukun WANG and Omar HAMMAMI. "A 24 Processors System on Chip FPGA Design with Network on Chip". [1]
13. ↑ "John Kent. "Micro16 Array - A Simple CPU Array"". http://members.optusnet.com.au/jekent/Micro16Array/index.html.
14. ↑ Kit Eaton. "1,000 Core CPU Achieved: Your Future Desktop Will Be a Supercomputer". 2011. [2]
15. ↑ "Scientists Squeeze Over 1,000 Cores onto One Chip". 2011. [3]
16. ↑ Kienle, Frank; Wehn, Norbert; Meyr, Heinrich (December 2011). "On Complexity, Energy- and Implementation-Efficiency of Channel Decoders" (in en-US). IEEE Transactions on Communications 59 (12): 3301–3310. doi:10.1109/tcomm.2011.092011.100157. ISSN 0090-6778. Bibcode: 2011ITCom..59.3301K.
17. ↑ 17.0 17.1 "Regular Expressions in hardware". http://www.wellho.net/regex/hardware.html.
18. ↑ Rico, Alejandro; Pareek, Satyaprakash; Cabezas, Javier; Clarke, David; Ozgul, Baris; Barat, Francisco; Fu, Yao; Münz, Stephan et al. (2024-07-10). "AMD XDNA NPU in Ryzen AI Processors". IEEE Micro 44 (6): 73–82. doi:10.1109/MM.2024.3423692. ISSN 1937-4143. Bibcode: 2024IMicr..44f..73R.
19. ↑ "Intel® PRO/100 S Desktop Adapter Datasheet". Intel. 2005. https://www.intel.com/content/dam/doc/product-brief/intel-pro-100-s-desktop-adapter-datasheet.pdf.
20. ↑ "Compression Accelerators". Microsoft Research. 16 June 2014. https://www.microsoft.com/en-us/research/project/compression-accelerators/.
21. ↑ 21.0 21.1 Farabet, Clément (2010). "Hardware accelerated convolutional neural networks for synthetic vision systems". Proceedings of 2010 IEEE International Symposium on Circuits and Systems. Paris: IEEE. pp. 257-260. doi:10.1109/ISCAS.2010.5537908. https://www.academia.edu/15224562/Hardware_accelerated_convolutional_neural_networks_for_synthetic_vision_systems. Retrieved 15 August 2025.

## External links

* v
* t
* e

Hardware acceleration

Theory|

* Universal Turing machine
* Parallel computing
* Distributed computing

Applications|

* GPU
* GPGPU
* DirectX
* Audio
* Digital signal processing
* Hardware random number generation
* Artificial intelligence
* Cryptography
* TLS
* Machine vision
* Custom hardware attack
* scrypt
* Networking

Implementations|

* High-level synthesis
* C to HDL
* FPGA
* ASIC
* CPLD
* System on Chip
* Network on Chip

Architectures|

* Data flow
* Transport triggered
* Multicore
* Manycore
* Heterogeneous
* In-memory computing
* Systolic array
* Neuromorphic

Related|

* Programmable logic
* Processor
* design
* chronology
* Digital electronics
* Virtualization
* Hardware emulation
* Logic synthesis
* Embedded systems

* v
* t
* e

Graphics processing unit

GPU|

| Desktop|

* Intel
* GT
* Nvidia
* GeForce
* Quadro
* Tesla
* AMD
* Radeon
* Pro
* Instinct
* Matrox
* InfiniteReality
* µPD7220
* Voodoo

|

Mobile|

* Adreno
* Apple
* Mali
* PowerVR
* VideoCore

Architecture|

* Compute kernel
* Fabrication
* CMOS
* FinFET
* MOSFET
* Graphics pipeline
* Geometry
* Vertex
* HDR rendering
* MAC
* Rasterisation
* Shading
* Ray-tracing
* SIMD
* SIMT
* Tessellation
* T&L
* Tiled rendering
* Unified shader model

Components|

* Blitter
* Geometry processor
* Input–output memory management unit
* Render output unit
* Shader unit
* Stream processor
* Tensor unit
* Texture mapping unit
* Video display controller
* Video processing unit

Memory|

* DMA
* Framebuffer
* SGRAM
* GDDR
* GDDR3
* GDDR4
* GDDR5
* GDDR6
* HBM
* Memory bandwidth
* Memory controller
* Shared graphics memory
* Texture memory
* VRAM

Form factor|

* IP core
* Discrete graphics
* Clustering
* Switching
* External graphics
* Integrated graphics
* System on a chip

Performance|

* Clock rate
* Display resolution
* Fillrate
* Pixel/s
* Texel/s
* FLOP/s
* Frame rate
* Performance per watt
* Transistor count

Misc|

* 2D
* Scrolling
* Sprite
* Tile
* 3D
* GI
* Texture
* ASIC
* GPGPU
* Graphics library
* Hardware acceleration
* Image processing
* Compression
* Parallel computing
* Vector processor
* Video coding
* Codec
* VLIW

* v
* t
* e

Digital electronics

Components|

* Combinational logic
* Sequential logic
* Integrated circuit (IC)
* Logic gate

Theory|

* Digital signal
* Boolean algebra
* Logic synthesis
* Logic in computer science
* Computer architecture
* Digital signal
* Digital signal processing
* Circuit minimization
* Switching circuit theory

Design|

* Logic synthesis
* Place and route
* Placement
* Routing
* Register-transfer level
* Hardware description language
* High-level synthesis
* Formal equivalence checking
* Synchronous logic
* Asynchronous logic
* Finite-state machine
* Hierarchical state machine

Applications|

* Computer hardware
* Hardware acceleration
* Digital audio
* radio
* Digital photography
* Digital telephone
* Digital video
* cinema
* television
* Electronic literature

Design issues|

* Metastability
* Runt pulse

0.00

(0 votes)

Original source: https://en.wikipedia.org/wiki/Hardware acceleration. Read more

|

Retrieved from "https://handwiki.org/wiki/index.php?title=Hardware_acceleration&oldid=4349788"
*[v]: View this template
*[t]: Discuss this template
*[e]: Edit this template