Instruction window

An instruction window in computer architecture refers to the set of instructions which can execute out-of-order in a speculative processor. In particular, in a conventional design, the instruction window consists of all instructions which are in the re-order buffer (ROB).[1] In such a processor, any instruction within the instruction window can be executed when its operands are ready. Out-of-order processors derive their name because this may occur out-of-order (if operands to a younger instruction are ready before those of an older instruction).

The instruction window has a finite size, and new instructions can enter the window (usually called dispatch or allocate) only when other instructions leave the window (usually called retire or commit). Instructions enter and leave the instruction window in program order, and an instruction can only leave the window when it is the oldest instruction in the window, and it has been completed. Hence, the instruction window can be seen as a sliding window in which the instructions can become out-of-order. All execution within the window is speculative (i.e., side-effects are not applied outside the CPU) until it is committed in order to support asynchronous exception handling like interrupts.

This paradigm is also known as restricted dataflow[2] because instructions within the window execute in dataflow order (not necessarily in program order) but the window in which this occurs is restricted (of finite size).

The instruction window is distinct from pipelining: instructions in an in-order pipeline are not in an instruction window in the conventionally understood sense, because they cannot execute out of order with respect to one another. Out-of-order processors are usually built around pipelines, but many of the pipeline stages (e.g., front-end instruction fetch and decode stages) are not considered to be part of the instruction window.

## See also

* Superscalar processor

## References

1. ↑ Shen and Lipasti. Modern Processor Design: Fundamentals of Superscalar Processors. McGraw-Hill, 2005.
2. ↑ Patt et al., HPS, A New Microarchitecture: Rationale and Introduction. In IEEE International Symposium on Microarchitecture (MICRO), 1985.

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