Intel SHA extensions

Short description: Extensions to the x86 instruction set architecture

Intel SHA Extensions are a set of extensions to the x86 instruction set architecture which support hardware acceleration of Secure Hash Algorithm (SHA) family. It was introduced in 2013. Instructions for SHA-512 will be introduced in Arrow Lake and Lunar Lake in 2024.

The original SSE-based extensions added four instructions supporting SHA-1 and three for SHA-256. AVX-based versions are also available with a `V` prefix.

* SHA-1: `SHA1RNDS4`, `SHA1NEXTE`, `SHA1MSG1`, `SHA1MSG2`
* SHA-256: `SHA256RNDS2`, `SHA256MSG1`, `SHA256MSG2`

The AVX-based extensions added three for SHA-512.

* `VSHA512RNDS2`, `VSHA512MSG1`, `VSHA512MSG2`

## Contents

* 1 x86 architecture processors
* 1.1 Intel
* 1.2 AMD
* 2 References
* 3 External links

## x86 architecture processors

### Intel

The following Intel processors support the original SHA instruction set:

* Intel Goldmont (and later Atom microarchitectures) processors.[1]
* Intel Ice Lake (and later) processors.[2]
* Intel Rocket Lake (and later) processors.

The following Intel processors will support the newer SHA-512 instruction set:

* Intel Arrow Lake and Lunar Lake processors.

### AMD

Several AMD processors support the original SHA instruction set:

* AMD Zen (and later) processors.[3]

## References

1. ↑ "Goldmont - Microarchitectures - Intel - WikiChip" (in en). https://en.wikichip.org/wiki/intel/microarchitectures/goldmont.
2. ↑ "Ice Lake (client) - Microarchitectures - Intel - WikiChip" (in en). https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(client).
3. ↑ "Zen - Microarchitectures - AMD - WikiChip" (in en). https://en.wikichip.org/wiki/amd/microarchitectures/zen.

## External links

* New Instructions Supporting the Secure Hash Algorithm on Intel® Architecture Processors
* Intel Instruction Set Architecture Extensions
* "Intel Architecture Instruction Set Extensions Programming Reference". http://download-software.intel.com/sites/default/files/319433-015.pdf. , Chapter 8

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Intel

Subsidiaries|

* 3Dlabs
* Altera
* Intel Security
* Mobileye
* Recon Instruments
* Virtutech
* Wind River Systems

Joint ventures|

* 4Group Holdings (50% owned by Technicolor SA)
* McAfee (49%)

* v
* t
* e

Instruction set extensions

SIMD (RISC)|

* Alpha
* MVI
* ARM
* NEON
* SVE
* MIPS
* MDMX
* MIPS-3D
* MXU
* MIPS SIMD
* PA-RISC
* MAX
* Power ISA
* VMX
* SPARC
* VIS

SIMD (x86)|

* MMX (1996)
* 3DNow! (1998)
* SSE (1999)
* SSE2 (2001)
* SSE3 (2004)
* SSSE3 (2006)
* SSE4 (2006)
* SSE5 ~~(2007)~~
* AVX (2008)
* F16C (2009)
* XOP (2009)
* FMA (FMA4: 2011, FMA3: 2012)
* AVX2 (2013)
* AVX-512 (2015)

Bit manipulation|

* BMI (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)
* ADX (2014)

Compressed instructions|

* Thumb
* MIPS16e ASE

Security and cryptography|

* AES-NI (2008); 32- and 64-bit ARMv8 also has AES instructions
* CLMUL (2010)
* RDRAND (2012)
* SHA (2013)
* MPX (2015)
* SGX (2015)

Transactional memory|

* TSX (2013)
* ASF

Virtualization|

* VT-x (2005)
* AMD-V (2006)

Suspended extensions' dates have been ~~struck through~~.

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