Maia (verification language)

Maia is a hardware verification language. Maia source code is transcompiled into Verilog, and the output forms a complete self-checking testbench for a DUT. The output may be run directly on a Verilog simulator (which supports IEEE 1364-2005), either under the simulator GUI, or as a stand-alone batch-mode simulation. Maia can be used to test both Verilog and VHDL designs (a dual-language simulator is required if the DUT includes any VHDL code).

Maia is generally used to implement automated regression and unit testing.

Maia programs contain a DUT section, together with a procedural section which implements the test algorithms. The DUT section declares the interface to the device to be tested, together with declarations of any required clocks, timing parameters, and 'drive statements'. The interface declaration is normally a cut-and-paste of the DUT's top-level module declaration, but can also declare internal DUT signals which are to be tested.

The procedural section is designed to be familiar to anyone who has experience of C or related languages. The primary differences from C include:

* A type system which uses explicitly-sized `bit` (2-state), `var` (4-state), and unconstrained variables
* Additional hardware-related operators to handle bitslices, attributes, rotates, and so on
* Operators which are explicitly sized, and which carry out sign-extension, if necessary
* Constructs which handle concurrency, advancing time, and DUT access
* Parameters may be passed by reference; there is no pointer support

The DUT section is optional, and can be omitted if a program is used simply for algorithm development. The additional operators are designed specifically to simplify the modelling of complex hardware algorithms which may require the combination of multiple variables of different sizes.

Self-checking testbenches are implemented primarily through the use of drive statements, which are of the form:

` [ei1, ei2, .., ein] ->p [eo1, eo2, .., eom] `

where eij are 'input' expressions, eok are 'output' expressions, and p is an optional pipeline level. The input expressions are applied to the DUT inputs, while the device outputs are compared (at some later time) against the output expressions. If timing parameters are present in the DUT section, the relevant signals are driven with worst-case timing, or tested during the relevant stability window. The language automatically maintains records of passed and failed tests, and reports them on test termination.

Maia was developed in the early 2000s, and has gone through a number of iterations during development. It has been used for the verification of a large number of FPGA and ASIC devices. The current stable release is 2019.11. A free compiler can be downloaded from the Official website.

## External links

Official website

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