Statistical static timing analysis

Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. This has led to considerable research into statistical static timing analysis, which replaces the normal deterministic timing of gates and interconnects with probability distributions, and gives a distribution of possible circuit outcomes rather than a single outcome.

## Contents

* 1 Comparison with conventional STA
* 2 Methods
* 3 Criticism
* 4 Tools that perform static timing analysis
* 5 See also
* 6 References

## Comparison with conventional STA

Deterministic STA is popular for good reasons:

* It requires no vectors, so it does not miss paths.
* The run time is linear in circuit size (for the basic algorithm).
* The result is conservative.
* It typically uses some fairly simple libraries (typically delay and output slope as a function of input slope and output load).
* It is easy to extend to incremental operation for use in optimization.

STA, while very successful, has a number of limitations:

* Cannot easily handle within-die correlation, especially if spatial correlation is included.
* Needs many corners to handle all possible cases.
* If there are significant random variations, then in order to be conservative at all times, it is too pessimistic to result in competitive products.
* Changes to address various correlation problems, such as CPPR (Common Path Pessimism Removal) make the basic algorithm slower than linear time, or non-incremental, or both.

SSTA attacks these limitations more or less directly. First, SSTA uses sensitivities to find correlations among delays. Then it uses these correlations when computing how to add statistical distributions of delays.

There is no technical reason why determistic STA could not be enhanced to handle correlation and sensitivities, by keeping a vector of sensitivities with each value as SSTA does. Historically, this seemed like a big burden to add to STA, whereas it was clear it was needed for SSTA, so no-one complained. See some of the criticism of SSTA below where this alternative is proposed.

## Methods

There are two main categories of SSTA algorithms – path-based and block-based methods.

A path-based algorithm[1] sums gate and wire delays on specific paths. The statistical calculation is simple, but the paths of interest must be identified prior to running the analysis. There is the potential that some other paths may be relevant but not analyzed so path selection is important.

A block-based algorithm[2] generates the arrival times (and required) times for each node, working forward (and backward) from the clocked elements. The advantage is completeness, and no need for path selection. The biggest problem is that a statistical max (or min) operation that also considered correlation is needed, which is a hard technical problem.

There are SSTA cell characterization tools that are now available such as Altos Design Automation's Variety tool.

## Criticism

A number of criticisms have been leveled at SSTA:

* It's too complex, especially with realistic (non-gaussian) distributions.
* It's hard to couple to an optimization flow or algorithm.
* It's hard to get the data the algorithm needs. Even if you can get this data, it is likely to be time-varying and hence unreliable.
* If used seriously by the customers of a fab, it restricts the changes the fab might make, if they change that statistical properties of the process.
* The benefit is relatively small, compared to an enhanced deterministic STA that also takes into account sensitivities and correlation.[3]

## Tools that perform static timing analysis

FPGAs

* Altera Quartus II
* Xilinx ISE

ASICs

* Synopsys Primetime (Synopsys PrimeTime)
* Cadence Encounter Timing System (Cadence Tempus)
* IBM EinsTimer
* ANSYS Path FX (ANSYS Path FX)

## See also

* Static timing analysis

## References

1. ↑ Orshansky, M.; Keutzer, K., 2002, A general probabilistic framework for worst case timing analysis, Design Automation Conference, 2002. Proceedings. 39th, Vol., Iss., 2002, Pages: 556-561.
2. ↑ Visweswariah, C.; Ravindran, K.; Kalafala, K.; Walker, S.G.; Narayan, S.; Beece, D.K.; Piaget, J.; Venkateswaran, N.; Hemmett, J.G., 2006, First-Order Incremental Block-Based Statistical Timing Analysis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.25, Iss.10, Oct. 2006, Pages: 2170-2180
3. ↑ Noel Menezes. "The Good, the Bad, and the Statistical". ISPD 2007. http://www.ispd.cc/slides/archives/ispd2007/slides07/noel.pdf.

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