VAX

Short description: Line of computers sold by Digital Equipment Corporation

VAX

Designer| Digital Equipment Corporation
Bits| 32-bit
Introduced| 1977; 47 years ago (1977)
Design| CISC
Type| Register-Register
Register-Memory
Memory-Memory
Encoding| Variable (1 to 56 bytes)
Branching| Condition code
Endianness| Little
Page size| 512 bytes
Extensions| PDP-11 compatibility mode, VAX Vector Extensions,[1] VAX Virtualization Extensions[2]
Open| No
Predecessor| PDP-11
Successor| Alpha
Registers
General purpose| 16 × 32-bit
Floating point| not present, uses the GPR
Vector| 16 × 4096-bit (512 bytes)

VAX (an acronym for Virtual Address eXtension) is a series of computers featuring a 32-bit instruction set architecture (ISA) and virtual memory that was developed and sold by Digital Equipment Corporation (DEC) in the late 20th century. The VAX-11/780, introduced October 25, 1977, was the first of a range of popular and influential computers implementing the VAX ISA. The VAX family was a huge success for DEC - over 100 models were introduced over the lifetime of the design,[citation needed] with the last members arriving in the early 1990s. The VAX was succeeded by the DEC Alpha, which included several features from VAX machines to make porting from the VAX easier.

VAX was designed as a successor to the 16-bit PDP-11, one of the most successful minicomputers in history with approximately 600,000 examples sold. The system was designed to offer backward compatibility with the PDP-11 while extending the memory to a full 32-bit implementation and adding demand paged virtual memory. The name VAX refers to its Virtual Address eXtension concept that allowed programs to make use of this newly available memory while still being compatible with unmodified user mode PDP-11 code. The name "VAX-11", used on early models, was chosen to highlight this capability. The VAX ISA is considered a complex instruction set computer (CISC) design.

Later models in the series dropped the -11 branding as PDP-11 compatibility was no longer a major concern. The line expanded to both high-end machines like the VAX 9000 as well as to the workstation-scale systems like the VAXstation series. The VAX family ultimately contained ten distinct designs and over 100 individual models in total. All of these were compatible with each other and normally ran the VAX/VMS operating system.

VAX has been perceived as the quintessential CISC ISA,[3] with its very large number of assembly language programmer-friendly addressing modes and machine instructions, highly orthogonal instruction set architecture, and instructions for complex operations such as queue insertion or deletion, number formatting, and polynomial evaluation.[4]

## Contents

* 1 Name
* 2 Instruction set
* 3 Operating systems
* 4 History
* 5 Processor architecture
* 5.1 Virtual memory map
* 5.2 Privilege modes
* 5.3 Processor status longword
* 6 VAX-based systems
* 6.1 SImultaneous Machine ACceSs (SIMACS)
* 6.2 Canceled systems
* 6.3 Clones
* 7 Further reading
* 8 References
* 9 External links

## Name

VAX-11/780

The name "VAX" originated as an acronym for Virtual Address eXtension, both because the VAX was seen as a 32-bit extension of the older 16-bit PDP-11 and because it was (after Prime Computer) an early adopter of virtual memory to manage this larger address space.

Early versions of the VAX processor implement a "compatibility mode" that emulates many of the PDP-11's instructions, giving it the 11 in VAX-11 to highlight this compatibility. Later versions offloaded the compatibility mode and some of the less used CISC instructions to emulation in the operating system software.

## Instruction set

The VAX instruction set was designed to be powerful and orthogonal.[5] When it was introduced, many programs were written in assembly language, so having a "programmer-friendly" instruction set was important.[6][7] In time, as more programs were written in high-level programming languages, the instruction set became less visible, and the only ones much concerned about it were compiler writers.

One unusual aspect of the VAX instruction set is the presence of register masks[8] at the start of each subprogram.[5] These are arbitrary bit patterns that specify, when control is passed to the subprogram, which registers are to be preserved. Since register masks are a form of data embedded within the executable code, they can make linear parsing of the machine code difficult. This can complicate optimization techniques that are applied on machine code.[9]

## Operating systems

Stylized "VAX/VMS" used by Digital

The native VAX operating system is Digital's VAX/VMS (renamed to OpenVMS in 1991 or early 1992 when it was ported to Alpha, modified to comply with POSIX standards, and branded as compliant with XPG4 by the X/Open consortium).[10] The VAX architecture and VMS operating system were "engineered concurrently" to take maximum advantage of each other, as was the initial implementation of the VAXcluster facility.

During the 1980s, a hypervisor for the VAX architecture named VMM (Virtual Machine Monitor), also known as the VAX Security Kernel, was developed at Digital with the aim of allowing multiple isolated instances of VMS and ULTRIX to be run on the same hardware.[11] VMM was intended to achieve TCSEC A1 compliance. By the late 1980s, it was operational on VAX 8000 series hardware, but was abandoned before release to customers.

Other VAX operating systems have included various releases of Berkeley Software Distribution (BSD) UNIX up to 4.3BSD, Ultrix-32, VAXELN, and Xinu. More recently, NetBSD[12] and OpenBSD[13] have supported various VAX models and some work has been done on porting Linux to the VAX architecture.[14] OpenBSD discontinued support for the architecture in September 2016.[15]

## History

VAX 8350 front view with cover removed

The first VAX model sold was the VAX-11/780, which was introduced on October 25, 1977, at the Digital Equipment Corporation's Annual Meeting of Shareholders.[16] Bill Strecker, C. Gordon Bell's doctoral student at Carnegie Mellon University, was responsible for the architecture.[17] Many different models with different prices, performance levels, and capacities were subsequently created. VAX superminicomputers were very popular in the early 1980s.

For a while the VAX-11/780 was used as a standard in CPU benchmarks. It was initially described as a one-MIPS machine, because its performance was equivalent to an IBM System/360 that ran at one MIPS, and the System/360 implementations had previously been de facto performance standards. The actual number of instructions executed in 1 second was about 500,000, which led to complaints of marketing exaggeration. The result was the definition of a "VAX MIPS," the speed of a VAX-11/780; a computer performing at 27 VAX MIPS would run the same program roughly 27 times faster than the VAX-11/780.

Within the Digital community the term VUP (VAX Unit of Performance) was the more common term, because MIPS do not compare well across different architectures. The related term cluster VUPs was informally used to describe the aggregate performance of a VAXcluster. (The performance of the VAX-11/780 still serves as the baseline metric in the BRL-CAD Benchmark, a performance analysis suite included in the BRL-CAD solid modeling software distribution.) The VAX-11/780 included a subordinate stand-alone LSI-11 computer that performed microcode load, booting, and diagnostic functions for the parent computer. This was dropped from subsequent VAX models. Enterprising VAX-11/780 users could therefore run three different Digital Equipment Corporation operating systems: VMS on the VAX processor (from the hard drives), and either RSX-11S or RT-11 on the LSI-11 (from the single density single drive floppy disk).

The VAX went through many different implementations. The original VAX 11/780 was implemented in TTL and filled a four-by-five-foot cabinet[18] with a single CPU. Through the 1980s, the high-end of the family was continually improved using ever-faster discrete components, an evolution that ended with the introduction of the VAX 9000 in October 1989. This design proved too complex and expensive and was ultimately abandoned not long after introduction. CPU implementations that consisted of multiple emitter-coupled logic (ECL) gate array or macrocell array chips included the VAX 8600 and 8800 superminis and finally the VAX 9000 mainframe class machines. CPU implementations that consisted of multiple MOSFET custom chips included the 8100 and 8200 class machines. The VAX 11-730 and 725 low-end machines were built using AMD Am2901 bit-slice components for the ALU.

The MicroVAX I represented a major transition within the VAX family. At the time of its design, it was not yet possible to implement the full VAX architecture as a single VLSI chip (or even a few VLSI chips as was later done with the V-11 CPU of the VAX 8200/8300). Instead, the MicroVAX I was the first VAX implementation to move some of the more complex VAX instructions (such as the packed decimal and related opcodes) into emulation software. This partitioning substantially reduced the amount of microcode required and was referred to as the "MicroVAX" architecture. In the MicroVAX I, the ALU and registers were implemented as a single gate-array chip while the rest of the machine control was conventional logic.

A full VLSI (microprocessor) implementation of the MicroVAX architecture arrived with the MicroVAX II's 78032 (or DC333) CPU and 78132 (DC335) FPU. The 78032 was the first microprocessor with an on-board memory management unit[19] The MicroVAX II was based on a single, quad-sized processor board which carried the processor chips and ran the MicroVMS or Ultrix-32 operating systems. The machine featured 1 MB of on-board memory and a Q22-bus interface with DMA transfers. The MicroVAX II was succeeded by many further MicroVAX models with much improved performance and memory.

Further VLSI VAX processors followed in the form of the V-11, CVAX, CVAX SOC ("System On Chip", a single-chip CVAX), Rigel, Mariah and NVAX implementations. The VAX microprocessors extended the architecture to inexpensive workstations and later also supplanted the high-end VAX models. This wide range of platforms (mainframe to workstation) using one architecture was unique in the computer industry at that time. Sundry graphics were etched onto the CVAX microprocessor die. The phrase CVAX... when you care enough to steal the very best was etched in broken Russian as a play on a Hallmark Cards slogan, intended as a message to Soviet engineers who were known to be both purloining DEC computers for military applications and reverse engineering their chip design.[20][21] By the late 1980s, the VAX microprocessors had grown in power to be competitive with discrete designs. This led to the abandonment of the 8000 and 9000 series and their replacement by Rigel-powered models of the VAX 6000, and later by NVAX-powered VAX 7000 systems.

In DEC's product offerings, the VAX architecture was eventually superseded by RISC technology. In 1989 DEC introduced a range of workstations and servers that ran Ultrix, the DECstation and DECsystem respectively, based on processors that implemented the MIPS architecture. In 1992 DEC introduced their own RISC instruction set architecture, the Alpha AXP (later renamed Alpha), and their own Alpha-based microprocessor, the DECchip 21064, a high performance 64-bit design capable of running OpenVMS.

In August 2000, Compaq announced that the remaining VAX models would be discontinued by the end of the year,[22] but old systems remain in widespread use.[23] The Stromasys CHARON-VAX and SIMH software-based VAX emulators remain available. VMS is now developed by VMS Software Incorporated, albeit only for the Alpha, HPE Integrity, and x86-64 platforms.

## Processor architecture

MicroVAX 3600 (left) with printer (right)

DEC VAX registers

| 31 | ...  | 23 | ...  | 15 | ...  | 07 | ...  | 00 | (bit position)

|
|
|
|
|
|
|
|
|

General registers
R0  | Register 0
R1  | Register 1
R2  | Register 2
R3  | Register 3
R4  | Register 4
R5  | Register 5
R6  | Register 6
R7  | Register 7
R8  | Register 8
R9  | Register 9
R10  | Register 10
R11  | Register 11
R12 / AP  | Register 12 / Argument Pointer
R13 / FP  | Register 13 / Frame Pointer
R14 / SP  | Register 14 / Stack Pointer
R15 / PC  | Register 15 / Program Counter
Processor Status Longword
(See adjacent table for bit definitions)  | PSL

### Virtual memory map

The VAX virtual memory is divided into four sections. Each is one gigabyte (in the context of addressing, 230 bytes) in size:

Section  | Address Range

|

P0  | `0x00000000` \- `0x3fffffff`
P1  | `0x40000000` \- `0x7fffffff`
S0  | `0x80000000` \- `0xbfffffff`
S1  | `0xc0000000` \- `0xffffffff`

For VMS, P0 was used for user process space, P1 for process stack, S0 for the operating system, and S1 was reserved.

### Privilege modes

The VAX has four hardware implemented privilege modes:

No.  | Mode  | VMS use  | Notes

|
|
|

0  | Kernel  | OS kernel  | Highest privilege level
1  | Executive  | File system |
2  | Supervisor  | Shell (DCL)  |
3  | User  | Normal programs  | Lowest privilege level

### Processor status longword

The Process Status Longword contains 32 bits:

CM  | TP  | MBZ  | FD  | IS  | cmod  | pmod  | MBZ  | IPL  | MBZ  | DV  | FU  | IV  | T  | N  | Z  | V  | C

|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|

31  | 30  | 29  | 27  | 26  | 25  | 23  | 21  | 20  | 15  | 7  | 6  | 5  | 4  | 3  | 2  | 1  | 0
Bits  | Meaning

|

31  | PDP-11 compatibility mode
30  | trace pending
29:28  | MBZ (must be zero)
27  | first part done (interrupted instruction)
26  | interrupt stack
25:24  | current privilege mode
23:22  | previous privilege mode
21  | MBZ (must be zero)
20:16  | IPL (interrupt priority level)
15:8  | MBZ (must be zero)
7  | decimal overflow trap enable
6  | floating-point underflow trap enable
5  | integer overflow trap enable
4  | trace
3  | negative
2  | zero
1  | overflow
0  | carry

The SPEC-1 VAX, a VAX 11/780 used for benchmarking, showing internals

## VAX-based systems

The first VAX-based system was the VAX-11/780, a member of the VAX-11 family. The high-end VAX 8600 replaced the VAX-11/780 in October 1984 and was joined by the entry-level MicroVAX minicomputers and the VAXstation workstations in the mid-1980s. The MicroVAX was superseded by the VAX 4000, the VAX 8000 was superseded by the VAX 6000 in the late 1980s and the mainframe-class VAX 9000 was introduced. In the early 1990s, the fault-tolerant VAXft was introduced, as were the Alpha compatible VAX 7000/10000. A variant of various VAX-based systems were sold as the VAXserver.

### SImultaneous Machine ACceSs (SIMACS)

System Industries developed an ability to give more than one DEC CPU, but not at the same time, write access to a shared disk. They implemented an enhancement named SImultaneous Machine ACceSs (SIMACS),[24][25] which allowed their special disk controller to set a semaphore flag for disk access, allowing multiple WRITES to the same files; the disk is shared by multiple DEC systems. SIMACS also existed on PDP-11 RSTS systems.

### Canceled systems

Canceled systems include the BVAX, a high-end emitter-coupled logic (ECL) based VAX, and two other ECL-based VAX models: Argonaut and Raven.[26] Raven was canceled in 1990.[27] A VAX named Gemini was also canceled, which was a fall-back in case the LSI-based Scorpio failed. It never shipped.

### Clones

A number of VAX clones, both authorized and unauthorized, were produced. Examples include:

* Systime Computers Ltd of the United Kingdom produced clones of early VAX models such as the Systime 8750 (equivalent to the VAX 11/750).[28]
* Norden Systems produced the ruggedized, Military-specification MIL VAX series.[10]
* The Hungarian Central Research Institute for Physics (KFKI) produced a series of clones of early VAX models, the TPA-11/540, 560 and 580.[29]
* The SM 52/12[30] from Czechoslovakia, developed at VUVT Žilina (today Slovakia) and produced from 1986 at ZVT Banská Bystrica (today Slovakia).
* The East German VEB Robotron K 1840 (SM 1710) is a clone of the VAX-11/780 and Robotron K 1820 (SM 1720) is a copy of the MicroVAX II.
* The SM-1700 is a Soviet clone of the VAX-11/730, SM-1702 was a clone of MicroVAX II and SM-1705 was a clone of VAX-11/785.[31] These systems ran a variety of clone operating systems - DEMOS (based on BSD Unix), MOS VP (based on VAX/VMS) or MOS VP RV (based on VAXELN).[32]
* The NCI-2780 Super-mini, also sold as Taiji-2780, is a clone of the VAX-11/780 developed by North China Institute of Computing Technology in Beijing.[33][34]

## Further reading

* Coy, Peter (6 January 2021). "Who Remembers the VAX Minicomputer, Icon of the 1980s?" (in en). Bloomberg News. https://www.bloomberg.com/news/articles/2021-01-06/who-remembers-the-vax-minicomputer-icon-of-the-1980s.

## References

1. ↑ "VAX MACRO and Instruction Set Reference Manual". OpenVMS documentation. April 2001. 8.1 Basic Architecture. http://www.openvms.compaq.com/doc/73final/4515/4515pro_012.html#basic_arch_sect.
2. ↑ DEC STD 032 - VAX Architecture Standard. Digital Equipment Corp. 1990-01-05. p. 12-5. http://www.bitsavers.org/pdf/dec/vax/archSpec/EL-00032-00-decStd32_Jan90.pdf. Retrieved 2022-08-01.
3. ↑ Bistriceanu, Virgil. "Computer Architecture - Class notes". Illinois Institute of Technology. http://www.cs.iit.edu/~virgil/cs470/Book/chapter3.pdf.
4. ↑ Payne, Mary; Bhandarkar, Dileep (1980). "VAX floating point: a solid foundation for numerical computation". SIGARCH Computer Architecture News (ACM) 8 (4): 22–33. doi:10.1145/641845.641849. ISSN 0163-5964.
5. ↑ 5.0 5.1 Levy, Henry; Eckhouse, Richard (June 28, 2014) (in en). Computer Programming and Architecture: The Vax. Digital Press. ISBN 9781483299372. https://books.google.com/books?id=3LijBQAAQBAJ.
6. ↑ "Another Approach to Instruction Set Architecture—VAX". http://www.weblearn.hs-bremen.de/risse/RST/docs/COD2e/WebExtns.ion/webext3.pdf. "... instruction set architectures, we chose the VAX as programmer-friendly instruction set, an asset"
7. ↑ "VAX". http://www.lysator.liu.se/hackdict/split/vax.html. "Esp. noted for its large, assembler-programmer-friendly instruction set 
 an asset that"
8. ↑ "VAX MACRO and Instruction Set Reference Manual". OpenVMS documentation. April 2001. 9.2.5 Procedure Call Instructions. http://www.openvms.compaq.com/doc/73final/4515/4515pro_020.html#index_x_790.
9. ↑ Goss, Clinton F. (August 2013) [First published June 1986]. Machine Code Optimization: Improving Executable Object Code (PDF) (PhD). Computer Science Department Technical Report #246. Courant Institute, New York University. arXiv:1308.4815. Bibcode:2013arXiv1308.4815G. Retrieved August 22, 2013.
* Clinton F. Goss (2013) [1986]. Machine Code Optimization - Improving Executable Object Code (PhD thesis). Courant Institute, New York University.
10. ↑ 10.0 10.1 Rainville, Jim; Howard, Karen, eds (1997). "VAX/VMS at 20". Digital Equipment Corporation. http://h41379.www4.hpe.com/openvms/20th/.
11. ↑ Paul A. Karger; Mary Ellen Zurko; Douglas W. Benin; Andrew H. Mason; Clifford E. Kahnh (7–9 May 1990). "A VMM security kernel for the VAX architecture". Proceedings. 1990 IEEE Computer Society Symposium on Research in Security and Privacy. IEEE. doi:10.1109/RISP.1990.63834. https://www.scs.stanford.edu/nyu/04fa/sched/readings/vmm.pdf. Retrieved 2021-01-31.
12. ↑ "NetBSD/vax". http://wiki.netbsd.org/ports/vax/.
13. ↑ "OpenBSD/vax". http://www.openbsd.org/vax.html.
14. ↑ "Porting Linux to the VAX". http://vax-linux.org.
15. ↑ "OpenBSD 6.0". 2016. https://www.openbsd.org/60.html.
16. ↑ "VAX 11/780, The First VAX System (October 1977)". https://www.old-computers.com/history/detail.asp?n=20&t=3.
17. ↑ Slater, Robert (1987). Portraits in Silicon. MIT Press. p. 213. ISBN 978-0-262-69131-4. https://books.google.com/books?id=aWTtMyYmKhUC&q="Bill+Strecker"+vax+designer.
18. ↑ "VAX 11/780 Computer: CPU". Computer History Museum. http://www.computerhistory.org/revolution/mainframe-computers/7/182/736.
19. ↑ The Computer History Simulation Project: MicroVAX II (1985)
20. ↑ micro.magnet.fsu.edu, Steal the best, retrieved January 30, 2008. The Russian phrase was: СВАКС... Когда вы забатите довольно воровать настоящий лучший
21. ↑ The Computer History Simulation Project: CVAX (1987), retrieved January 30, 2008
22. ↑ "VAX Systems: A letter from Jesse Lipcon". http://www.compaq.com/alphaserver/vax/vax_letter_final.html.
23. ↑ "If It Ain't Broke, Don't Fix It: Ancient Computers in Use Today". https://www.pcworld.com/article/468250/if-it-aint-broke-dont-fix-it-ancient-computers-in-use-today.html.
24. ↑ Wand, R.; Kesteven, M.; Rayner, P. (February 24, 1984). "Computing Requirements for AT Software Development". http://www.atnf.csiro.au/observers/memos/d95f80~1.pdf.
25. ↑ Joshi, Prem; Delacroix, Jacques (September 1984). "New Flexibility For Multiple VAX/VMS". HARDCOPY: 64–68.
26. ↑ Mark Smotherman (July 19, 2008). "Who are the Computer Architects?". http://www.cs.clemson.edu/~mark/architects.html.
27. ↑ Supnik, Bob (2007). "Raven". http://simh.trailing-edge.com/semi/raven.html.
28. ↑ "RAL Informatics Report 1984-85". http://www.chilton-computing.org.uk/inf/literature/inf_reports/p001.htm.
29. ↑ "The TPA story". http://hampage.hu/tpa/e_index.html.
30. ↑ Dujnic, J.; Fristacky, N.; Molnar, L.; Plander, I.; Rovan, B. (1999). "On the history of computer science, computer engineering, and computer technology development in Slovakia". IEEE Annals of the History of Computing 21 (3): 38–48. doi:10.1109/85.778981.
31. ↑ Laimutis Telksnys; Antanas Zilinskas (July 1999). "Computers in Lithuania". IEEE Annals of the History of Computing 21 (3): 31–37. doi:10.1109/85.778980. http://www.computer.org/csdl/mags/an/1999/03/00778980.pdf.
32. ↑ Prokhorov N.L.; Gorskiy V.E.. "Basic software for 32-bit SM computer models" (in Russian). Software Systems Journal 1988 (3). http://www.swsys.ru/index.php?page=article&id=1480#. Retrieved 2021-09-15.
33. ↑ U.S. Congress, Office of Technology Assessment (July 1987). Technology transfer to China. U.S. Government Printing Office. p. 96. OTA-USC-340. ISBN 9781428922914. https://books.google.com/books?id=E0LoOH-GqagC&q="NCI-2780"&pg=PA96.
34. ↑ Xia Nanyin; Chan Laixing (1990). "Satellite Launch and TT&C Systems of China and Their Roles in International Cooperation". Space Commercialization: Launch Vehicles and Programs. American Institute of Aeronautics and Astronautics. p. 244. ISBN 0-930403-75-4. https://books.google.com/books?id=u7HItO03SlwC&q="NCI-2780"&pg=PA244.

## External links

* HP: VAX Systems
* DEC Microprocessors
* SimH VAX Open source emulator that supports VAX architecture
* The complete Digital Technical Journals

* v
* t
* e

Digital Equipment Corporation computers

PDP|

| 18-bit|

* PDP-1
* PDP-4
* PDP-7
* PDP-9
* PDP-15

|

12-bit|

* LINC
* PDP-5
* PDP-8
* PDP-12
* LINC-8
* DECmate
* PDP-14 PLC

| 36-bit|

* PDP-6
* PDP-10
* DECSYSTEM-20

|

16-bit|

* PDP-11
* DEC Professional

VAX|

* VAX-11
* MicroVAX
* VAX 8000
* VAXstation
* Firefly
* VAXserver
* VAX 6000
* VAX 4000
* VAX 9000
* VAXft
* VAX 7000/10000

x86|

* Rainbow 100
* VAXmate
* DECstation
* Multia
* Digital Personal Workstation

MIPS|

* DECstation
* DECsystem (see "36-bit" for DECSYSTEM-20 and the PDP-10/DECsystem-10))

Alpha|

* DEC 3000 AXP
* DEC 4000 AXP
* DEC 7000/10000 AXP
* DECpc AXP 150
* DEC 2000 AXP
* Multia
* AlphaServer
* AlphaStation
* Digital Personal Workstation

* v
* t
* e

Processor technologies

Models|

* Turing machine
* Universal
* Post–Turing
* Quantum
* Belt machine
* Stack machine
* Finite-state machine
* with datapath
* Hierarchical
* Queue automaton
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load/store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* comparison
* addressing modes

|

* x86
* ARM
* MIPS
* Power ISA
* SPARC
* Itanium
* Unicore
* MicroBlaze
* RISC-V
* others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Tomasulo algorithm
* Reservation station
* Re-order buffer
* Register renaming

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* SWAR
* SIMT
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Coprocessor
* ASIC
* FPGA
* CPLD
* Multi-chip module (MCM)
* System in package (SiP)

| By application|

* Microprocessor
* Microcontroller
* Mobile
* Notebook
* Ultra-low-voltage
* ASIP

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Programmable (PSoC)
* Network on a chip (NoC)

Hardware
accelerators|

* AI accelerator
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor processing unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 2-bit
* 4-bit
* 8-bit
* 16-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Integrated memory controller (IMC)

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Program counter

Control unit|

* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)
* Race to sleep

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model

0.00

(0 votes)

|

Retrieved from "https://handwiki.org/wiki/index.php?title=VAX&oldid=2624617"
*[v]: View this template
*[t]: Discuss this template
*[e]: Edit this template