Addressing mode

Aspect of the instruction set architecture of CPUs

This article is about addressing fields in instructions. For IBM addressing bits in the PSW, see IBM System/370-XA § 31-bit virtual addressing, and z/Architecture § Addressing modes.

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Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions in that architecture identify the operand(s) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

In computer programming, addressing modes are primarily of interest to those who write in assembly languages and to compiler writers. For a related concept see orthogonal instruction set which deals with the ability of any instruction to use any addressing mode.

## Caveats

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There are no generally accepted names for addressing modes: different authors and computer manufacturers may give different names to the same addressing mode, or the same names to different addressing modes. Furthermore, an addressing mode which, in one given architecture, is treated as a single addressing mode may represent functionality that, in another architecture, is covered by two or more addressing modes. For example, some complex instruction set computer (CISC) architectures, such as the Digital Equipment Corporation (DEC) VAX, treat registers and literal or immediate constants as just another addressing mode. Others, such as the IBM System/360 and its successors, and most reduced instruction set computer (RISC) designs, encode this information within the instruction. Thus, the latter machines have three distinct instruction codes for copying one register to another, copying a literal constant into a register, and copying the contents of a memory location into a register, while the VAX has only a single "MOV" instruction.

The term "addressing mode" is itself subject to different interpretations: either "memory address calculation mode" or "operand accessing mode". Under the first interpretation, instructions that do not read from memory or write to memory (such as "add literal to register") are considered not to have an "addressing mode". The second interpretation allows for machines such as VAX which use operand mode bits to allow for a register or for a literal operand. Only the first interpretation applies to instructions such as "load effective address," which loads the address of the operand, not the operand itself.

The addressing modes listed below are divided into code addressing and data addressing. Most computer architectures maintain this distinction, but there are (or have been) some architectures which allow (almost) all addressing modes to be used in any context.

The instructions shown below are purely representative in order to illustrate the addressing modes, and do not necessarily reflect the mnemonics used by any particular computer.

Some computers, e.g., IBM 709, RCA 3301,[1] do not have a single address mode field but rather have separate fields for indirect addressing and indexing.

## Number of addressing modes

[edit]

Computer architectures vary greatly as to the number of addressing modes they provide in hardware. There are some benefits to eliminating complex addressing modes and using only one or a few simpler addressing modes, even though it requires a few extra instructions, and perhaps an extra register.[2][3] It has proven[4][5][6] much easier to design pipelined CPUs if the only addressing modes available are simple ones.

Most RISC architectures have only about five simple addressing modes, while CISC architectures such as the DEC VAX have over a dozen addressing modes, some of which are quite complicated. The IBM System/360 architecture has only four addressing modes; a few more have been added for the ESA/390 architecture.

When there are only a few addressing modes, the particular addressing mode required is usually encoded within the instruction code (e.g. IBM System/360 and successors, most RISC). But when there are many addressing modes, a specific field is often set aside in the instruction to specify the addressing mode. The DEC VAX allowed multiple memory operands for almost all instructions, and so reserved the first few bits of each operand specifier to indicate the addressing mode for that particular operand. Keeping the addressing mode specifier bits separate from the opcode operation bits produces an orthogonal instruction set.

Even on a computer with many addressing modes, measurements of actual programs[7] indicate that the simple addressing modes listed below account for some 90% or more of all addressing modes used. Since most such measurements are based on code generated from high-level languages by compilers, this reflects to some extent the limitations of the compilers being used.[8][7][9]

## Load effective address

[edit]

Some instruction set architectures, such as IBM System/360 and its successors,[10] Intel x86,[11] and the Motorola 68000 series,[12] have a load effective address instruction. This calculates the effective operand address and loads it into a register, without accessing the memory it refers to. This can be useful when passing the address of an array element to a subroutine. It may also be a clever way of doing more calculations than normal in one instruction; for example, using such an instruction with the addressing mode "base+index+offset" (detailed below) allows one instruction to add two registers and a constant together and store the result in a third register.[13]

A few instruction set architectures, such as the Motorola 68000 series, also have a push effective address instruction. This calculates the effective operand address and pushes it on the stack rather than storing it in a register. This can be used to pass pointers as arguments to a function.

## Simple addressing modes for code

[edit]

Some simple addressing modes for code are shown below. The nomenclature may vary depending on platform.

### Absolute or direct

[edit]

+
-+

+
|jump|           address            |
+
-+

+

(Effective PC address = address)

The effective address for an absolute instruction address is the address parameter itself with no modifications.

### PC-relative

[edit]

+
-+

+
|jump|           offset             |    jump relative
+
-+

+

(Effective PC address = next instruction address + offset, offset may be negative)

The effective address for a PC-relative instruction address is the offset parameter added to the address of the next instruction. This offset is usually signed to allow reference to code both before and after the instruction.[14]

This is particularly useful in connection with jump instructions, because typical jumps are to nearby instructions (in a high-level language most if or while statements are reasonably short). Measurements of actual programs suggest that an 8 or 10 bit offset is large enough for some 90% of conditional jumps (roughly ±128 or ±512 bytes).[15] For jumps to instructions that are not nearby, other addressing modes are used.

Another advantage of PC-relative addressing is that the code may be position-independent, i.e. it can be loaded anywhere in memory without the need to adjust any addresses.

### Register indirect

[edit]

+

-+
--+
|jumpVia| reg |
+

-+
--+

(Effective PC address = contents of register 'reg')

The effective address for a register indirect instruction is the address in the specified register. For example, (A7) to access the content of address register A7.

The effect is to transfer control to the instruction whose address is in the specified register.

Many RISC machines, as well as the CISC IBM System/360 and successors, have subroutine call instructions that place the return address in an address register—the register indirect addressing mode is used to return from that subroutine call.

## Sequential addressing modes for code

[edit]

### Sequential execution

[edit]

+

+
| nop  |              execute the following instruction
+

+

(Effective PC address = next instruction address)

The CPU, after executing a sequential instruction, immediately executes the following instruction.

Sequential execution is not considered to be an addressing mode on some computers.

Most instructions on most CPU architectures are sequential instructions. Because most instructions are sequential instructions, CPU designers often add features that deliberately sacrifice performance on the other instructions—branch instructions—in order to make these sequential instructions run faster.

Conditional branches load the PC with one of 2 possible results, depending on the condition—most CPU architectures use some other addressing mode for the "taken" branch, and sequential execution for the "not taken" branch.

Many features in modern CPUs—instruction prefetch and more complex pipelineing, out-of-order execution, etc.—maintain the illusion that each instruction finishes before the next one begins, giving the same final results, even though that's not exactly what happens internally.

Each "basic block" of such sequential instructions exhibits both temporal and spatial locality of reference.

#### CPUs that do not use sequential execution

[edit]

CPUs that do not use sequential execution with a program counter are extremely rare. In some CPUs, each instruction always specifies the address of next instruction. Such CPUs have an instruction pointer that holds that specified address; it is not a program counter because there is no provision for incrementing it. Such CPUs include some drum memory computers such as the IBM 650, the SECD machine, Librascope RPC 4000, and the RTX 32P.[16]

On processors implemented with horizontal microcode, the microinstruction may contain the high order bits of the next instruction address.

Other computing architectures go much further, attempting to bypass the von Neumann bottleneck using a variety of alternatives to the program counter.

### Conditional execution

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Some computer architectures have conditional instructions (such as ARM, but no longer for all instructions in 64-bit mode) or conditional load instructions (such as x86) which can in some cases make conditional branches unnecessary and avoid flushing the instruction pipeline. An instruction such as a 'compare' is used to set a condition code, and subsequent instructions include a test on that condition code to see whether they are obeyed or ignored.

### Skip

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+

+
--+
--+
|skipEQ| reg1| reg2|      skip the next instruction if reg1=reg2
+

+
--+
--+

(Effective PC address = next instruction address + 1)

Skip addressing may be considered a special kind of PC-relative addressing mode with fixed offsets.[a] Like PC-relative addressing, some CPUs have versions of this addressing mode that only refer to one register ("skip if reg1=0") or no registers, implicitly referring to some previously-set bit in the status register. Other CPUs have a version that selects a specific bit in a specific byte to test ("skip if bit 7 of reg12 is 0").

Unlike all other conditional branches, a "skip" instruction never needs to flush the instruction pipeline, though it may need to cause the next instruction to be ignored.

## Simple addressing modes for data

[edit]

Some simple addressing modes for data are shown below. The nomenclature may vary depending on platform.

### Register (or, register direct)

[edit]

+

+
--+
--+
--+
| mul  | reg1| reg2| reg3|      reg1 := reg2 * reg3;
+

+
--+
--+
--+

This "addressing mode" does not have an effective address and is not considered to be an addressing mode on some computers.

In this example, all the operands are in registers, and the result is placed in a register.

### Base plus offset, and variations

[edit]

This is sometimes referred to as 'base plus displacement' or 'truncated'.

+

+
--+
--+

-+
| load | reg | base|     offset     |  reg := RAM[base + offset]
+

+
--+
--+

-+

(Effective address = offset + contents of specified base register)

If the offset is zero, this becomes an example of register indirect addressing; the effective address is just the value in the base register.

On many RISC machines, register 0 is fixed at the value zero. If register 0 is used as the base register, this becomes an example of absolute addressing. However, only a small portion of memory can be accessed.

The offset is often small in relation to the size of current computer memories. However, the principle of locality of reference applies: over a short time span, most of the data items a program wants to access are fairly close to each other.

This addressing mode is closely related to the indexed absolute addressing mode.

Example 1: Within a subroutine a programmer will mainly be interested in the parameters and the local variables, for which one base register (the frame pointer) usually suffices. If this routine is a class method in an object-oriented language, then a second base register is needed which points at the attributes for the current object (this or self in some high level languages).

Example 2: If the base register contains the address of a composite type (a record or structure), the offset can be usually used to select a field from that record.

### Immediate/literal

[edit]

+

+
--+
--+

-+
| add  | reg1| reg2|    constant    |    reg1 := reg2 + constant;
+

+
--+
--+

-+

This "addressing mode" does not have an effective address, and is not considered to be an addressing mode on some computers.

The constant might be signed or unsigned. For example, `move.l #$FEEDABBA, D0` to move the immediate hex value of "FEEDABBA" into register D0.

Instead of using an operand from memory, the value of the operand is held within the instruction itself. On the DEC VAX machine, the literal operand sizes could be 6, 8, 16, or 32 bits long.

Andrew Tanenbaum showed that 98% of all the constants in a program would fit in 13 bits (see RISC design philosophy).

### Implicit

[edit]

+

--+
| clear carry bit |
+

--+

+

-+
| clear Accumulator |
+

-+

The implied addressing mode, also called the implicit addressing mode (x86 assembly language), does not explicitly specify an effective address for either the source or the destination (or sometimes both).

Either the source (if any) or destination effective address (or sometimes both) is implied by the opcode.

Implied addressing was quite common on older computers (up to mid-1970s). Such computers typically had only a single register in which arithmetic could be performed—the accumulator. Such accumulator machines implicitly reference that accumulator in almost every instruction. For example, the operation < a := b + c; > can be done using the sequence < load b; add c; store a; > \-- the destination (the accumulator) is implied in every "load" and "add" instruction; the source (the accumulator) is implied in every "store" instruction.

Later computers generally had more than one general-purpose register or RAM location which could be the source or destination or both for arithmetic—and so later computers need some other addressing mode to specify the source and destination of arithmetic.

Among the x86 instructions, some use implicit registers for one of the operands or results (multiplication, division, counting conditional jump).

Some instruction sets (such as x86 and AVR) have one special-purpose register called the stack pointer which is implicitly incremented or decremented when pushing or popping data from the stack, and the source or destination effective address is (implicitly) the address stored in that stack pointer.

Some other instruction sets (such as m68k, ARM, and PowerPC) have more than one register that could be used as a stack pointer—and so use the "register autoincrement indirect" addressing mode to specify which of those registers should be used when pushing or popping data from a stack.

Some current computer instruction sets (e.g. z/Architecture and IA-32/x86-64) contain some instructions with implicit operands in order to maintain backwards compatibility with earlier designs.

On some instruction sets, instructions that flip the user/system mode bit, the interrupt-enable bit, etc. implicitly specify the special register that holds those bits. This simplifies the hardware necessary to trap those instructions in order to meet the Popek and Goldberg virtualization requirements—on such a system, the trap logic does not need to look at any operand (or at the final effective address), but only at the opcode.

Some instruction sets have been designed where every operand is always implicitly specified in every instruction -- zero-operand CPUs.

## Other addressing modes for code or data

[edit]

### Absolute/direct

[edit]

+

+
--+

--+
| load | reg |         address                      |
+

+
--+

--+

(Effective address = address as given in instruction)

This requires space in an instruction for quite a large address. It is often available on CISC machines which have variable-length instructions, such as x86.

Some RISC machines have a special Load Upper Literal instruction which places a 16- or 20-bit constant in the top half of a register. That can then be used as the base register in a base-plus-offset addressing mode which supplies the low-order 16 or 12 bits. The combination allows a full 32-bit address.

### Indexed absolute

[edit]

+

+
--+
--+

--+
| load | reg |index|         address                |
+

+
--+
--+

--+

(Effective address = address + contents of specified index register)

This also requires space in an instruction for quite a large address. The address could be the start of an array or vector, and the index could select the particular array element required. The processor may scale the index register to allow for the size of each array element.

Note that this is more or less the same as base-plus-offset addressing mode, except that the offset in this case is large enough to address any memory location.

Example 1: Within a subroutine, a programmer may define a string as a local constant or a static variable. The address of the string is stored in the literal address in the instruction. The offset—which character of the string to use on this iteration of a loop—is stored in the index register.

Example 2: A programmer may define several large arrays as globals or as class variables. The start of the array is stored in the literal address (perhaps modified at program-load time by a relocating loader) of the instruction that references it. The offset—which item from the array to use on this iteration of a loop—is stored in the index register. Often the instructions in a loop re-use the same register for the loop counter and the offsets of several arrays.

### Base plus index

[edit]

+

+
--+
--+
--+
| load | reg | base|index|
+

+
--+
--+
--+

(Effective address = contents of specified base register + contents of specified index register)

The base register could contain the start address of an array or vector, and the index could select the particular array element required. The processor may scale the index register to allow for the size of each array element. This could be used for accessing elements of an array passed as a parameter.

### Base plus index plus offset

[edit]

+

+
--+
--+
--+

-+
| load | reg | base|index|     offset     |
+

+
--+
--+
--+

-+

(Effective address = offset + contents of specified base register + contents of specified index register)

The base register could contain the start address of an array or vector of records, the index could select the particular record required, and the offset could select a field within that record. The processor may scale the index register to allow for the size of each array element.

### Scaled

[edit]

+

+
--+
--+
--+
| load | reg | base|index|
+

+
--+
--+
--+

(Effective address = contents of specified base register + scaled contents of specified index register)

The base register could contain the start address of an array or vector data structure, and the index could contain the offset of the one particular array element required.

This addressing mode dynamically scales the value in the index register to allow for the size of each array element, e.g. if the array elements are double precision floating-point numbers occupying 8 bytes each then the value in the index register is multiplied by 8 before being used in the effective address calculation. The scale factor is normally restricted to being a power of two, so that shifting rather than multiplication can be used.

### Register indirect

[edit]

+

+

+
--+
| load | reg1 | base|
+

+

+
--+

(Effective address = contents of base register)

A few computers have this as a distinct addressing mode. Many computers just use base plus offset with an offset value of 0. For example, (A7)

### Register autoincrement indirect

[edit]

+

+
--+

-+
| load | reg | base  |
+

+
--+

-+

(Effective address = contents of base register)

After determining the effective address, the value in the base register is incremented by the size of the data item that is to be accessed. For example, (A7)+ would access the content of the address register A7, then increase the address pointer of A7 by 1 (usually 1 word). Within a loop, this addressing mode can be used to step through all the elements of an array or vector.

In high-level languages it is often thought to be a good idea that functions which return a result should not have side effects (lack of side effects makes program understanding and validation much easier). This addressing mode has a side effect in that the base register is altered. If the subsequent memory access causes an error (e.g. page fault, bus error, address error) leading to an interrupt, then restarting the instruction becomes much more problematic since one or more registers may need to be set back to the state they were in before the instruction originally started.

There have been at least three computer architectures that have had implementation problems with regard to recovery from faults when this addressing mode is used:

* DEC PDP-11. Could have one or two autoincrement register operands.[17] Some models, such as the PDP-11/45 and PDP-11/70, had a register that recorded modifications to registers, allowing the fault handler to undo the register modifications and re-execute the instruction.[18]
* Motorola 68000 series. Could have one or two autoincrement register operands.[19] The 68010 and later processors resolved the problem by saving the processor's internal state on bus or address errors and restoring it when returning from the fault.[20][21][22][23]
* DEC VAX. Could have up to 6 autoincrement register operands. The First Part Done bit in the saved processor status longword in a stack frame for a fault is set if the faulting instruction must not be restarted at the beginning, resolving the problem.[24]

### Register autodecrement indirect

[edit]

+

+
--+
--+
| load | reg | base|
+

+
--+
--+

(Effective address = new contents of base register)

Before determining the effective address, the value in the base register is decremented by the size of the data item which is to be accessed.

Within a loop, this addressing mode can be used to step backwards through all the elements of an array or vector. A stack can be implemented by using this mode in conjunction with the previous addressing mode (autoincrement).

See the discussion of side-effects under the autoincrement addressing mode.

### Memory indirect or deferred

[edit]

Any of the addressing modes mentioned in this article could have an extra bit to indicate indirect addressing, i.e. the address calculated using some mode is in fact the address of a location (typically a complete word) which contains the actual effective address. On some machines the indirect word could indicate indexing, indirection, tallying[b] or some combination.

Indirect addressing may be used for code or data. It can make implementation of pointers, references, or handles much easier, and can also make it easier to call subroutines which are not otherwise addressable. Indirect addressing does carry a performance penalty due to the extra memory access involved.

Some early minicomputers (e.g. DEC PDP-8, Data General Nova) had only a few registers and only a limited direct addressing range (8 bits). Hence the use of memory indirect addressing was almost the only way of referring to any significant amount of memory.

Half of the DEC PDP-11's eight addressing modes are deferred. Register deferred @Rn is the same as register indirect as defined above. Predecrement deferred @-(Rn), postincrement deferred @(Rn)+, and indexed deferred @nn(Rn) modes point to addresses in memory which are read to find the address of the parameter. The PDP-11's deferred mode, when combined with the program counter, provide its absolute addressing mode.

### PC-relative

[edit]

+

+

+

+

-+
| load | reg1 | base=PC |     offset     |
+

+

+

+

-+

reg1 := RAM[PC + offset]
(Effective address = PC + offset)

The PC-relative addressing mode can be used to load a register with a value stored in program memory a short distance away from the current instruction. It can be seen as a special case of the "base plus offset" addressing mode, one that selects the program counter (PC) as the "base register".

There are a few CPUs that support PC-relative data references. Such CPUs include:

The x86-64 architecture and the 64-bit ARMv8-A architecture[25] have PC-relative addressing modes, called "RIP-relative" in x86-64 and "literal" in ARMv8-A. The Motorola 6809 also supports a PC-relative addressing mode.

The PDP-11 architecture, the VAX architecture, and the 32-bit ARM architectures support PC-relative addressing by having the PC in the register file.

The IBM z/Architecture includes specific instructions, e.g., Load Relative Long, with PC-relative addressing if the General-Instructions-Extension Facility is active.

When this addressing mode is used, the compiler typically places the constants in a literal pool immediately before or immediately after the subroutine that uses them, to prevent accidentally executing those constants as instructions.

This addressing mode, which always fetches data from memory or stores data to memory and then sequentially falls through to execute the next instruction (the effective address points to data), should not be confused with "PC-relative branch" which does not fetch data from or store data to memory, but instead branches to some other instruction at the given offset (the effective address points to an executable instruction).

## Obsolete addressing modes

[edit]

The addressing modes listed here were used in the 1950–1980 period, but are no longer available on most current computers. This list is by no means complete; there have been many other interesting and peculiar addressing modes used from time to time, e.g. absolute-minus-logical-OR of two or three index registers.[26][27]

### Multi-level memory indirect

[edit]

If the word size is larger than the address, then the word referenced for memory-indirect addressing could itself have an indirect flag set to indicate another memory indirect cycle. This flag is referred to as an indirection bit, and the resulting pointer is a tagged pointer, the indirection bit tagging whether it is a direct pointer or an indirect pointer. Care is needed to ensure that a chain of indirect addresses does not refer to itself; if it does, one can get an infinite loop while trying to resolve an address.

The IBM 1620, the Data General Nova, and the HP 2100 series each have such a multi-level memory indirect, and could enter such an infinite address calculation loop. The memory indirect addressing mode on the Nova influenced the invention of indirect threaded code.

The DEC PDP-10 computer with 18-bit addresses and 36-bit words allowed multi-level indirect addressing with the possibility of using an index register at each stage as well. The priority interrupt system was queried before decoding of every address word.[28] So, an indirect address loop would not prevent execution of device service routines, including any preemptive multitasking scheduler's time-slice expiration handler. A looping instruction would be treated like any other compute-bound job.

### Memory-mapped registers

[edit]

On some computers, there were addresses that referred to registers rather than to primary storage, or to primary memory used to implement those registers. Although on some early computers there were register addresses at the high end of the address range, e.g., IBM 650,[29][c] IBM 7070,[30][e] the trend has been to use only register address at the low end and to use only the first 8 or 16 words of memory (e.g. ICL 1900, DEC PDP-6/PDP-10). This meant that there was no need for a separate "add register to register" instruction – one could just use the "add memory to register" instruction.

In the case of early models of the PDP-10, which did not have any cache memory, if the "fast registers" option, which provided faster circuits to store the registers but still allowed them to be addressed as if they were in memory, was installed, a tight inner loop loaded into the first few words of memory ran much faster than it would have in magnetic core memory.

Later models of the DEC PDP-11 series mapped the registers onto addresses in the input/output area, but this was primarily intended to allow remote diagnostics. Confusingly, the 16-bit registers were mapped onto consecutive 8-bit byte addresses.

### Memory indirect and autoincrement

[edit]

The DEC PDP-8 minicomputer had eight special locations (at addresses 8 through 15). When accessed via memory indirect addressing, these locations would automatically increment prior to use.[31] This made it easy to step through memory in a loop without needing to use the accumulator to increment the address.

The Data General Nova minicomputer had 16 special memory locations at addresses 16 through 31.[32] When accessed via memory indirect addressing, 16 through 23 would automatically increment before use, and 24 through 31 would automatically decrement before use.

### Zero page

[edit]

The Data General Nova, Motorola 6800 family, and MOS Technology 6502 family of processors had very few internal registers. Arithmetic and logical instructions were mostly performed against values in memory as opposed to internal registers. As a result, many instructions required a two-byte (16-bit) location to memory. Given that opcodes on these processors were only one byte (8 bits) in length, memory addresses could make up a significant part of code size.

Designers of these processors included a partial remedy known as "zero page" addressing. The initial 256 bytes of memory ($0000 – $00FF; a.k.a., page "0") could be accessed using a one-byte absolute or indexed memory address. This reduced instruction execution time by one clock cycle and instruction length by one byte. By storing often-used data in this region, programs could be made smaller and faster.

As a result, the zero page was used similarly to a register file. On many systems, however, this resulted in high utilization of the zero page memory area by the operating system and user programs, which limited its use since free space was limited.

### Direct page

[edit]

The zero page address mode was enhanced in several late model 8-bit processors, including the WDC 65816, the CSG 65CE02, and the Motorola 6809. The new mode, known as "direct page" addressing, added the ability to move the 256-byte zero page memory window from the start of memory (offset address $0000) to a new location within the first 64 KB of memory.

The CSG 65CE02 allowed the direct page to be moved to any 256-byte boundary within the first 64 KB of memory by storing an 8-bit offset value in the new base page (B) register. The Motorola 6809 could do the same with its direct page (DP) register. The WDC 65816 went a step further and allowed the direct page to be moved to any location within the first 64 KB of memory by storing a 16-bit offset value in the new direct (D) register.

As a result, a greater number of programs were able to utilize the enhanced direct page addressing mode versus legacy processors that only included the zero page addressing mode.

### Scaled index with bounds checking

[edit]

This is similar to scaled index addressing, except that the instruction has two extra operands (typically constants), and the hardware checks that the index value is between these bounds.

Another variation uses vector descriptors to hold the bounds; this makes it easy to implement dynamically allocated arrays and still have full bounds checking.

### Indirect to bit field within word

[edit]

Some computers had special indirect addressing modes for subfields within words.

The GE/Honeywell 600 series character addressing indirect word specified either 6-bit or 9-bit character fields within its 36-bit word.

The DEC PDP-10, also 36-bit, had special instructions which allowed memory to be treated as a sequence of fixed-size bit fields or bytes of any size from 1 bit to 36 bits. A one-word sequence descriptor in memory, called a "byte pointer", held the current word address within the sequence, a bit position within a word, and the size of each byte.

Instructions existed to load and store bytes via this descriptor, and to increment the descriptor to point at the next byte (bytes were not split across word boundaries). Much DEC software used five 7-bit bytes per word (plain ASCII characters), with one bit per word unused. Implementations of C had to use four 9-bit bytes per word, since the 'malloc' function in C assumes that the size of an int is some multiple of the size of a char;[33] the actual multiple is determined by the system-dependent compile-time operator sizeof.

### Index next instruction

[edit]

The Elliott 503,[34] the Elliott 803,[34][35] and the Apollo Guidance Computer only used absolute addressing, and did not have any index registers. Thus, indirect jumps, or jumps through registers, were not supported in the instruction set. Instead, it could be instructed to add the contents of the current memory word to the next instruction. Adding a small value to the next instruction to be executed could, for example, change a `JUMP 0` into a `JUMP 20`, thus creating the effect of an indexed jump. Note that the instruction is modified on-the-fly and remains unchanged in memory, i.e. it is not self-modifying code. If the value being added to the next instruction was large enough, it could modify the opcode of that instruction as well as or instead of the address.

## Glossary

[edit]

Indirect
Data referred to through a pointer or address.
Immediate
Data embedded directly in an instruction or command list.
Index
A dynamic offset, typically held in an index register, possibly scaled by an object size.
Offset
An immediate value added to an address; e.g., corresponding to structure field access in the C programming language.
Relative
An address formed relative to another address.
Post increment
The stepping of an address past data used, similar to `*p++` in the C programming language, used for stack pop operations.
Pre decrement
The decrementing of an address prior to use, similar to `*--p` in the C programming language, used for stack push operations.

## See also

[edit]

* Instruction set architecture
* Address bus

## Notes

[edit]

1. ^ Most often just NSI+1 on word-oriented machines, but, e.g., the Compare Accumulator and Skip (CAS) on the IBM 7090 can skip to NSI+1 or NSI+2.
2. ^ Either increment or decrement.
3. ^ Condensor storage units for 650:

8000 Console switches
8001 Distributor
8002 Lower accumulator
8003 Upper accumulator
4. ^ a b Only valid from console
5. ^ For 5K or 10K 7070

00xx Index register xx
9991 Accumulator 1
9992 Accumulator 2
9993 Accumulator 3
9995 Program register[d]
9999 Instruction counter[d]

## References

[edit]

1. ^ System Reference Manual - RCA 3301 REALCOM EDP (PDF). RCA. September 1967. 94-16-000-1. Retrieved December 21, 2023.
2. ^ F. Chow; S. Correll; M. Himelstein; E. Killian; L. Weber (1987). "How many addressing modes are enough?". ACM SIGARCH Computer Architecture News. 15 (5): 117–121\. doi:10.1145/36177.36193.
3. ^ John L. Hennessy; Mark A. Horowitz (1986). "An Overview of the MIPS-X-MP Project" (PDF). "... MIPS-X uses a single addressing mode: base register plus offset. This simple addressing mode allows the computation of the effective address to begin very early ..."
4. ^ Dr. Jon Squire. "Lecture 19, Pipelining Data Forwarding". CS411 Selected Lecture Notes.
5. ^ "High Performance Computing, Notes of Class 11 (Sept. 15 and 20, 2000) - Pipelining". Archived from the original on 2013-12-27. Retrieved 2014-02-08.
6. ^ John Paul Shen, Mikko H. Lipasti (2004). Modern Processor Design. McGraw-Hill Professional. ISBN 9780070570641.
7. ^ a b John L. Hennessy; David A. Patterson (2002-05-29). Computer Architecture: A Quantitative Approach. Elsevier. p. 104\. ISBN 9780080502526. "The C54x has 17 data addressing modes, not counting register access, but the four found in MIPS account for 70% of the modes. Autoincrement and autodecrement, found in some RISC architectures, account for another 25% of the usage. This data was collected form a measurement of static instructions for the C-callable library of 54 DSP routines coded in assembly language."
8. ^ Dr. Sofiène Tahar. "Instruction Set Principles: Addressing Mode Usage (Summary)" (PDF). Archived from the original (PDF) on 2011-09-30. "3 programs measured on machine with all address modes (VAX) ... 75% displacement and immediate"
9. ^ Ali-Reza Adl-Tabatabai; Geoff Langdale; Steven Lucco; Robert Wahbe (1995). "Efficient and Language-Independent Mobile Programs". Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation - PLDI '96. pp. 127–136\. doi:10.1145/231379.231402. ISBN 0897917952. S2CID 2534344. "79% of all instructions executed could be replaced by RISC instructions or synthesized into RISC instructions using only basic block instruction combination."
10. ^ "Load Address" (PDF). z/Architecture - Principles of Operation (PDF) (Fourteenth ed.). IBM. May 2022. p. 7-269. SA22-7832-13. Retrieved May 30, 2025.
11. ^ "7.3.16.1 Address Computation Instruction" (PDF). Intel® 64 and IA-32 Architectures Software Developer’s Manual (Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D and 4) (PDF). Vol. 1\. Intel Corporation. July 2017. p. 7-23. Retrieved Jun 23, 2025. "The LEA (load effective address) instruction computes the effective address in memory (offset within a segment) of a source operand and places it in a general-purpose register. This instruction can interpret any of the processor's addressing modes and can perform any indexing or scaling that may be needed. It is especially useful for initializing the ESI or EDI registers before the execution of string instructions or for initializing the EBX register before an XLAT instruction."
12. ^ "section 4 Integer Instructions" (PDF). M68000 Family - Programmer's Reference Manual - (Includes CPU32 Instructions) (PDF). Motorola. 1992. p. 4-110. Retrieved June 23, 2025.
13. ^ "Instruction Use Examples" (PDF). IBM System/360 Principles of Operation (PDF). IBM. September 1968. p. 135. A22-6821-7. Retrieved 12 July 2019.
14. ^ Max Maxfield. "Building a 4-Bit Computer: Assembly Language and Assembler". Section "Addressing modes". 2019.
15. ^ Kong, Shing; Patterson, David (1995). "Instruction set design". Slide 27.
16. ^ Koopman, Philip (1989). "Architecture of the RTX 32P". Stack Computers.
17. ^ PDP-11 Architecture Handbook (PDF). Digital Equipment Corporation. 1973.
18. ^ PDP-11/45 Processor Handbook (PDF). Digital Equipment Corporation. 1973. pp. 150–153.
19. ^ M68000 Family Programmer's Reference Manual (PDF). Motorola. 1992.
20. ^ MC68010/MC68012 16-/32-Bit Virtual Memory Microprocessors (PDF). Motorola. May 1985. pp. 5-12 – 5-15.
21. ^ MC68020 32-Bit Microprocessor User's Manual (PDF). Prentice-Hall. 1984. pp. 6-9 – 6-10. ISBN 0-13-541418-0.
22. ^ MC68030 Enhanced 32-Bit Microprocessor User's Manual (PDF) (Third ed.). Prentice-Hall. 1990. pp. 8-7 – 8-8. ISBN 0-13-566423-3.
23. ^ MC68040 32-Bit Microprocessor User's Manual (PDF) (Third ed.). Motorola. 1989. pp. 9-8 – 9-9.
24. ^ VAX Architecture Reference Manual (PDF). Digital Equipment Corporation. 1987. p. 21\. ISBN 0-932376-86-X.
25. ^ "Introduction to ARMv8 64-bit Architecture". UIC Academy. quequero.org. 9 April 2014.
26. ^ 704 Electronic Data-Processing Machine Manual of Operation (PDF). IBM. 1955. pp. 10–11.
27. ^ Reference Manual IBM 7090 Data Processing System (PDF). IBM. 1962. pp. 9–10.
28. ^ DEC-10-HMAA-D: PDP-10 KA10 Central Processor Maintenance Manual (PDF) (1st Printing ed.). Maynard, Massachusetts: Digital Equipment Corporation. December 1968. pp. 2–11. Retrieved 15 May 2021. "Figure 2-9: Effective Address Calculation: test "PI RQ ?""
29. ^ "Storage" (PDF). 650 magnetic drum data-processing machine - manual of operation (PDF). June 1955. p. 9. 22-6060-2. Retrieved March 14, 2022.
30. ^ "Core Storage and Register Addresses" (PDF). Reference Manual - IBM 7070 Data Processing System (PDF). January 1960. p. 252\. A22-7003-0. Retrieved March 14, 2022.
31. ^ Jones, Douglas, Reference Instructions on the PDP-8, retrieved 1 July 2013
32. ^ Friend, Carl, Data General NOVA Instruction Set Summary, retrieved 1 July 2013
33. ^ "C Reference: function malloc()"
34. ^ a b Dave Brooks. "Some Old Computers".
35. ^ Bill Purvis. "Some details of the Elliott 803B hardware"

## External links

[edit]

* Addressing modes in assembly language
* Addressing modes

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Processor technologies

Models|

* Abstract machine
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Instruction set
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|

Instruction
sets|

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Execution|

| Instruction pipelining|

* Pipeline stall
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|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Scoreboarding
* Tomasulo's algorithm
* Reservation station
* Re-order buffer
* Register renaming
* Wide-issue

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Simultaneous and heterogenous
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* Array processing (SIMT)
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* Associative processing
* SWAR
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Processor
performance|

* Transistor count
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* Cache performance metrics
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Types|

* Central processing unit (CPU)
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* GPGPU
* Vector
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| By application|

* Embedded system
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|

Systems
on chip|

* System on a chip (SoC)
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* Cypress PSoC
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Hardware
accelerators|

* Coprocessor
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Word size|

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Core count|

* Single-core
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Components|

* Core
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| Functional
units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Branch predictor
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* Memory management unit
* Instruction decoder

|

Logic|

* Combinational
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* Array

Registers|

* Processor register
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* Memory buffer
* Memory address register
* Program counter

Control unit|

* Hardwired control unit
* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum-addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
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* Power management
* Boolean
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* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model
* Pin grid array
* Chip carrier

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