CUDA

Parallel computing platform and programming model

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For other uses, see Cuda (disambiguation).

CUDA

Original author(s)| Ian Buck
John Nickolls
Developer(s)| Nvidia
Initial release| February 16, 2007; 18 years ago (2007-02-16)[1]
Stable release|

12.9 / May 2025; 2 months ago (2025-05)

Written in| C
Operating system| Windows, Linux
Platform| Supported GPUs
Type| GPGPU
License| Proprietary
Website| developer.nvidia.com/cuda-zone

CUDA is a proprietary[2] parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for accelerated general-purpose processing, significantly broadening their utility in scientific and high-performance computing. CUDA was created by Nvidia starting in 2004 and was officially released by in 2007.[3] When it was first introduced, the name was an acronym for Compute Unified Device Architecture,[4] but Nvidia later dropped the common use of the acronym and now rarely expands it.[5]

CUDA is both a software layer that manages data, giving direct access to the GPU and CPU as necessary and a library of APIs that enable parallel computation for various needs.[6][7] In addition to drivers and runtime kernels, the CUDA platform includes compilers, libraries and developer tools to help programmers accelerate their applications.

CUDA is written in C but is designed to work with a wide array of other programming languages including C++, Fortran, Python and Julia. This accessibility makes it easier for specialists in parallel programming to use GPU resources, in contrast to prior APIs like Direct3D and OpenGL, which require advanced skills in graphics programming.[8] CUDA-powered GPUs also support programming frameworks such as OpenMP, OpenACC and OpenCL.[9][6]

## Background

[edit]

Further information: Graphics processing unit

The graphics processing unit (GPU), as a specialized computer processor, addresses the demands of real-time high-resolution 3D graphics compute-intensive tasks. By 2012, GPUs had evolved into highly parallel multi-core systems allowing efficient manipulation of large blocks of data. This design is more effective than general-purpose central processing unit (CPUs) for algorithms in situations where processing large blocks of data is done in parallel, such as:

* cryptographic hash functions
* machine learning
* molecular dynamics simulations
* physics engines

The origins of CUDA trace back to the early 2000s, when Ian Buck, a computer science Ph.D. student at Stanford University, began experimenting with using GPUs for purposes beyond rendering graphics. Buck had first become interested in GPUs during his undergraduate studies at Princeton University, initially through video gaming. After graduation, he interned at Nvidia, gaining deeper exposure to GPU architecture. At Stanford, he built an 8K gaming rig using 32 GeForce graphics cards, originally to push the limits of graphics performance in games like Quake and Doom. However, his interests shifted toward exploring the potential of GPUs for general-purpose parallel computing.[10]

To that end, Buck developed Brook, a programming language designed to enable general-purpose computing on GPUs. His work attracted support from both Nvidia and the Defense Advanced Research Projects Agency (DARPA). In 2004, Nvidia hired Buck and paired him with John Nickolls, the company’s director of architecture for GPU computing. Together, they began transforming Brook into what would become CUDA.[10] CUDA was officially released by Nvidia in 2007.

Under the leadership of Nvidia CEO Jensen Huang, CUDA became central to the company’s strategy of positioning GPUs as versatile hardware for scientific applications. By 2015, CUDA’s development increasingly focused on accelerating machine learning and artificial neural network workloads.[11]

## Ontology

[edit]

The following table offers a non-exact description for the ontology of CUDA framework.

The ontology of CUDA framework  memory
(hardware)  | memory (code, or variable scoping)  | computation
(hardware)  | computation
(code syntax)  | computation
(code semantics)

|
|
|
|

RAM | non-CUDA variables  | host  | program  | one routine call
VRAM,
GPU L2 cache  | global, const, texture  | device  | grid  | simultaneous call of the same subroutine on many processors
GPU L1 cache  | local, shared  | SM ("streaming multiprocessor")  | block  | individual subroutine call
|  | warp = 32 threads  |  | SIMD instructions
GPU L0 cache,
register  |  | thread (aka. "SP", "streaming processor", "cuda core", but these names are now deprecated)  |  | analogous to individual scalar ops within a vector op

## Programming abilities

[edit]

Example of CUDA processing flow

1. Copy data from main memory to GPU memory
2. CPU initiates the GPU compute kernel
3. GPU's CUDA cores execute the kernel in parallel
4. Copy the resulting data from GPU memory to main memory

The CUDA platform is accessible to software developers through CUDA-accelerated libraries, compiler directives such as OpenACC, and extensions to industry-standard programming languages including C, C++, Fortran and Python. C/C++ programmers can use 'CUDA C/C++', compiled to PTX with nvcc, Nvidia's LLVM-based C/C++ compiler, or by clang itself.[12] Fortran programmers can use 'CUDA Fortran', compiled with the PGI CUDA Fortran compiler from The Portland Group.[needs update] Python programmers can use the cuNumeric library to accelerate applications on Nvidia GPUs.

In addition to libraries, compiler directives, CUDA C/C++ and CUDA Fortran, the CUDA platform supports other computational interfaces, including the Khronos Group's OpenCL,[13] Microsoft's DirectCompute, OpenGL Compute Shader and C++ AMP.[14] Third party wrappers are also available for Python, Perl, Fortran, Java, Ruby, Lua, Common Lisp, Haskell, R, MATLAB, IDL, Julia, and native support in Mathematica.

In the computer game industry, GPUs are used for graphics rendering, and for game physics calculations (physical effects such as debris, smoke, fire, fluids); examples include PhysX and Bullet. CUDA has also been used to accelerate non-graphical applications in computational biology, cryptography and other fields by an order of magnitude or more.[15][16][17][18][19]

CUDA provides both a low level API (CUDA Driver API, non single-source) and a higher level API (CUDA Runtime API, single-source). The initial CUDA SDK was made public on 15 February 2007, for Microsoft Windows and Linux. Mac OS X support was later added in version 2.0,[20] which supersedes the beta released February 14, 2008.[21] CUDA works with all Nvidia GPUs from the G8x series onwards, including GeForce, Quadro and the Tesla line. CUDA is compatible with most standard operating systems.

CUDA 8.0 comes with the following libraries (for compilation & runtime, in alphabetical order):

* cuBLAS – CUDA Basic Linear Algebra Subroutines library
* CUDART – CUDA Runtime library
* cuFFT – CUDA Fast Fourier Transform library
* cuRAND – CUDA Random Number Generation library
* cuSOLVER – CUDA based collection of dense and sparse direct solvers
* cuSPARSE – CUDA Sparse Matrix library
* NPP – NVIDIA Performance Primitives library
* nvGRAPH – NVIDIA Graph Analytics library
* NVML – NVIDIA Management Library
* NVRTC – NVIDIA Runtime Compilation library for CUDA C++

CUDA 8.0 comes with these other software components:

* nView – NVIDIA nView Desktop Management Software
* NVWMI – NVIDIA Enterprise Management Toolkit
* GameWorks PhysX – is a multi-platform game physics engine

CUDA 9.0–9.2 comes with these other components:

* CUTLASS 1.0 – custom linear algebra algorithms,
* NVIDIA Video Decoder was deprecated in CUDA 9.2; it is now available in NVIDIA Video Codec SDK

CUDA 10 comes with these other components:

* nvJPEG – Hybrid (CPU and GPU) JPEG processing

CUDA 11.0–11.8 comes with these other components:[22][23][24][25]

* CUB is new one of more supported C++ libraries
* MIG multi instance GPU support
* nvJPEG2000 – JPEG 2000 encoder and decoder

## Advantages

[edit]

CUDA has several advantages over traditional general-purpose computation on GPUs (GPGPU) using graphics APIs:

* Scattered reads – code can read from arbitrary addresses in memory.
* Unified virtual memory (CUDA 4.0 and above)
* Unified memory (CUDA 6.0 and above)
* Shared memory – CUDA exposes a fast shared memory region that can be shared among threads. This can be used as a user-managed cache, enabling higher bandwidth than is possible using texture lookups.[26]
* Faster downloads and readbacks to and from the GPU
* Full support for integer and bitwise operations, including integer texture lookups

## Limitations

[edit]

* Whether for the host computer or the GPU device, all CUDA source code is now processed according to C++ syntax rules.[27] This was not always the case. Earlier versions of CUDA were based on C syntax rules.[28] As with the more general case of compiling C code with a C++ compiler, it is therefore possible that old C-style CUDA source code will either fail to compile or will not behave as originally intended.
* Interoperability with rendering languages such as OpenGL is one-way, with OpenGL having access to registered CUDA memory but CUDA not having access to OpenGL memory.
* Copying between host and device memory may incur a performance hit due to system bus bandwidth and latency (this can be partly alleviated with asynchronous memory transfers, handled by the GPU's DMA engine).
* Threads should be running in groups of at least 32 for best performance, with total number of threads numbering in the thousands. Branches in the program code do not affect performance significantly, provided that each of 32 threads takes the same execution path; the SIMD execution model becomes a significant limitation for any inherently divergent task (e.g. traversing a space partitioning data structure during ray tracing).
* No emulation or fallback functionality is available for modern revisions.
* Valid C++ may sometimes be flagged and prevent compilation due to the way the compiler approaches optimization for target GPU device limitations.[citation needed]
* C++ run-time type information (RTTI) and C++-style exception handling are only supported in host code, not in device code.
* In single-precision on first generation CUDA compute capability 1.x devices, denormal numbers are unsupported and are instead flushed to zero, and the precision of both the division and square root operations are slightly lower than IEEE 754-compliant single precision math. Devices that support compute capability 2.0 and above support denormal numbers, and the division and square root operations are IEEE 754 compliant by default. However, users can obtain the prior faster gaming-grade math of compute capability 1.x devices if desired by setting compiler flags to disable accurate divisions and accurate square roots, and enable flushing denormal numbers to zero.[29]
* Unlike OpenCL, CUDA-enabled GPUs are only available from Nvidia as it is proprietary.[30][2] Attempts to implement CUDA on other GPUs include:
* Project Coriander: Converts CUDA C++11 source to OpenCL 1.2 C. A fork of CUDA-on-CL intended to run TensorFlow.[31][32][33]
* CU2CL: Convert CUDA 3.2 C++ to OpenCL C.[34]
* GPUOpen HIP: A thin abstraction layer on top of CUDA and ROCm intended for AMD and Nvidia GPUs. Has a conversion tool for importing CUDA C++ source. Supports CUDA 4.0 plus C++11 and float16.
* ZLUDA is a drop-in replacement for CUDA on AMD GPUs and formerly Intel GPUs with near-native performance.[35] The developer, Andrzej Janik, was separately contracted by both Intel and AMD to develop the software in 2021 and 2022, respectively. However, neither company decided to release it officially due to the lack of a business use case. AMD's contract included a clause that allowed Janik to release his code for AMD independently, allowing him to release the new version that only supports AMD GPUs.[36]
* chipStar can compile and run CUDA/HIP programs on advanced OpenCL 3.0 or Level Zero platforms.[37]

## Example

[edit]

This example code in C++ loads a texture from an image into an array on the GPU:

texture<float, 2, cudaReadModeElementType> tex;

void foo()

cudaArray* cu_array;

// Allocate array
cudaChannelFormatDesc description = cudaCreateChannelDesc<float>();
cudaMallocArray(&cu_array, &description, width, height);

// Copy image data to array
cudaMemcpyToArray(cu_array, image, width*height*sizeof(float), cudaMemcpyHostToDevice);

// Set texture parameters (default)
tex.addressMode[0] = cudaAddressModeClamp;
tex.addressMode[1] = cudaAddressModeClamp;
tex.filterMode = cudaFilterModePoint;
tex.normalized = false; // do not normalize coordinates

// Bind the array to the texture
cudaBindTextureToArray(tex, cu_array);

// Run kernel
dim3 blockDim(16, 16, 1);
dim3 gridDim((width + blockDim.x - 1)/ blockDim.x, (height + blockDim.y - 1) / blockDim.y, 1);
kernel<<< gridDim, blockDim, 0 >>>(d_data, height, width);

// Unbind the array from the texture
cudaUnbindTexture(tex);
} //end foo()

__global__ void kernel(float* odata, int height, int width)

unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x < width && y < height) {
float c = tex2D(tex, x, y);
odata[y*width+x] = c;

Below is an example given in Python that computes the product of two arrays on the GPU. The unofficial Python language bindings can be obtained from PyCUDA.[38]

import pycuda.compiler as comp
import pycuda.driver as drv
import numpy
import pycuda.autoinit

mod = comp.SourceModule(
"""
__global__ void multiply_them(float *dest, float *a, float *b)

const int i = threadIdx.x;
dest[i] = a[i] * b[i];

"""

multiply_them = mod.get_function("multiply_them")

a = numpy.random.randn(400).astype(numpy.float32)
b = numpy.random.randn(400).astype(numpy.float32)

dest = numpy.zeros_like(a)
multiply_them(drv.Out(dest), drv.In(a), drv.In(b), block=(400, 1, 1))

print(dest - a * b)

Additional Python bindings to simplify matrix multiplication operations can be found in the program pycublas.[39]

import numpy
from pycublas import CUBLASMatrix

A = CUBLASMatrix(numpy.mat([[1, 2, 3], [4, 5, 6]], numpy.float32))
B = CUBLASMatrix(numpy.mat([[2, 3], [4, 5], [6, 7]], numpy.float32))
C = A * B
print(C.np_mat())

while CuPy directly replaces NumPy:[40]

import cupy

a = cupy.random.randn(400)
b = cupy.random.randn(400)

dest = cupy.zeros_like(a)

print(dest - a * b)

## GPUs supported

[edit]

Supported CUDA compute capability versions for CUDA SDK version and microarchitecture (by code name):

Compute capability (CUDA SDK support vs. microarchitecture)  CUDA SDK
version(s) | Tesla | Fermi | Kepler
(early) | Kepler
(late) | Maxwell | Pascal | Volta | Turing | Ampere | Ada
Lovelace | Hopper | Blackwell

|
|
|
|
|
|
|
|
|
|
|
|

1.0[41] | 1.0 – 1.1 |  |  |  |  |  |  |  |  |  |  |
1.1 | 1.0 – 1.1+x |  |  |  |  |  |  |  |  |  |  |
2.0 | 1.0 – 1.1+x |  |  |  |  |  |  |  |  |  |  |
2.1 – 2.3.1[42][43][44][45] | 1.0 – 1.3 |  |  |  |  |  |  |  |  |  |  |
3.0 – 3.1[46][47] | 1.0 | 2.0 |  |  |  |  |  |  |  |  |  |
3.2[48] | 1.0 | 2.1 |  |  |  |  |  |  |  |  |  |
4.0 – 4.2 | 1.0 | 2.1 |  |  |  |  |  |  |  |  |  |
5.0 – 5.5 | 1.0 |  | 3.0 | 3.5 |  |  |  |  |  |  |  |
6.0 | 1.0 |  | 3.2 | 3.5 |  |  |  |  |  |  |  |
6.5 | 1.1 |  |  | 3.7 | 5.x |  |  |  |  |  |  |
7.0 – 7.5 |  | 2.0 |  |  | 5.x |  |  |  |  |  |  |
8.0 |  | 2.0 |  |  |  | 6.x |  |  |  |  |  |
9.0 – 9.2 |  |  | 3.0 |  |  |  | 7.0 – 7.2 |  |  |  |  |
10.0 – 10.2 |  |  | 3.0 |  |  |  |  | 7.5 |  |  |  |
11.0[49] |  |  |  | 3.5 |  |  |  |  | 8.0 |  |  |
11.1 – 11.4[50] |  |  |  | 3.5 |  |  |  |  | 8.6 |  |  |
11.5 – 11.7.1[51] |  |  |  | 3.5 |  |  |  |  | 8.7 |  |  |
11.8[52] |  |  |  | 3.5 |  |  |  |  |  | 8.9 | 9.0 |
12.0 – 12.6 |  |  |  |  | 5.0 |  |  |  |  |  | 9.0 |
12.8 |  |  |  |  | 5.0 |  |  |  |  |  |  | 12.0
12.9 |  |  |  |  | 5.0 |  |  |  |  |  |  | 12.1

Note: CUDA SDK 10.2 is the last official release for macOS, as support will not be available for macOS in newer releases.

CUDA compute capability by version with associated GPU semiconductors and GPU card models (separated by their various application areas):

Compute capability, GPU semiconductors and Nvidia GPU board products  Compute
capability
(version)  | Micro-
architecture | GPUs  | GeForce | Quadro, NVS | Tesla/Datacenter | Tegra,
Jetson,
DRIVE

|
|
|
|
|
|

1.0  | Tesla | G80  | GeForce 8800 Ultra, GeForce 8800 GTX, GeForce 8800 GTS(G80)  | Quadro FX 5600, Quadro FX 4600, Quadro Plex 2100 S4  | Tesla C870, Tesla D870, Tesla S870  |
1.1  | G92, G94, G96, G98, G84, G86  | GeForce GTS 250, GeForce 9800 GX2, GeForce 9800 GTX, GeForce 9800 GT, GeForce 8800 GTS(G92), GeForce 8800 GT, GeForce 9600 GT, GeForce 9500 GT, GeForce 9400 GT, GeForce 8600 GTS, GeForce 8600 GT, GeForce 8500 GT,
GeForce G110M, GeForce 9300M GS, GeForce 9200M GS, GeForce 9100M G, GeForce 8400M GT, GeForce G105M  | Quadro FX 4700 X2, Quadro FX 3700, Quadro FX 1800, Quadro FX 1700, Quadro FX 580, Quadro FX 570, Quadro FX 470, Quadro FX 380, Quadro FX 370, Quadro FX 370 Low Profile, Quadro NVS 450, Quadro NVS 420, Quadro NVS 290, Quadro NVS 295, Quadro Plex 2100 D4,
Quadro FX 3800M, Quadro FX 3700M, Quadro FX 3600M, Quadro FX 2800M, Quadro FX 2700M, Quadro FX 1700M, Quadro FX 1600M, Quadro FX 770M, Quadro FX 570M, Quadro FX 370M, Quadro FX 360M, Quadro NVS 320M, Quadro NVS 160M, Quadro NVS 150M, Quadro NVS 140M, Quadro NVS 135M, Quadro NVS 130M, Quadro NVS 450, Quadro NVS 420,[53] Quadro NVS 295  |  |
1.2  | GT218, GT216, GT215  | GeForce GT 340*, GeForce GT 330*, GeForce GT 320*, GeForce 315*, GeForce 310*, GeForce GT 240, GeForce GT 220, GeForce 210,
GeForce GTS 360M, GeForce GTS 350M, GeForce GT 335M, GeForce GT 330M, GeForce GT 325M, GeForce GT 240M, GeForce G210M, GeForce 310M, GeForce 305M  | Quadro FX 380 Low Profile, Quadro FX 1800M, Quadro FX 880M, Quadro FX 380M,
Nvidia NVS 300, NVS 5100M, NVS 3100M, NVS 2100M, ION  |  |
1.3  | GT200, GT200b  | GeForce GTX 295, GTX 285, GTX 280, GeForce GTX 275, GeForce GTX 260  | Quadro FX 5800, Quadro FX 4800, Quadro FX 4800 for Mac, Quadro FX 3800, Quadro CX, Quadro Plex 2200 D2  | Tesla C1060, Tesla S1070, Tesla M1060  |
2.0  | Fermi | GF100, GF110  | GeForce GTX 590, GeForce GTX 580, GeForce GTX 570, GeForce GTX 480, GeForce GTX 470, GeForce GTX 465,
GeForce GTX 480M  | Quadro 6000, Quadro 5000, Quadro 4000, Quadro 4000 for Mac, Quadro Plex 7000,
Quadro 5010M, Quadro 5000M  | Tesla C2075, Tesla C2050/C2070, Tesla M2050/M2070/M2075/M2090  |
2.1  | GF104, GF106 GF108, GF114, GF116, GF117, GF119  | GeForce GTX 560 Ti, GeForce GTX 550 Ti, GeForce GTX 460, GeForce GTS 450, GeForce GTS 450*, GeForce GT 640 (GDDR3), GeForce GT 630, GeForce GT 620, GeForce GT 610, GeForce GT 520, GeForce GT 440, GeForce GT 440*, GeForce GT 430, GeForce GT 430*, GeForce GT 420*,
GeForce GTX 675M, GeForce GTX 670M, GeForce GT 635M, GeForce GT 630M, GeForce GT 625M, GeForce GT 720M, GeForce GT 620M, GeForce 710M, GeForce 610M, GeForce 820M, GeForce GTX 580M, GeForce GTX 570M, GeForce GTX 560M, GeForce GT 555M, GeForce GT 550M, GeForce GT 540M, GeForce GT 525M, GeForce GT 520MX, GeForce GT 520M, GeForce GTX 485M, GeForce GTX 470M, GeForce GTX 460M, GeForce GT 445M, GeForce GT 435M, GeForce GT 420M, GeForce GT 415M, GeForce 710M, GeForce 410M  | Quadro 2000, Quadro 2000D, Quadro 600,
Quadro 4000M, Quadro 3000M, Quadro 2000M, Quadro 1000M,
NVS 310, NVS 315, NVS 5400M, NVS 5200M, NVS 4200M  |  |
3.0  | Kepler | GK104, GK106, GK107  | GeForce GTX 770, GeForce GTX 760, GeForce GT 740, GeForce GTX 690, GeForce GTX 680, GeForce GTX 670, GeForce GTX 660 Ti, GeForce GTX 660, GeForce GTX 650 Ti BOOST, GeForce GTX 650 Ti, GeForce GTX 650,
GeForce GTX 880M, GeForce GTX 870M, GeForce GTX 780M, GeForce GTX 770M, GeForce GTX 765M, GeForce GTX 760M, GeForce GTX 680MX, GeForce GTX 680M, GeForce GTX 675MX, GeForce GTX 670MX, GeForce GTX 660M, GeForce GT 750M, GeForce GT 650M, GeForce GT 745M, GeForce GT 645M, GeForce GT 740M, GeForce GT 730M, GeForce GT 640M, GeForce GT 640M LE, GeForce GT 735M, GeForce GT 730M  | Quadro K5000, Quadro K4200, Quadro K4000, Quadro K2000, Quadro K2000D, Quadro K600, Quadro K420,
Quadro K500M, Quadro K510M, Quadro K610M, Quadro K1000M, Quadro K2000M, Quadro K1100M, Quadro K2100M, Quadro K3000M, Quadro K3100M, Quadro K4000M, Quadro K5000M, Quadro K4100M, Quadro K5100M,
NVS 510, Quadro 410  | Tesla K10, GRID K340, GRID K520, GRID K2  |
3.2  | GK20A  |  |  |  | Tegra K1,
Jetson TK1
3.5  | GK110, GK208  | GeForce GTX Titan Z, GeForce GTX Titan Black, GeForce GTX Titan, GeForce GTX 780 Ti, GeForce GTX 780, GeForce GT 640 (GDDR5), GeForce GT 630 v2, GeForce GT 730, GeForce GT 720, GeForce GT 710, GeForce GT 740M (64-bit, DDR3), GeForce GT 920M  | Quadro K6000, Quadro K5200  | Tesla K40, Tesla K20x, Tesla K20  |
3.7  | GK210  |  |  | Tesla K80  |
5.0  | Maxwell | GM107, GM108  | GeForce GTX 750 Ti, GeForce GTX 750, GeForce GTX 960M, GeForce GTX 950M, GeForce 940M, GeForce 930M, GeForce GTX 860M, GeForce GTX 850M, GeForce 845M, GeForce 840M, GeForce 830M  | Quadro K1200, Quadro K2200, Quadro K620, Quadro M2000M, Quadro M1000M, Quadro M600M, Quadro K620M, NVS 810  | Tesla M10  |
5.2  | GM200, GM204, GM206  | GeForce GTX Titan X, GeForce GTX 980 Ti, GeForce GTX 980, GeForce GTX 970, GeForce GTX 960, GeForce GTX 950, GeForce GTX 750 SE,
GeForce GTX 980M, GeForce GTX 970M, GeForce GTX 965M  | Quadro M6000 24GB, Quadro M6000, Quadro M5000, Quadro M4000, Quadro M2000, Quadro M5500,
Quadro M5000M, Quadro M4000M, Quadro M3000M  | Tesla M4, Tesla M40, Tesla M6, Tesla M60  |
5.3  | GM20B  |  |  |  | Tegra X1,
Jetson TX1,
Jetson Nano,
DRIVE CX,
DRIVE PX
6.0  | Pascal | GP100  |  | Quadro GP100  | Tesla P100  |
6.1  | GP102, GP104, GP106, GP107, GP108  | Nvidia TITAN Xp, Titan X,
GeForce GTX 1080 Ti, GTX 1080, GTX 1070 Ti, GTX 1070, GTX 1060,
GTX 1050 Ti, GTX 1050, GT 1030, GT 1010,
MX350, MX330, MX250, MX230, MX150, MX130, MX110  | Quadro P6000, Quadro P5000, Quadro P4000, Quadro P2200, Quadro P2000, Quadro P1000, Quadro P400, Quadro P500, Quadro P520, Quadro P600,
Quadro P5000 (mobile), Quadro P4000 (mobile), Quadro P3000 (mobile)  | Tesla P40, Tesla P6, Tesla P4  |
6.2  | GP10B[54] |  |  |  | Tegra X2, Jetson TX2, DRIVE PX 2
7.0  | Volta | GV100  | NVIDIA TITAN V  | Quadro GV100  | Tesla V100, Tesla V100S  |
7.2  | GV10B[55]

GV11B[56][57]

|  |  |  | Tegra Xavier,
Jetson Xavier NX,
Jetson AGX Xavier,
DRIVE AGX Xavier,
DRIVE AGX Pegasus,
Clara AGX
7.5  | Turing | TU102, TU104, TU106, TU116, TU117  | NVIDIA TITAN RTX,
GeForce RTX 2080 Ti, RTX 2080 Super, RTX 2080, RTX 2070 Super, RTX 2070, RTX 2060 Super, RTX 2060 12GB, RTX 2060,
GeForce GTX 1660 Ti, GTX 1660 Super, GTX 1660, GTX 1650 Super, GTX 1650, MX550, MX450  | Quadro RTX 8000, Quadro RTX 6000, Quadro RTX 5000, Quadro RTX 4000, T1000, T600, T400
T1200 (mobile), T600 (mobile), T500 (mobile), Quadro T2000 (mobile), Quadro T1000 (mobile)  | Tesla T4  |
8.0  | Ampere | GA100  |  |  | A100 80GB, A100 40GB, A30  |
8.6  | GA102, GA103, GA104, GA106, GA107  | GeForce RTX 3090 Ti, RTX 3090, RTX 3080 Ti, RTX 3080 12GB, RTX 3080, RTX 3070 Ti, RTX 3070, RTX 3060 Ti, RTX 3060, RTX 3050, RTX 3050 Ti (mobile), RTX 3050 (mobile), RTX 2050 (mobile), MX570  | RTX A6000, RTX A5500, RTX A5000, RTX A4500, RTX A4000, RTX A2000
RTX A5000 (mobile), RTX A4000 (mobile), RTX A3000 (mobile), RTX A2000 (mobile)  | A40, A16, A10, A2  |
8.7  | GA10B  |  |  |  | Jetson Orin Nano,
Jetson Orin NX,
Jetson AGX Orin,
DRIVE AGX Orin,
IGX Orin
8.9  | Ada Lovelace[58] | AD102, AD103, AD104, AD106, AD107  | GeForce RTX 4090, RTX 4080 Super, RTX 4080, RTX 4070 Ti Super, RTX 4070 Ti, RTX 4070 Super, RTX 4070, RTX 4060 Ti, RTX 4060, RTX 4050 (mobile)  | RTX 6000 Ada, RTX 5880 Ada, RTX 5000 Ada, RTX 4500 Ada, RTX 4000 Ada, RTX 4000 SFF Ada, RTX 2000 Ada, RTX 5000 Ada (mobile), RTX 4000 Ada (mobile), RTX 3500 Ada (mobile), RTX 2000 Ada (mobile)  | L40S, L40, L20, L4, L2  |
9.0  | Hopper | GH100  |  |  | H200, H100, GH200  |
10.0  | Blackwell | GB100  |  |  | B200, B100, GB200  |
10.1  |  |  |  |  | Jetson AGX Thor,
DRIVE AGX Thor
10.3  | GB200, G10  |  |  | B300, GB10  |
12.0  | GB202, GB203, GB205, GB206, GB207  | GeForce RTX 5090, RTX 5080, RTX 5070 Ti, RTX 5070, RTX 5060 Ti, RTX 5060, RTX 5050  | RTX PRO 6000 Blackwell, RTX PRO 5000 Blackwell, RTX PRO 4500 Blackwell, RTX PRO 4000 Blackwell  | B40  |
12.1  |  |  |  |  |
Compute
capability
(version)  | Micro-
architecture | GPUs  | GeForce | Quadro, NVS | Tesla/Datacenter | Tegra,
Jetson,
DRIVE

* – OEM-only products

## Version features and specifications

[edit]

Feature support (unlisted features are supported for all compute capabilities)  | Compute capability (version)

|

1.0, 1.1 | 1.2, 1.3 | 2.x | 3.0 | 3.2 | 3.5, 3.7, 5.x, 6.x, 7.0, 7.2 | 7.5 | 8.x | 9.0, 10.x, 12.x
Warp vote functions (__all(), __any())  | No  | Yes
Warp vote functions (__ballot())  | No  | Yes
Memory fence functions (__threadfence_system())
Synchronization functions (__syncthreads_count(), __syncthreads_and(), __syncthreads_or())
Surface functions
3D grid of thread blocks
Warp shuffle functions  | No  | Yes
Unified memory programming
Funnel shift  | No  | Yes
Dynamic parallelism  | No  | Yes
Uniform Datapath[59] | No  | Yes
Hardware-accelerated async-copy  | No  | Yes
Hardware-accelerated split arrive/wait barrier
Warp-level support for reduction ops
L2 cache residency management
DPX instructions for accelerated dynamic programming  | No  | Yes
Distributed shared memory
Thread block cluster
Tensor memory accelerator (TMA) unit
Feature support (unlisted features are supported for all compute capabilities)  | 1.0, 1.1 | 1.2, 1.3 | 2.x | 3.0 | 3.2 | 3.5, 3.7, 5.x, 6.x, 7.0, 7.2 | 7.5 | 8.x | 9.0, 10.x, 12.x
Compute capability (version)

[60]

### Data types

[edit]

#### Floating-point types

[edit]

Data type  | Supported vector types  | Storage Length Bits
(complete vector)  | Used Length Bits
(single value)  | Sign Bits  | Exponent Bits  | Mantissa Bits  | Comments

|
|
|
|
|
|
|

E2M1 = FP4  | e2m1x2 / e2m1x4  | 8 / 16  | 4  | 1  | 2  | 1  |
E2M3 = FP6 variant  | e2m3x2 / e2m3x4  | 16 / 32  | 6  | 1  | 2  | 3  |
E3M2 = FP6 variant  | e3m2x2 / e3m2x4  | 16 / 32  | 6  | 1  | 3  | 2  |
UE4M3  | ue4m3  | 8  | 7  | 0  | 4  | 3  | Used for scaling (E2M1 only)
E4M3 = FP8 variant  | e4m3 / e4m3x2 / e4m3x4  | 8 / 16 / 32  | 8  | 1  | 4  | 3  |
E5M2 = FP8 variant  | e5m2 / e5m2x2 / e5m2x4  | 8 / 16 / 32  | 8  | 1  | 5  | 2  | Exponent/range of FP16, fits into 8 bits
UE8M0  | ue8m0x2  | 16  | 8  | 0  | 8  | 0  | Used for scaling (any FP4 or FP6 or FP8 format)
FP16  | f16 / f16x2  | 16 / 32  | 16  | 1  | 5  | 10  |
BF16  | bf16 / bf16x2  | 16 / 32  | 16  | 1  | 8  | 7  | Exponent/range of FP32, fits into 16 bits
TF32  | tf32  | 32  | 19  | 1  | 8  | 10  | Exponent/range of FP32, mantissa/precision of FP16
FP32  | f32 / f32x2  | 32 / 64  | 32  | 1  | 8  | 23  |
FP64  | f64  | 64  | 64  | 1  | 11  | 52  |

#### Version support

[edit]

Data type  | Basic Operations  | Supported since
| Atomic Operations  | Supported since
for global memory  | Supported since
for shared memory

|
|
|
|
|

8-bit integer
signed/unsigned  | loading, storing, conversion  | 1.0  | —  | —
16-bit integer
signed/unsigned  | general operations  | 1.0  | atomicCAS()  | 3.5
32-bit integer
signed/unsigned  | general operations  | 1.0  | atomic functions  | 1.1  | 1.2
64-bit integer
signed/unsigned  | general operations  | 1.0  | atomic functions  | 1.2  | 2.0
any 128-bit trivially copyable type  | general operations  | No  | atomicExch, atomicCAS  | 9.0
16-bit floating point
FP16  | addition, subtraction,
multiplication, comparison,
warp shuffle functions, conversion  | 5.3  | half2 atomic addition  | 6.0
atomic addition  | 7.0
16-bit floating point
BF16  | addition, subtraction,
multiplication, comparison,
warp shuffle functions, conversion  | 8.0  | atomic addition  | 8.0
32-bit floating point  | general operations  | 1.0  | atomicExch()  | 1.1  | 1.2
atomic addition  | 2.0
32-bit floating point float2 and float4  | general operations  | No  | atomic addition  | 9.0
64-bit floating point  | general operations  | 1.3  | atomic addition  | 6.0

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.[61]

### Tensor cores

[edit]

FMA per cycle per tensor core[62] | Supported since  | 7.0  | 7.2  | 7.5 Workstation  | 7.5 Desktop  | 8.0  | 8.6 Workstation  | 8.7  | 8.6 Desktop  | 8.9 Desktop  | 8.9 Workstation  | 9.0  | 10.0  | 10.1  | 12.0

|
|
|
|
|
|
|
|
|
|
|
|
|
|
|

Data Type  | For dense matrices  | For sparse matrices  | 1st Gen (8x/SM)  | 1st Gen? (8x/SM)  | 2nd Gen (8x/SM)  | 3rd Gen (4x/SM)  | 4th Gen (4x/SM)  | 5th Gen (4x/SM)
1-bit values (AND)  | 8.0 as
experimental  | No  | No  | 4096  | 2048  | speed tbd
1-bit values (XOR)  | 7.5–8.9 as
experimental  | No  | 1024  | Deprecated or removed?
4-bit integers  | 8.0–8.9 as
experimental  | 256  | 1024  | 512
4-bit floating point FP4 (E2M1)  | 10.0  | No  | 4096  | tbd  | 512
6-bit floating point FP6 (E3M2 and E2M3)  | 10.0  | No  | 2048  | tbd
8-bit integers  | 7.2  | 8.0  | No  | 128  | 128  | 512  | 256  | 1024  | 2048  | 256
8-bit floating point FP8 (E4M3 and E5M2) with FP16 accumulate  | 8.9  | No  | 256
8-bit floating point FP8 (E4M3 and E5M2) with FP32 accumulate  | 128  | 128
16-bit floating point FP16 with FP16 accumulate  | 7.0  | 8.0  | 64  | 64  | 64  | 256  | 128  | 512  | 1024  | 128
16-bit floating point FP16 with FP32 accumulate  | 32  | 64  | 128  | 64
16-bit floating point BF16 with FP32 accumulate  | 7.5[63] | 8.0  | No  | 64[64]
32-bit (19 bits used) floating point TF32  | speed tbd (32?)[64] | 128  | 32  | 64  | 256  | 512  | 32
64-bit floating point  | 8.0  | No  | No  | 16  | speed tbd  | 32  | 16  | tbd

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.[65][66] [67] [68] [69] [70]

Tensor Core Composition  | 7.0  | 7.2, 7.5  | 8.0, 8.6  | 8.7  | 8.9  | 9.0

|
|
|
|
|
|

Dot Product Unit Width in FP16 units (in bytes)[71][72][73][74] | 4 (8)  | 8 (16)  | 4 (8)  | 16 (32)
Dot Product Units per Tensor Core  | 16  | 32
Tensor Cores per SM partition  | 2  | 1
Full throughput (Bytes/cycle)[75] per SM partition[76] | 256  | 512  | 256  |  | 1024
FP Tensor Cores: Minimum cycles for warp-wide matrix calculation  | 8  | 4  | 8  |  |
FP Tensor Cores: Minimum Matrix Shape for full throughput (Bytes)[77] | 2048  |  |
INT Tensor Cores: Minimum cycles for warp-wide matrix calculation  | No  | 4  |  |
INT Tensor Cores: Minimum Matrix Shape for full throughput (Bytes)  | No  | 1024  | 2048  | 1024  |  |

[78][79][80][81]

FP64 Tensor Core Composition  | 8.0  | 8.6  | 8.7  | 8.9  | 9.0

|
|
|
|
|

Dot Product Unit Width in FP64 units (in bytes)  | 4 (32)  | tbd  |  | 4 (32)
Dot Product Units per Tensor Core  | 4  | tbd  |  | 8
Tensor Cores per SM partition  | 1
Full throughput (Bytes/cycle)[75] per SM partition[76] | 128  | tbd  |  | 256
Minimum cycles for warp-wide matrix calculation  | 16  | tbd  |  |
Minimum Matrix Shape for full throughput (Bytes)[77] | 2048  |  |

### Technical specifications

[edit]

Technical specifications  | Compute capability (version)

|

1.0  | 1.1  | 1.2  | 1.3  | 2.x  | 3.0  | 3.2  | 3.5  | 3.7  | 5.0  | 5.2  | 5.3  | 6.0  | 6.1  | 6.2  | 7.0  | 7.2  | 7.5  | 8.0  | 8.6  | 8.7  | 8.9  | 9.0  | 10.x  | 12.x
Maximum number of resident grids per device
(concurrent kernel execution, can be lower for specific devices)  | 1  | 16  | 4  | 32  | 16  | 128  | 32  | 16  | 128  | 16  | 128
Maximum dimensionality of grid of thread blocks  | 2  | 3
Maximum x-dimension of a grid of thread blocks  | 65535  | 231 − 1
Maximum y-, or z-dimension of a grid of thread blocks  | 65535
Maximum dimensionality of thread block  | 3
Maximum x- or y-dimension of a block  | 512  | 1024
Maximum z-dimension of a block  | 64
Maximum number of threads per block  | 512  | 1024
Warp size  | 32
Maximum number of resident blocks per multiprocessor  | 8  | 16  | 32  | 16  | 32  | 16  | 24  | 32
Maximum number of resident warps per multiprocessor  | 24  | 32  | 48  | 64  | 32  | 64  | 48  | 64  | 48
Maximum number of resident threads per multiprocessor  | 768  | 1024  | 1536  | 2048  | 1024  | 2048  | 1536  | 2048  | 1536
Number of 32-bit regular registers per multiprocessor  | 8 K  | 16 K  | 32 K  | 64 K  | 128 K  | 64 K
Number of 32-bit uniform registers per multiprocessor  | No  | 2 K[82]

[83]

Maximum number of 32-bit registers per thread block  | 8 K  | 16 K  | 32 K  | 64 K  | 32 K  | 64 K  | 32 K  | 64 K  | 32 K  | 64 K
Maximum number of 32-bit regular registers per thread  | 124  | 63  | 255
Maximum number of 32-bit uniform registers per warp  | No  | 63[82]

[84]

Amount of shared memory per multiprocessor
(out of overall shared memory + L1 cache, where applicable)  | 16 KiB  | 16 / 48 KiB (of 64 KiB)  | 16 / 32 / 48 KiB (of 64 KiB)  | 80 / 96 / 112 KiB (of 128 KiB)  | 64 KiB  | 96 KiB  | 64 KiB  | 96 KiB  | 64 KiB  | 0 / 8 / 16 / 32 / 64 / 96 KiB (of 128 KiB)  | 32 / 64 KiB (of 96 KiB)  | 0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 KiB (of 192 KiB)  | 0 / 8 / 16 / 32 / 64 / 100 KiB (of 128 KiB)  | 0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 KiB (of 192 KiB)  | 0 / 8 / 16 / 32 / 64 / 100 KiB (of 128 KiB)  | 0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 / 196 / 228 KiB (of 256 KiB)  | 0 / 8 / 16 / 32 / 64 / 100 KiB (of 128 KiB)
Maximum amount of shared memory per thread block  | 16 KiB  | 48 KiB  | 96 KiB  | 48 KiB  | 64 KiB  | 163 KiB  | 99 KiB  | 163 KiB  | 99 KiB  | 227 KiB  | 99 KiB
Number of shared memory banks  | 16  | 32
Amount of local memory per thread  | 16 KiB  | 512 KiB
Constant memory size accessible by CUDA C/C++
(1 bank, PTX can access 11 banks, SASS can access 18 banks)  | 64 KiB
Cache working set per multiprocessor for constant memory  | 8 KiB  | 4 KiB  | 8 KiB
Cache working set per multiprocessor for texture memory  | 16 KiB per TPC  | 24 KiB per TPC  | 12 KiB  | 12 – 48 KiB[85] | 24 KiB  | 48 KiB  | 32 KiB[86] | 24 KiB  | 48 KiB  | 24 KiB  | 32 – 128 KiB  | 32 – 64 KiB  | 28 – 192 KiB  | 28 – 128 KiB  | 28 – 192 KiB  | 28 – 128 KiB  | 28 – 256 KiB
Maximum width for 1D texture reference bound to a CUDA
array  | 8192  | 65536  | 131072
Maximum width for 1D texture reference bound to linear
memory  | 227 | 228 | 227 | 228 | 227 | 228
Maximum width and number of layers for a 1D layered
texture reference  | 8192 × 512  | 16384 × 2048  | 32768 x 2048
Maximum width and height for 2D texture reference bound
to a CUDA array  | 65536 × 32768  | 65536 × 65535  | 131072 x 65536
Maximum width and height for 2D texture reference bound
to a linear memory  | 65000 x 65000  | 65536 x 65536  | 131072 x 65000
Maximum width and height for 2D texture reference bound
to a CUDA array supporting texture gather  | —  | 16384 x 16384  | 32768 x 32768
Maximum width, height, and number of layers for a 2D
layered texture reference  | 8192 × 8192 × 512  | 16384 × 16384 × 2048  | 32768 x 32768 x 2048
Maximum width, height and depth for a 3D texture
reference bound to linear memory or a CUDA array  | 20483 | 40963 | 163843
Maximum width (and height) for a cubemap texture reference  | —  | 16384  | 32768
Maximum width (and height) and number of layers
for a cubemap layered texture reference  | —  | 16384 × 2046  | 32768 × 2046
Maximum number of textures that can be bound to a
kernel  | 128  | 256
Maximum width for a 1D surface reference bound to a
CUDA array  | Not
supported  | 65536  | 16384  | 32768
Maximum width and number of layers for a 1D layered
surface reference  | 65536 × 2048  | 16384 × 2048  | 32768 × 2048
Maximum width and height for a 2D surface reference
bound to a CUDA array  | 65536 × 32768  | 16384 × 65536  | 131072 × 65536
Maximum width, height, and number of layers for a 2D
layered surface reference  | 65536 × 32768 × 2048  | 16384 × 16384 × 2048  | 32768 × 32768 × 2048
Maximum width, height, and depth for a 3D surface
reference bound to a CUDA array  | 65536 × 32768 × 2048  | 4096 × 4096 × 4096  | 16384 × 16384 × 16384
Maximum width (and height) for a cubemap surface reference bound to a CUDA array  | 32768  | 16384  | 32768
Maximum width and number of layers for a cubemap
layered surface reference  | 32768 × 2046  | 16384 × 2046  | 32768 × 2046
Maximum number of surfaces that can be bound to a
kernel  | 8  | 16  | 32
Maximum number of instructions per kernel  | 2 million  | 512 million
Maximum number of Thread Blocks per Thread Block Cluster[87] | No  | 16  | 8
Technical specifications  | 1.0  | 1.1  | 1.2  | 1.3  | 2.x  | 3.0  | 3.2  | 3.5  | 3.7  | 5.0  | 5.2  | 5.3  | 6.0  | 6.1  | 6.2  | 7.0  | 7.2  | 7.5  | 8.0  | 8.6  | 8.7  | 8.9  | 9.0  | 10.x  | 12.x
Compute capability (version)
[88][89]

### Multiprocessor architecture

[edit]

Architecture specifications  | Compute capability (version)

|

1.0  | 1.1  | 1.2  | 1.3  | 2.0  | 2.1  | 3.0  | 3.2  | 3.5  | 3.7  | 5.0  | 5.2  | 5.3  | 6.0  | 6.1  | 6.2  | 7.0  | 7.2  | 7.5  | 8.0  | 8.6  | 8.7  | 8.9  | 9.0  | 10.x  | 12.x
Number of ALU lanes for INT32 arithmetic operations  | 8  | 32  | 48  | 192[90] | 128  | 128  | 64  | 128  | 128  | 64  | 64  | 64  | 128
Number of ALU lanes for any INT32 or FP32 arithmetic operation  | —  | —
Number of ALU lanes for FP32 arithmetic operations  | 64  | 64  | 128  | 128
Number of ALU lanes for FP16x2 arithmetic operations  | No  | 1  | 128[91] | 128[92] | 64[93]
Number of ALU lanes for FP64 arithmetic operations  | No  | 1  | 16 by FP32[94] | 4 by FP32[95] | 8  | 8 / 64[96] | 64  | 4[97] | 32  | 4  | 32  | 2  | 32  | 2  | 64  | 2
Number of Load/Store Units  | 4 per 2 SM  | 8 per 2 SM  | 8 per 2 SM / 3 SM[96] | 8 per 3 SM  | 16  | 32  | 16  | 32  | 16  | 32
Number of special function units for single-precision floating-point transcendental functions  | 2[98] | 4  | 8  | 32  | 16  | 32  | 16
Number of texture mapping units (TMU)  | 4 per 2 SM  | 8 per 2 SM  | 8 per 2 / 3SM[96] | 8 per 3 SM  | 4  | 4 / 8[96] | 16  | 8  | 16  | 8  | 4
Number of ALU lanes for uniform INT32 arithmetic operations  | No  | 2[99] |
Number of tensor cores  | No  | 8 (1st gen.)[100] | 0 / 8[96] (2nd gen.)  | 4 (3rd gen.)  | 4 (4th gen.)
Number of raytracing cores  | No  | 0 / 1[96] (1st gen.)  | No  | 1 (2nd gen.)  | No  | 1 (3rd gen.)  | No
Number of SM Partitions = Processing Blocks[101] | 1  | 4  | 2  | 4
Number of warp schedulers per SM partition  | 1  | 2  | 4  | 1
Max number of new instructions issued each cycle by a single scheduler[102] | 2[103] | 1  | 2[104] | 2  | 1
Size of unified memory for data cache and shared memory  | 16 KiB[105] | 16 KiB[105] | 64 KiB  | 128 KiB  | 64 KiB SM + 24 KiB L1 (separate)[106] | 96 KiB SM + 24 KiB L1 (separate)[106] | 64 KiB SM + 24 KiB L1 (separate)[106] | 64 KiB SM + 24 KiB L1 (separate)[106] | 96 KiB SM + 24 KiB L1 (separate)[106] | 64 KiB SM + 24 KiB L1 (separate)[106] | 128 KiB  | 96 KiB[107] | 192 KiB  | 128 KiB  | 192 KiB  | 128 KiB  | 256 KiB
Size of L3 instruction cache per GPU  |  | 32 KiB[108] |  | use L2 Data Cache
Size of L2 instruction cache per Texture Processor Cluster (TPC)  |  | 8 KiB  |
Size of L1.5 instruction cache per SM[109] |  | 4 KiB  |  |  | 32 KiB  |  | 32 KiB  | 48 KiB[86] | 128 KiB  | 32 KiB  |  | 128 KiB  |  | ~46 KiB[110] | 128 KiB[111] |
Size of L1 instruction cache per SM  |  |  | 8 KiB  |  | 8 KiB  |
Size of L0 instruction cache per SM partition  | only 1 partition per SM  | No  | 12 KiB  |  | 16 KiB?[112] | 32 KiB  |
Instruction Width[109] | 32 bits instructions and 64 bits instructions[113] | 64 bits instructions + 64 bits control logic every 7 instructions  | 64 bits instructions + 64 bits control logic every 3 instructions  | 128 bits combined instruction and control logic
Memory Bus Width per Memory Partition in bits  | 64 ((G)DDR)  | 32 ((G)DDR)  | 512 (HBM)  | 32 ((G)DDR)  | 512 (HBM)  | 32 ((G)DDR)  | 512 (HBM)  | 32 ((G)DDR)  | 512 (HBM)  | 32 ((G)DDR)
L2 Cache per Memory Partition  | 16 KiB[114] | 32 KiB[114] | 128 KiB  | 256 KiB  | 1 MiB  | 512 KiB  | 128 KiB  | 512 KiB  | 256 KiB  | 128 KiB  | 768 KiB  | 64 KiB  | 512 KiB  | 4 MiB  | 512 KiB  | 8 MiB[115] | 5 MiB  | 6.25 MiB  | 8 MiB[116]
Number of Render Output Units (ROP) per memory partition (or per GPC in later models)  | 4  | 8  | 4  | 8  | 16  | 8  | 12  | 8  | 4  | 16  | 2  | 8  | 16  | 16 per GPC  | 3 per GPC  | 16 per GPC
Architecture specifications  | 1.0  | 1.1  | 1.2  | 1.3  | 2.0  | 2.1  | 3.0  | 3.2  | 3.5  | 3.7  | 5.0  | 5.2  | 5.3  | 6.0  | 6.1  | 6.2  | 7.0  | 7.2  | 7.5  | 8.0  | 8.6  | 8.7  | 8.9  | 9.0  | 10.x  | 12.x
Compute capability (version)

For more information read the Nvidia CUDA C++ Programming Guide.[117]

## Usages of CUDA architecture

[edit]

* Accelerated rendering of 3D graphics
* Accelerated interconversion of video file formats
* Accelerated encryption, decryption and compression
* Bioinformatics, e.g. NGS DNA sequencing BarraCUDA[118]
* Distributed calculations, such as predicting the native conformation of proteins
* Medical analysis simulations, for example virtual reality based on CT and MRI scan images
* Physical simulations,[119] particularly in fluid dynamics
* Neural network training in machine learning problems
* Large Language Model inference
* Face recognition
* Volunteer computing projects, such as SETI@home and other projects using BOINC software
* Molecular dynamics
* Mining cryptocurrencies
* Structure from motion (SfM) software

## Comparison with competitors

[edit]

CUDA competes with other GPU computing stacks: Intel OneAPI and AMD ROCm.

Whereas Nvidia's CUDA is closed-source, Intel's OneAPI and AMD's ROCm are open source.

### Intel OneAPI

[edit]

Main article: OneAPI (compute acceleration)

oneAPI is an initiative based in open standards, created to support software development for multiple hardware architectures.[120] The oneAPI libraries must implement open specifications that are discussed publicly by the Special Interest Groups, offering the possibility for any developer or organization to implement their own versions of oneAPI libraries.[121][122]

Originally made by Intel, other hardware adopters include Fujitsu and Huawei.

#### Unified Acceleration Foundation (UXL)

[edit]

Unified Acceleration Foundation (UXL) is a new technology consortium working on the continuation of the OneAPI initiative, with the goal to create a new open standard accelerator software ecosystem, related open standards and specification projects through Working Groups and Special Interest Groups (SIGs). The goal is to offer open alternatives to Nvidia's CUDA. The main companies behind it are Intel, Google, ARM, Qualcomm, Samsung, Imagination, and VMware.[123]

### AMD ROCm

[edit]

Main article: ROCm

ROCm[124] is an open source software stack for graphics processing unit (GPU) programming from Advanced Micro Devices (AMD).

## See also

[edit]

* SYCL – an open standard from Khronos Group for programming a variety of platforms, including GPUs, with single-source modern C++, similar to higher-level CUDA Runtime API (single-source)
* BrookGPU – the Stanford University graphics group's compiler
* Array programming
* Parallel computing
* Stream processing
* rCUDA – an API for computing on remote computers
* Molecular modeling on GPUs
* Vulkan – low-level, high-performance 3D graphics and computing API
* OptiX – ray tracing API by NVIDIA
* CUDA binary (cubin) – a type of fat binary
* Numerical Library Collection – by NEC for their vector processor

## References

[edit]

1. ^ "NVIDIA® CUDA™ Unleashes Power of GPU Computing - Press Release". nvidia.com. Archived from the original on 29 March 2007. Retrieved 26 January 2025.
2. ^ a b Shah, Agam. "Nvidia not totally against third parties making CUDA chips". www.theregister.com. Retrieved 2024-04-25.
3. ^ "Nvidia CUDA Home Page". 18 July 2017.
4. ^ Shimpi, Anand Lal; Wilson, Derek (November 8, 2006). "Nvidia's GeForce 8800 (G80): GPUs Re-architected for DirectX 10". AnandTech. Retrieved May 16, 2015.
5. ^ "Introduction — nsight-visual-studio-edition 12.6 documentation". docs.nvidia.com. Retrieved 2024-10-10.
6. ^ a b Abi-Chahla, Fedy (June 18, 2008). "Nvidia's CUDA: The End of the CPU?". Tom's Hardware. Retrieved May 17, 2015.
7. ^ Jones, Stephen (2025-04-22). What is CUDA? (Video). Computerphile. Retrieved 2025-07-24 – via YouTube.
8. ^ Zunitch, Peter (2018-01-24). "CUDA vs. OpenCL vs. OpenGL". Videomaker. Retrieved 2018-09-16.
9. ^ "OpenCL". NVIDIA Developer. 2013-04-24. Retrieved 2019-11-04.
10. ^ a b Cosgrove, Emma. "Ian Buck built Nvidia's secret weapon. He may spend the rest of his career defending it". Business Insider. Retrieved 2025-07-24.
11. ^ Witt, Stephen (2023-11-27). "How Jensen Huang's Nvidia Is Powering the A.I. Revolution". The New Yorker. ISSN 0028-792X. Retrieved 2023-12-10.
12. ^ "CUDA LLVM Compiler". 7 May 2012.
13. ^ First OpenCL demo on a GPU on YouTube
14. ^ DirectCompute Ocean Demo Running on Nvidia CUDA-enabled GPU on YouTube
15. ^ Vasiliadis, Giorgos; Antonatos, Spiros; Polychronakis, Michalis; Markatos, Evangelos P.; Ioannidis, Sotiris (September 2008). "Gnort: High Performance Network Intrusion Detection Using Graphics Processors" (PDF). Recent Advances in Intrusion Detection. Lecture Notes in Computer Science. Vol. 5230\. pp. 116–134\. doi:10.1007/978-3-540-87403-4_7. ISBN 978-3-540-87402-7.
16. ^ Schatz, Michael C.; Trapnell, Cole; Delcher, Arthur L.; Varshney, Amitabh (2007). "High-throughput sequence alignment using Graphics Processing Units". BMC Bioinformatics. 8: 474. doi:10.1186/1471-2105-8-474. PMC 2222658. PMID 18070356.
17. ^ Manavski, Svetlin A.; Giorgio, Valle (2008). "CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment". BMC Bioinformatics. 10 (Suppl 2): S10. doi:10.1186/1471-2105-9-S2-S10. PMC 2323659. PMID 18387198.
18. ^ "Pyrit – Google Code".
19. ^ "Use your Nvidia GPU for scientific computing". BOINC. 2008-12-18. Archived from the original on 2008-12-28. Retrieved 2017-08-08.
20. ^ "Nvidia CUDA Software Development Kit (CUDA SDK) – Release Notes Version 2.0 for MAC OS X". Archived from the original on 2009-01-06.
21. ^ "CUDA 1.1 – Now on Mac OS X". February 14, 2008. Archived from the original on November 22, 2008.
22. ^ "CUDA 11 Features Revealed". 14 May 2020.
23. ^ "CUDA Toolkit 11.1 Introduces Support for GeForce RTX 30 Series and Quadro RTX Series GPUs". 23 September 2020.
24. ^ "Enhancing Memory Allocation with New NVIDIA CUDA 11.2 Features". 16 December 2020.
25. ^ "Exploring the New Features of CUDA 11.3". 16 April 2021.
26. ^ Silberstein, Mark; Schuster, Assaf; Geiger, Dan; Patney, Anjul; Owens, John D. (2008). "Efficient computation of sum-products on GPUs through software-managed cache" (PDF). Proceedings of the 22nd annual international conference on Supercomputing – ICS '08 (PDF). Proceedings of the 22nd annual international conference on Supercomputing – ICS '08. pp. 309–318\. doi:10.1145/1375527.1375572. ISBN 978-1-60558-158-3.
27. ^ "CUDA C Programming Guide v8.0" (PDF). nVidia Developer Zone. January 2017. p. 19. Retrieved 22 March 2017.
28. ^ "NVCC forces c++ compilation of .cu files". 29 November 2011.
29. ^ Whitehead, Nathan; Fit-Florea, Alex. "Precision & Performance: Floating Point and IEEE 754 Compliance for Nvidia GPUs" (PDF). Nvidia. Retrieved November 18, 2014.
30. ^ "CUDA-Enabled Products". CUDA Zone. Nvidia Corporation. Retrieved 2008-11-03.
31. ^ "Coriander Project: Compile CUDA Codes To OpenCL, Run Everywhere". Phoronix.
32. ^ Perkins, Hugh (2017). "cuda-on-cl" (PDF). IWOCL. Retrieved August 8, 2017.
33. ^ "hughperkins/coriander: Build NVIDIA® CUDA™ code for OpenCL™ 1.2 devices". GitHub. May 6, 2019.
34. ^ "CU2CL Documentation". chrec.cs.vt.edu.
35. ^ "GitHub – vosen/ZLUDA". GitHub.
36. ^ Larabel, Michael (2024-02-12), "AMD Quietly Funded A Drop-In CUDA Implementation Built On ROCm: It's Now Open-Source", Phoronix, retrieved 2024-02-12
37. ^ "GitHub – chip-spv/chipStar". GitHub.
38. ^ "PyCUDA".
39. ^ "pycublas". Archived from the original on 2009-04-20. Retrieved 2017-08-08.
40. ^ "CuPy". Retrieved 2020-01-08.
41. ^ "NVIDIA CUDA Programming Guide. Version 1.0" (PDF). June 23, 2007.
42. ^ "NVIDIA CUDA Programming Guide. Version 2.1" (PDF). December 8, 2008.
43. ^ "NVIDIA CUDA Programming Guide. Version 2.2" (PDF). April 2, 2009.
44. ^ "NVIDIA CUDA Programming Guide. Version 2.2.1" (PDF). May 26, 2009.
45. ^ "NVIDIA CUDA Programming Guide. Version 2.3.1" (PDF). August 26, 2009.
46. ^ "NVIDIA CUDA Programming Guide. Version 3.0" (PDF). February 20, 2010.
47. ^ "NVIDIA CUDA C Programming Guide. Version 3.1.1" (PDF). July 21, 2010.
48. ^ "NVIDIA CUDA C Programming Guide. Version 3.2" (PDF). November 9, 2010.
49. ^ "CUDA 11.0 Release Notes". NVIDIA Developer.
50. ^ "CUDA 11.1 Release Notes". NVIDIA Developer.
51. ^ "CUDA 11.5 Release Notes". NVIDIA Developer.
52. ^ "CUDA 11.8 Release Notes". NVIDIA Developer.
53. ^ "NVIDIA Quadro NVS 420 Specs". TechPowerUp GPU Database. 25 August 2023.
54. ^ Larabel, Michael (March 29, 2017). "NVIDIA Rolls Out Tegra X2 GPU Support In Nouveau". Phoronix. Retrieved August 8, 2017.
55. ^ Nvidia Xavier Specs on TechPowerUp (preliminary)
56. ^ "Welcome — Jetson LinuxDeveloper Guide 34.1 documentation".
57. ^ "NVIDIA Bringing up Open-Source Volta GPU Support for Their Xavier SoC".
58. ^ "NVIDIA Ada Lovelace Architecture".
59. ^ Dissecting the Turing GPU Architecture through Microbenchmarking
60. ^ "H.1. Features and Technical Specifications – Table 13. Feature Support per Compute Capability". docs.nvidia.com. Retrieved 2020-09-23.
61. ^ "CUDA C++ Programming Guide".
62. ^ Fused-Multiply-Add, actually executed, Dense Matrix
63. ^ as SASS since 7.5, as PTX since 8.0
64. ^ a b unofficial support in SASS
65. ^ "Technical brief. NVIDIA Jetson AGX Orin Series" (PDF). nvidia.com. Retrieved 5 September 2023.
66. ^ "NVIDIA Ampere GA102 GPU Architecture" (PDF). nvidia.com. Retrieved 5 September 2023.
67. ^ Luo, Weile; Fan, Ruibo; Li, Zeyu; Du, Dayou; Wang, Qiang; Chu, Xiaowen (2024). "Benchmarking and Dissecting the Nvidia Hopper GPU Architecture". arXiv:2402.13499v1 [cs.AR].
68. ^ "Datasheet NVIDIA A40" (PDF). nvidia.com. Retrieved 27 April 2024.
69. ^ "NVIDIA AMPERE GA102 GPU ARCHITECTURE" (PDF). 27 April 2024.
70. ^ "Datasheet NVIDIA L40" (PDF). 27 April 2024.
71. ^ In the Whitepapers the Tensor Core cube diagrams represent the Dot Product Unit Width into the height (4 FP16 for Volta and Turing, 8 FP16 for A100, 4 FP16 for GA102, 16 FP16 for GH100). The other two dimensions represent the number of Dot Product Units (4x4 = 16 for Volta and Turing, 8x4 = 32 for Ampere and Hopper). The resulting gray blocks are the FP16 FMA operations per cycle. Pascal without Tensor core is only shown for speed comparison as is Volta V100 with non-FP16 datatypes.
72. ^ "NVIDIA Turing Architecture Whitepaper" (PDF). nvidia.com. Retrieved 5 September 2023.
73. ^ "NVIDIA Tensor Core GPU" (PDF). nvidia.com. Retrieved 5 September 2023.
74. ^ "NVIDIA Hopper Architecture In-Depth". 22 March 2022.
75. ^ a b shape x converted operand size, e.g. 2 tensor cores x 4x4x4xFP16/cycle = 256 Bytes/cycle
76. ^ a b = product first 3 table rows
77. ^ a b = product of previous 2 table rows; shape: e.g. 8x8x4xFP16 = 512 Bytes
78. ^ Sun, Wei; Li, Ang; Geng, Tong; Stuijk, Sander; Corporaal, Henk (2023). "Dissecting Tensor Cores via Microbenchmarks: Latency, Throughput and Numeric Behaviors". IEEE Transactions on Parallel and Distributed Systems. 34 (1): 246–261\. arXiv:2206.02874. doi:10.1109/tpds.2022.3217824. S2CID 249431357.
79. ^ "Parallel Thread Execution ISA Version 7.7".
80. ^ Raihan, Md Aamir; Goli, Negar; Aamodt, Tor (2018). "Modeling Deep Learning Accelerator Enabled GPUs". arXiv:1811.08309 [cs.MS].
81. ^ "NVIDIA Ada Lovelace Architecture".
82. ^ a b Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv:1903.07486 [cs.DC].
83. ^ Burgess, John (2019). "RTX ON – The NVIDIA TURING GPU". 2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27\. doi:10.1109/HOTCHIPS.2019.8875651. ISBN 978-1-7281-2089-8. S2CID 204822166.
84. ^ Burgess, John (2019). "RTX ON – The NVIDIA TURING GPU". 2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27\. doi:10.1109/HOTCHIPS.2019.8875651. ISBN 978-1-7281-2089-8. S2CID 204822166.
85. ^ dependent on device
86. ^ a b "Tegra X1". 9 January 2015.
87. ^ NVIDIA H100 Tensor Core GPU Architecture
88. ^ H.1. Features and Technical Specifications – Table 14. Technical Specifications per Compute Capability
89. ^ NVIDIA Hopper Architecture In-Depth
90. ^ can only execute 160 integer instructions according to programming guide
91. ^ 128 according to [1]. 64 from FP32 + 64 separate units?
92. ^ 64 by FP32 cores and 64 by flexible FP32/INT cores.
93. ^ "CUDA C++ Programming Guide".
94. ^ 32 FP32 lanes combine to 16 FP64 lanes. Maybe lower depending on model.
95. ^ only supported by 16 FP32 lanes, they combine to 4 FP64 lanes
96. ^ a b c d e f depending on model
97. ^ Effective speed, probably over FP32 ports. No description of actual FP64 cores.
98. ^ Can also be used for integer additions and comparisons
99. ^ 2 clock cycles/instruction for each SM partition Burgess, John (2019). "RTX ON – The NVIDIA TURING GPU". 2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27\. doi:10.1109/HOTCHIPS.2019.8875651. ISBN 978-1-7281-2089-8. S2CID 204822166.
100. ^ Durant, Luke; Giroux, Olivier; Harris, Mark; Stam, Nick (May 10, 2017). "Inside Volta: The World's Most Advanced Data Center GPU". Nvidia developer blog.
101. ^ The schedulers and dispatchers have dedicated execution units unlike with Fermi and Kepler.
102. ^ Dispatching can overlap concurrently, if it takes more than one cycle (when there are less execution units than 32/SM Partition)
103. ^ Can dual issue MAD pipe and SFU pipe
104. ^ No more than one scheduler can issue 2 instructions at once. The first scheduler is in charge of warps with odd IDs. The second scheduler is in charge of warps with even IDs.
105. ^ a b shared memory only, no data cache
106. ^ a b c d e f shared memory separate, but L1 includes texture cache
107. ^ "H.6.1. Architecture". docs.nvidia.com. Retrieved 2019-05-13.
108. ^ "Demystifying GPU Microarchitecture through Microbenchmarking" (PDF).
109. ^ a b Jia, Zhe; Maggioni, Marco; Staiger, Benjamin; Scarpazza, Daniele P. (2018). "Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking". arXiv:1804.06826 [cs.DC].
110. ^ Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv:1903.07486 [cs.DC].
111. ^ "Dissecting the Ampere GPU Architecture through Microbenchmarking".
112. ^ Note that Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking". arXiv:1903.07486 [cs.DC]. disagrees and states 2 KiB L0 instruction cache per SM partition and 16 KiB L1 instruction cache per SM
113. ^ "asfermi Opcode". GitHub.
114. ^ a b for access with texture engine only
115. ^ 25% disabled on RTX 4060, RTX 4070, RTX 4070 Ti and RTX 4090
116. ^ 25% disabled on RTX 5070 Ti and RTX 5090
117. ^ "CUDA C++ Programming Guide, Compute Capabilities". docs.nvidia.com. Retrieved 2025-02-06.
118. ^ "nVidia CUDA Bioinformatics: BarraCUDA". BioCentric. 2019-07-19. Retrieved 2019-10-15.
119. ^ "Part V: Physics Simulation". NVIDIA Developer. Retrieved 2020-09-11.
120. ^ "oneAPI Programming Model". oneAPI.io. Retrieved 2024-07-27.
121. ^ "Specifications | oneAPI". oneAPI.io. Retrieved 2024-07-27.
122. ^ "oneAPI Specification — oneAPI Specification 1.3-rev-1 documentation". oneapi-spec.uxlfoundation.org. Retrieved 2024-07-27.
123. ^ "Exclusive: Behind the plot to break Nvidia's grip on AI by targeting software". Reuters. Retrieved 2024-04-05.
124. ^ "Question: What does ROCm stand for? · Issue #1628 · RadeonOpenCompute/ROCm". Github.com. Retrieved January 18, 2022.

## Further reading

[edit]

* Buck, Ian; Foley, Tim; Horn, Daniel; Sugerman, Jeremy; Fatahalian, Kayvon; Houston, Mike; Hanrahan, Pat (2004-08-01). "Brook for GPUs: stream computing on graphics hardware". ACM Transactions on Graphics. 23 (3): 777–786\. doi:10.1145/1015706.1015800. ISSN 0730-0301.
* Nickolls, John; Buck, Ian; Garland, Michael; Skadron, Kevin (2008-03-01). "Scalable Parallel Programming with CUDA: Is CUDA the parallel programming model that application developers have been waiting for?". Queue. 6 (2): 40–53\. doi:10.1145/1365490.1365500. ISSN 1542-7730.

## External links

[edit]

* Official website

* v
* t
* e

Nvidia

GeForce (List of GPUs)

| Fixed pixel pipeline|

| Pre-GeForce|

* NV1
* NV2

* RIVA 128
* RIVA TNT
* TNT2

|

*  GeForce 256
* 2
* 4 MX

Vertex and pixel shaders|

* GeForce 3
* 4 Ti
* FX
* 6
* 7

Unified shaders|

* GeForce 8
* 9
* 100
* 200
* 300
* 400
* 500

Unified shaders & NUMA|

* GeForce 600
* 700
* 800M
* 900
* 10
* 16

Ray tracing & Tensor Cores|

* GeForce 20
* 30
* 40
* 50

Software and technologies

| Multimedia acceleration|

* NVENC (video encoding)
* NVDEC (video decoding)
* PureVideo (video decoding)

|

Software|

* Cg (shading language)
* CUDA
* Nvidia GameWorks
* OptiX (ray tracing API)
* PhysX (physics SDK)
* Nvidia Omniverse (3D graphics)
* Nvidia RTX (ray tracing platform)
* Nvidia System Tools
* VDPAU (video decode API)

Technologies|

* Nvidia 3D Vision (stereo 3D)
* Nvidia G-Sync (variable refresh rate)
* Nvidia Optimus (GPU switching)
* Nvidia Surround (multi-monitor)
* MXM (module/socket)
* SXM (module/socket)
* NVLink (protocol)
* Scalable Link Interface (multi-GPU)
* TurboCache (framebuffer in system memory)
* Video Super Resolution (live video upscaling)

GPU microarchitectures|

* Celsius
* Kelvin
* Rankine
* Curie
* Tesla
* Fermi
* Kepler
* Maxwell
* Pascal
* Volta
* Turing
* Ampere
* Hopper
* Ada Lovelace
* Blackwell
* Rubin
* Feynman

Other products

| Graphics Workstation cards|

* Nvidia Quadro
* Quadro Plex

|

GPGPU|

* Nvidia Tesla
* DGX

Console components|

* NV2A (Xbox)
* RSX 'Reality Synthesizer' (PlayStation 3)
* Tegra NX-SoC (Nintendo Switch)

Nvidia Shield|

* Shield Portable
* Shield Tablet
* Shield Android TV
* GeForce Now

SoCs and embedded|

* GoForce
* Drive
* Jetson
* Tegra

CPUs|

* Project Denver

Computer chipsets|

* nForce

Company

| Key people|

* Jen-Hsun Huang
* Chris Malachowsky
* Curtis Priem
* David Kirk
* Bill Dally
* Debora Shoquist
* Ranga Jayaraman
* Jonah M. Alben

|

Acquisitions|

* 3dfx Interactive
* Ageia
* ULi
* Bright Computing
* Cumulus Networks
* DeepMap
* Icera
* Mellanox Technologies
* Mental Images
* PortalPlayer
* Exluna
* MediaQ
* Stexar

* v
* t
* e

Processor technologies

Models|

* Abstract machine
* Stored-program computer
* Finite-state machine
* with datapath
* Hierarchical
* Deterministic finite automaton
* Queue automaton
* Cellular automaton
* Quantum cellular automaton
* Turing machine
* Alternating Turing machine
* Universal
* Post–Turing
* Quantum
* Nondeterministic Turing machine
* Probabilistic Turing machine
* Hypercomputation
* Zeno machine
* Belt machine
* Stack machine
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load–store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* Orthogonal instruction set
* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* VISC architecture
* Quantum computing
* Comparison
* Addressing modes

|

Instruction
sets|

* Motorola 68000 series
* VAX
* PDP-11
* x86
* ARM
* Stanford MIPS
* MIPS
* MIPS-X
* Power
* POWER
* PowerPC
* Power ISA
* Clipper architecture
* SPARC
* SuperH
* DEC Alpha
* ETRAX CRIS
* M32R
* Unicore
* Itanium
* OpenRISC
* RISC-V
* MicroBlaze
* LMC
* System/3x0
* S/360
* S/370
* S/390
* z/Architecture
* Tilera ISA
* VISC architecture
* Epiphany architecture
* Others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Scoreboarding
* Tomasulo's algorithm
* Reservation station
* Re-order buffer
* Register renaming
* Wide-issue

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Simultaneous and heterogenous
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* Array processing (SIMT)
* Pipelined processing
* Associative processing
* SWAR
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Tile processor
* Coprocessor
* PAL
* ASIC
* FPGA
* FPOA
* CPLD
* Multi-chip module (MCM)
* System in a package (SiP)
* Package on a package (PoP)

| By application|

* Embedded system
* Microprocessor
* Microcontroller
* Mobile
* Ultra-low-voltage
* ASIP
* Soft microprocessor

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Cypress PSoC
* Network on a chip (NoC)

Hardware
accelerators|

* Coprocessor
* AI accelerator
* Graphics processing unit (GPU)
* Image processor
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor Processing Unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 4-bit
* 8-bit
* 12-bit
* 15-bit
* 16-bit
* 24-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* bit slicing
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* Scratchpad memory
* Data cache
* Instruction cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional
units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Branch predictor
* Branch target predictor
* Integrated memory controller (IMC)
* Memory management unit
* Instruction decoder

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Memory address register
* Program counter

Control unit|

* Hardwired control unit
* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum-addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model
* Pin grid array
* Chip carrier

* v
* t
* e

Parallel computing

General|

* Distributed computing
* Parallel computing
* Parallel algorithm
* Massively parallel
* Cloud computing
* High-performance computing
* Multiprocessing
* Manycore processor
* GPGPU
* Computer network
* Systolic array

Levels|

* Bit
* Instruction
* Thread
* Task
* Data
* Memory
* Loop
* Pipeline

Multithreading|

* Temporal
* Simultaneous (SMT)
* Simultaneous and heterogenous
* Speculative (SpMT)
* Preemptive
* Cooperative
* Clustered multi-thread (CMT)
* Hardware scout

Theory|

* PRAM model
* PEM model
* Analysis of parallel algorithms
* Amdahl's law
* Gustafson's law
* Cost efficiency
* Karp–Flatt metric
* Slowdown
* Speedup

Elements|

* Process
* Thread
* Fiber
* Instruction window
* Array

Coordination|

* Multiprocessing
* Memory coherence
* Cache coherence
* Cache invalidation
* Barrier
* Synchronization
* Application checkpointing

Programming|

* Stream processing
* Dataflow programming
* Models
* Implicit parallelism
* Explicit parallelism
* Concurrency
* Non-blocking algorithm

Hardware|

* Flynn's taxonomy
* SISD
* SIMD
* Array processing (SIMT)
* Pipelined processing
* Associative processing
* MISD
* MIMD
* Dataflow architecture
* Pipelined processor
* Superscalar processor
* Vector processor
* Multiprocessor
* symmetric
* asymmetric
* Memory
* shared
* distributed
* distributed shared
* UMA
* NUMA
* COMA
* Massively parallel computer
* Computer cluster
* Beowulf cluster
* Grid computer
* Hardware acceleration

APIs|

* Ateji PX
* Boost
* Chapel
* HPX
* Charm++
* Cilk
* Coarray Fortran
* CUDA
* Dryad
* C++ AMP
* Global Arrays
* GPUOpen
* MPI
* OpenMP
* OpenCL
* OpenHMPP
* OpenACC
* Parallel Extensions
* PVM
* pthreads
* RaftLib
* ROCm
* UPC
* TBB
* ZPL

Problems|

* Automatic parallelization
* Deadlock
* Deterministic algorithm
* Embarrassingly parallel
* Parallel slowdown
* Race condition
* Software lockout
* Scalability
* Starvation

*  Category: Parallel computing

Authority control databases

National|

* Germany
* United States
* Israel

Other|

* Yale LUX

*[v]: View this template
*[t]: Discuss this template
*[e]: Edit this template