Launch Vehicle Digital Computer

Computer of the Saturn V rocket

LVDC from Instrument Unit technical manual

The Launch Vehicle Digital Computer (LVDC) was a computer that provided the autopilot for the Saturn V rocket from launch, through Canary Islands orbit insertion, and the trans-lunar injection burn that would send the Apollo spacecraft to the Moon. Designed and manufactured by IBM's Electronics Systems Center in Owego, New York, it was one of the major components of the Instrument Unit, fitted to the S-IVB stage of the Saturn V and Saturn IB rockets. The LVDC also supported pre- and post-launch checkout of the Saturn hardware. It was used in conjunction with the Launch Vehicle Data Adaptor (LVDA) which performed signal conditioning from the sensor inputs to the computer from the launch vehicle.

## Hardware

[edit]

The LVDC was capable of executing 12190 instructions per second. For comparison, as of 2022, researchers at the University of California created a chip capable of running at 1.78 trillion instructions per second,[1] 146 million times faster.

LVDC with cover removed. LVDC closeup

Its master clock ran at 2.048 MHz, but operations were performed bit-serially, with 4 cycles required to process each bit, 14 bits per instruction phase, and 3 phases per instruction, for a basic instruction cycle time of 82 μs (168 clock cycles) for a simple add. A few instructions (such as multiply or divide) took several multiples of the basic instruction cycle to execute.

Memory was in the form of 13-bit syllables, each with a 14th parity bit.[2] Instructions were one syllable in size, while data words were two syllables (26 bits). Main memory was random access magnetic core, in the form of 4,096-word memory modules. Up to 8 modules provided a maximum of 32,768 words of memory. Ultrasonic delay lines provided temporary storage.

For reliability, the LVDC used triple-redundant logic and a voting system. The computer included three identical logic systems. Each logic system was split into a seven-stage pipeline. At each stage in the pipeline, a voting system would take a majority vote on the results, with the most popular result being passed on to the next stage in all pipelines. This meant that, for each of the seven stages, one module in any one of the three pipelines could fail, and the LVDC would still produce the correct results.[3] The result was an estimated reliability of 99.6% over 250 hours of operation, which was far more than the few hours required for an Apollo mission.

With four memory modules, giving a total capacity of 16,384 words, the computer weighed 72.5 lb (32.9 kg), was 29.5 by 12.5 by 10.5 inches (750 mm × 320 mm × 270 mm) in size and consumed 137W.

Apollo Saturn V analog Flight Control Computer Unit FCC

The LVDC communicated digitally with a Launch Vehicle Data adapter (LVDA). The LVDA converted analog-to-digital and digital-to-analog with a Flight Control Computer (FCC). The FCC was an analog computer.

## Software architecture and algorithms

[edit]

LVDC instruction words were split into a 4-bit opcode field (least-significant bits) and a 9-bit operand address field (most-significant bits). This left it with sixteen possible opcode values when there were eighteen different instructions: consequently, three of the instructions used the same opcode value, and used two bits of the address value to determine which instruction was executed.

Memory was broken into 256-word "sectors". 8 bits of the address specified a word within a sector, and the 9th bit selected between the software-selectable "current sector" or a global sector called "residual memory".

The eighteen possible LVDC instructions were:[4]: 20–101

Instruction | Opcode | Function

|
|

`HOP` | 0000 | Transfer execution to a different part of the program. Unlike a modern 'jump' instruction the operand address did not actually specify the address to jump to, but pointed to a 26-bit 'HOP constant' which specified the address.
`MPY` | 0001 | Multiply the contents of the memory location specified in the operand address by the contents of the accumulator register. This instruction took four instruction cycles to complete, but didn't stall program execution, so other instructions could execute before it finished. The result was left in a known register.
`SUB` | 0010 | Subtract the contents of the memory location specified in the operand address from the accumulator register.
`DIV` | 0011 | Divide the contents of the memory location specified in the operand address into the accumulator. This instruction took eight instruction cycles to complete, but didn't stall program execution.
`TNZ` | 0100 | Transfers instruction execution to the operand address specified if the accumulator contents are not zero.
`MPH` | 0101 | Multiply the contents of the memory location specified in the operand address by the contents of the accumulator register. Unlike MPY, this instruction does halt execution until the multiplication is complete.
`AND` | 0110 | Logically AND the contents of the accumulator with the contents of the memory location specified in the operand address.
`ADD` | 0111 | Add the contents of the memory location specified in the operand address to the accumulator register.
`TRA` | 1000 | Transfer execution to the memory location specified in the operand address. The address is within the current instruction sector; the 9th (residual) bit of the operand selects the syllable.
`XOR` | 1001 | Logically XOR the contents of the accumulator with the contents of the memory location specified in the operand address.
`PIO` | 1010 | Process input or output: communicate with external hardware via the Data Adapter. "The low order address bits, A1 and A2, determine whether the operation is an input or output instruction. The high order address bits, A8 and A9, determine whether the data contents are transferred from the main memory, residual memory or accumulator."
`STO` | 1011 | Store the contents of the accumulator register in the memory location specified in the operand address.
`TMI` | 1100 | Transfer execution to the operand address specified if the accumulator contents are negative.
`RSU` | 1101 | Contents of the accumulator are subtracted from the contents of the memory location specified in the operand address, and the result left in the accumulator.
`SHR` | 01 1110 | Contents of accumulator are shifted by up to two bits, based on a value in the operand address. This instruction can also clear the accumulator if the operand address bits are zero.
`CDS` | x0 1110 | Change data sector.
`EXM` | 11 1110 | Transfer execution to one of eight addresses dependent on the operand address, which also specifies modifications to the operand address of the next instruction before it is executed.
`CLA` | 1111 | (Clear accumulator and) load memory.

### Programs and algorithms

[edit]

In flight the LVDC ran a major computation loop every 2 seconds for vehicle guidance, and a minor loop 25 times a second for attitude control. The minor loop is triggered by a dedicated interrupt every 40 ms and takes 18 ms to run.[5]

Unlike the Apollo Guidance Computer software, the software which ran on the LVDC seems to have vanished. While the hardware would be fairly simple to emulate, the only remaining copies of the software are probably in the core rope memory of the Instrument Unit LVDCs of the remaining Saturn V rockets on display at NASA sites.[citation needed]

## Interrupts

[edit]

The LVDC could also respond to a number of interrupts triggered by external events.

For a Saturn IB these interrupts were:

LVDC Data Word Bit | Function

|

`1` | Internal to LVDC
`2` | Spare
`3` | Simultaneous Memory Error
`4` | Command Decoder Interrupt
`5` | Guidance Reference Release
`6` | Manual Initiation of S-IVB Engine Cutoff
`7` | S-IB Outboard Engines Cutoff
`8` | S-IVB Engine Out
`9` | RCA-110A Interrupt
`10` | S-IB Low Fuel Level Sensors Dry
`11` | RCA-110A Interrupt

For a Saturn V these interrupts were:

LVDC Data Word Bit | Function

|

1 | Minor Loop Interrupt
2 | Switch Selector Interrupt
3 | Computer Interface Unit Interrupt
4 | Temporary Loss Of Control
5 | Command Receiver Interrupt
6 | Guidance Reference Release
7 | S-II Propellant Depletion/Engine Cutoff
8 | S-IC Propellant Depletion/Engine Cutoff
9 | S-IVB Engine Out
10 | Program Recycle (RCA-110A Interrupt)
11 | S-IC Inboard Engine Out
12 | Command LVDA/RCA-110A Interrupt

## Construction

[edit]

The LVDC was approximately 30 inches (760 mm) wide, 12.5 inches (320 mm) high, and 10.5 inches (270 mm) deep and weighed 72.5 pounds (32.9 kg).[6] The chassis was made of magnesium-lithium alloy LA 141, chosen for its high stiffness, low weight, and good vibration damping characteristics.[7]: 511 The chassis was divided into a 3 x 5 matrix of cells separated by walls through which coolant was circulated to remove the 138 watts[8] of power dissipated by the computer. Slots in the cell walls held "pages" of electronics. The decision to cool the LVDC by circulating coolant through the walls of the computer was unique at the time and allowed the LVDC and LVDA (part-cooled using this technique) to be placed in one cold plate location due to the three dimensional packaging. The cold plates used to cool most equipment in the Instrument Unit were inefficient from a space view although versatile for the variety of equipment used. The alloy LA 141 had been used by IBM on the Gemini keyboard, read out units, and computer in small quantities and the larger frame of the LVDC was produced from the largest billets of LA 141 cast at the time and subsequently CNC machined into the frame.

A page consisted of two 2.5–3-inch (64–76 mm) boards back to back and a magnesium-lithium frame to conduct heat to the chassis on low power pages and magnesium-aluminun-zinc on higher power pages. The 12-layer boards contained signal, power, and ground layers and connections between layers were made by plated-through holes. The plated-through holes were deliberately placed below the unit logic devices (ULD) to help conduct heat from the devices to the metal frames and thus the coolant walls.

Up to 35 alumina squares of 0.3 by 0.3 by 0.07 inches (7.6 mm × 7.6 mm × 1.8 mm)[9] could be reflow soldered to a board. These alumina squares had conductors silk screened to the top side and resistors silk-screened to the bottom side. Semiconductor chips of 0.025 by 0.025 inches (0.64 mm × 0.64 mm), each containing either one transistor or two diodes, were reflow soldered to the top side. The complete module was called a unit logic device.[10] The unit logic device (ULD) was a smaller version of IBM's Solid Logic Technology (SLT) module, but with clip connections.[3][11][12] Copper balls were used for contacts between the chips and the conductive patterns.[7]: 509

The hierarchy of the electronic structure is shown in the following table.

LVDC electronic packaging[7]: 501–516 Level | Component | Material | IBM term

|
|
|

1 | Transistor, diode | 0.025-by-0.025-inch (0.64 mm × 0.64 mm) silicon | \-
2 | Up to 14 transistors, diodes and resistors | 0.3-by-0.3-by-0.07-inch (7.6 mm × 7.6 mm × 1.8 mm) alumina | ULD (Unit Logic Device)
3 | Up to 35 ULDs | 2.5-by-3-inch (64 mm × 76 mm) printed circuit board | MIB (Multilayer Interconnection Board)
4 | Two MIBs | Magnesium-lithium frame | Page

## Gallery

[edit]

* MSFC officials, including Dr. Wernher von Braun (on left) looking at an LVDC

## See also

[edit]

* Apollo Guidance Computer
* Apollo PGNCS primary spacecraft guidance system
* Gemini Spacecraft On-Board Computer (OBC)

## Notes

[edit]

1. ^ "World's first 1,000-processor chip designed by UC Davis".
2. ^ "Chapter Seven - The Evolution of Automated Launch Processing". Computers in Spaceflight: The NASA Experience. NASA. Retrieved November 19, 2022.
3. ^ a b Dr. Wernher von Braun. "Tiny Computers Steer Mightiest Rockets". Popular Science. Oct 1965. p. 94-95; 206-208.
4. ^ Saturn Launch Vehicles TR X-881
5. ^ Haeussermann 1970, pp. 30–31.
6. ^ Apollo Study Report, Volume 2, pages 3-36 to 3-37. The log book for the LVDC at National Air and Space Museum says the dimensions were 31x13.1x13 inches and the weight was 90 pounds.
7. ^ a b c M.M. Dickinson, J.B. Jackson, G.C. Randa. IBM Space Guidance Center, Owego, NY. "Saturn V Launch Vehicle Digital Computer and Data Adapter." Proceedings of the Fall Joint Computer Conference, 1964
8. ^ Apollo Study Report, Volume 2, page 3-4.
9. ^ Apollo Study Report, Volume 2, page 2-37
10. ^ Haeussermann 1970, pp. 23.
11. ^ Ken Shirriff. "A circuit board from the Saturn V rocket, reverse-engineered and explained". 2020.
12. ^ Pugh, Emerson; Johnson; Palmer, John (1991). IBM's 360 and Early 370 Systems. MIT Press. p. 108. ISBN 978-0262161237.

## References

[edit]

* IBM, Saturn V Launch Vehicle Digital Computer, Volume One: General Description and Theory, 30 November 1964
* IBM, Saturn V Guidance Computer, Semiannual Progress Report, 1 Apr. - 30 Sep. 1963, 31 October 1963; archive
* Bellcomm, Inc, Memory Requirements for the Launch Vehicle Digital Computer (LVDC), April 25, 1967
* Boeing, Saturn V Launch Vehicle Guidance Equations, SA-504, 15 July 1967
* Haeussermann, Walter (July 1970). Description and Performance Of The Saturn Launch Vehicle's Navigation, Guidance And Control System (PDF). NASA TN D-5869.
* NASA Marshall Spaceflight Center, Saturn V Flight Manual SA-503, 1 November 1968
* NASA Marshall Spaceflight Center, Skylab Saturn IB Flight Manual, 30 September 1972
* M.M. Dickinson, J.B. Jackson, G.C. Randa. IBM Space Guidance Center, Owego, NY. "Saturn V Launch Vehicle Digital Computer and Data Adapter." Proceedings of the Fall Joint Computer Conference, 1964, pages 501–516.
* S. Bonis, R. Jackson, and B. Pagnani. IBM Space Guidance Center, Owego, NY. "Mechanical and Electronic Packaging for a Launch-Vehicle Guidance Computer." International Electronic Circuit Packaging Symposium 21–24 August 1964. Pages 226–241.
* IBM, Apollo Study Report, Volume 2.[dead link] IBM Space Guidance Center, Owego, NY, 1 October 1963. 133 pages. Also available on Virtual AGC (search for 63-928-130).
* NASA MSFC, Astrionics System Handbook Saturn Launch Vehicles NASA Marshall Space Flight Center, 1 Nov 1968. MSFC No. IV-4-401-1. IBM No. 68-966-0002. 419 pages. Chapter 15 is about the LVDC and Launch Vehicle Data Adapter.

## External links

[edit]

* IBM Archives: Saturn Guidance Computer
* High-resolution photos of LDVC components at the SpaceAholic collection of Apollo Lunar Module and Saturn V spaceflight artifacts

* v
* t
* e

Apollo program hardware

Launch vehicles|

* Little Joe II
* Saturn I
* Saturn IB
* Saturn V

Launch vehicle
components|

* F-1 engine
* J-2 engine
* Instrument unit
* Launch Vehicle Digital Computer

Spacecraft|

* Apollo
* Apollo command module
* Columbia
* Apollo service module
* Apollo Lunar Module
* Eagle

Spacecraft
components|

* Apollo Abort Guidance System
* Apollo Docking Mechanism
* Apollo Guidance Computer
* Lunar Sounder Experiment
* Primary guidance, navigation, and control system
* Apollo Telescope Mount
* Apollo TV camera
* Descent propulsion system
* Ascent propulsion system
* Scimitar antenna

Space suits|

* Apollo/Skylab A7L
* Beta cloth
* Thermal Micrometeoroid Garment

Lunar surface
equipment|

* Portable Life Support System
* Lunar Roving Vehicle
* Lunar Laser Ranging experiment
* list of retroreflectors
* Solar Wind Composition Experiment
* Apollo Lunar Surface Experiments Package
* Active Seismic Experiment
* Apollo 12 Passive Seismic Experiment
* Apollo 14 Passive Seismic Experiment
* Charged Particle Lunar Environment Experiment
* Lunar Ejecta and Meteorites Experiment
* Solar Wind Spectrometer Experiment
* Modular Equipment Transporter
* Lunar Seismic Profiling Experiment
* Lunar Surface Gravimeter
* Lunar Surface Magnetometer
* Lunar Traverse Gravimeter
* Cold Cathode Gauge Experiment
* Heat Flow Experiment
* Suprathermal Ion Detector Experiment

Ground support|

* Mobile Launcher
* Launch Umbilical Tower
* Crawler-transporter
* Lunar Landing Research Vehicle
* Mobile quarantine facility

Ceremonial|

* Lunar plaque
* Lunar Flag Assembly
* Fallen Astronaut
* Apollo 11 goodwill messages

Related|

* Lunar escape systems
* Rendezvous Docking Simulator
* Moon Museum

Category:Apollo program hardware

* v
* t
* e

Guidance computers

On crewed spacecraft|

* Gemini Guidance Computer
* Apollo Guidance Computer
* Apollo Abort Guidance System
* IBM System/4 Pi

On launch vehicles|

* ATHENA computer
* ASC-15
* D-17
* Launch Vehicle Digital Computer

Category:Guidance computers

* v
* t
* e

Processor technologies

Models|

* Abstract machine
* Stored-program computer
* Finite-state machine
* with datapath
* Hierarchical
* Deterministic finite automaton
* Queue automaton
* Cellular automaton
* Quantum cellular automaton
* Turing machine
* Alternating Turing machine
* Universal
* Post–Turing
* Quantum
* Nondeterministic Turing machine
* Probabilistic Turing machine
* Hypercomputation
* Zeno machine
* Belt machine
* Stack machine
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load–store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* Orthogonal instruction set
* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* VISC architecture
* Quantum computing
* Comparison
* Addressing modes

|

Instruction
sets|

* Motorola 68000 series
* VAX
* PDP-11
* x86
* ARM
* Stanford MIPS
* MIPS
* MIPS-X
* Power
* POWER
* PowerPC
* Power ISA
* Clipper architecture
* SPARC
* SuperH
* DEC Alpha
* ETRAX CRIS
* M32R
* Unicore
* Itanium
* OpenRISC
* RISC-V
* MicroBlaze
* LMC
* System/3x0
* S/360
* S/370
* S/390
* z/Architecture
* Tilera ISA
* VISC architecture
* Epiphany architecture
* Others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Scoreboarding
* Tomasulo's algorithm
* Reservation station
* Re-order buffer
* Register renaming
* Wide-issue

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Simultaneous and heterogenous
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* Array processing (SIMT)
* Pipelined processing
* Associative processing
* SWAR
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Tile processor
* Coprocessor
* PAL
* ASIC
* FPGA
* FPOA
* CPLD
* Multi-chip module (MCM)
* System in a package (SiP)
* Package on a package (PoP)

| By application|

* Embedded system
* Microprocessor
* Microcontroller
* Mobile
* Ultra-low-voltage
* ASIP
* Soft microprocessor

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Cypress PSoC
* Network on a chip (NoC)

Hardware
accelerators|

* Coprocessor
* AI accelerator
* Graphics processing unit (GPU)
* Image processor
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor Processing Unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 4-bit
* 8-bit
* 12-bit
* 15-bit
* 16-bit
* 24-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* bit slicing
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* Scratchpad memory
* Data cache
* Instruction cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional
units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Branch predictor
* Branch target predictor
* Integrated memory controller (IMC)
* Memory management unit
* Instruction decoder

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Memory address register
* Program counter

Control unit|

* Hardwired control unit
* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum-addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model
* Pin grid array
* Chip carrier

*[v]: View this template
*[t]: Discuss this template
*[e]: Edit this template