Load–store unit

Part of a computer system

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In computer engineering, a load–store unit (LSU) is a specialized execution unit responsible for executing all load and store instructions, generating virtual addresses of load and store operations[1][2][3] and loading data from memory or storing it back to memory from registers.[4]

The load–store unit usually includes a queue which acts as a waiting area for memory instructions, and the unit itself operates independently of other processor units.[4]

Load–store units may also be used in vector processing, and in such cases the term "load–store vector" may be used.[5]

Some load–store units are also capable of executing simple fixed-point and/or integer operations.

## See also[edit]

* Address-generation unit
* Arithmetic–logic unit
* Floating-point unit
* Load–store architecture

## References[edit]

1. ^ "IBM POWER8 processor core microarchitecture (PDF Download Available)". ResearchGate.
2. ^ "Structure of Computer Systems" (PDF). Users.utcluj.ro. p. 320. Retrieved 2017-06-23.
3. ^ "ARM Information Center". infocenter.arm.com.
4. ^ a b Memory Systems: Cache, DRAM, Disk by Bruce Jacob, Spencer Ng, David Wang 2007 ISBN 0123797519 page 298
5. ^ Computer Architecture: A Quantitative Approach by John L. Hennessy, David A. Patterson 2011 ISBN 012383872X pages 293-295

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Processor technologies

Models|

* Abstract machine
* Stored-program computer
* Finite-state machine
* with datapath
* Hierarchical
* Deterministic finite automaton
* Queue automaton
* Cellular automaton
* Quantum cellular automaton
* Turing machine
* Alternating Turing machine
* Universal
* Post–Turing
* Quantum
* Nondeterministic Turing machine
* Probabilistic Turing machine
* Hypercomputation
* Zeno machine
* Belt machine
* Stack machine
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load–store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* Orthogonal instruction set
* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* VISC architecture
* Quantum computing
* Comparison
* Addressing modes

|

Instruction
sets|

* Motorola 68000 series
* VAX
* PDP-11
* x86
* ARM
* Stanford MIPS
* MIPS
* MIPS-X
* Power
* POWER
* PowerPC
* Power ISA
* Clipper architecture
* SPARC
* SuperH
* DEC Alpha
* ETRAX CRIS
* M32R
* Unicore
* Itanium
* OpenRISC
* RISC-V
* MicroBlaze
* LMC
* System/3x0
* S/360
* S/370
* S/390
* z/Architecture
* Tilera ISA
* VISC architecture
* Epiphany architecture
* Others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Scoreboarding
* Tomasulo's algorithm
* Reservation station
* Re-order buffer
* Register renaming
* Wide-issue

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Simultaneous and heterogenous
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* Array processing (SIMT)
* Pipelined processing
* Associative processing
* SWAR
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Tile processor
* Coprocessor
* PAL
* ASIC
* FPGA
* FPOA
* CPLD
* Multi-chip module (MCM)
* System in a package (SiP)
* Package on a package (PoP)

| By application|

* Embedded system
* Microprocessor
* Microcontroller
* Mobile
* Ultra-low-voltage
* ASIP
* Soft microprocessor

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Cypress PSoC
* Network on a chip (NoC)

Hardware
accelerators|

* Coprocessor
* AI accelerator
* Graphics processing unit (GPU)
* Image processor
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor Processing Unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 4-bit
* 8-bit
* 12-bit
* 15-bit
* 16-bit
* 24-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* bit slicing
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* Scratchpad memory
* Data cache
* Instruction cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional
units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Branch predictor
* Branch target predictor
* Integrated memory controller (IMC)
* Memory management unit
* Instruction decoder

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Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Memory address register
* Program counter

Control unit|

* Hardwired control unit
* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum-addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model
* Pin grid array
* Chip carrier

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