Open collector

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Transistor switch output for integrated circuits

Open collector, open drain, open emitter, and open source refer to integrated circuit (IC) output pin configurations that process the IC's internal function through a transistor with an exposed terminal that is internally unconnected (i.e. "open"). One of the IC's internal high or low voltage rails typically connects to another terminal of that transistor. When the transistor is off, the output is internally disconnected from any internal power rail, a state called "high-impedance" (Hi-Z). Open outputs configurations thus differ from push–pull outputs, which use a pair of transistors to output a specific voltage or current.

These open outputs configurations are often used for digital applications when the transistor acts as a switch, to allow for logic-level conversion, wired-logic connections, and line sharing. External pull-up/down resistors are typically required to set the output during the Hi-Z state to a specific voltage. Analog applications include analog weighting, summing, limiting, and digital-to-analog converters.

The NPN BJT (n-type bipolar junction transistor) and nMOS (n-type metal oxide semiconductor field effect transistor) have greater conductance than their PNP and pMOS relatives, so may be more commonly used for these outputs. Open outputs using PNP and pMOS transistors will use the opposite internal voltage rail used by NPN and nMOS transistors.

## Open collector

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NPN open collector output schematic. A signal from an IC's internal function is applied as the base input for a NPN BJT transistor, which controls the transistor's switching to the IC's ground. The external output is the transistor's collector.

An open collector output processes an IC's output through the base of an internal bipolar junction transistor (BJT), whose collector is exposed as the external output pin.

For NPN open collector outputs, the emitter of the NPN transistor is internally connected to ground,[1] so the NPN open collector internally forms either a short-circuit (technically low impedance or "low-Z") connection to the low voltage (which could be ground) when the transistor is switched on, or an open-circuit (technically high impedance or "hi-Z") when the transistor is off. The output is usually connected to an external pull-up resistor, which pulls the output voltage to the resistor's supply voltage when the transistor is off.

For PNP open collector outputs, the emitter of the PNP transistor is internally connected to the positive voltage rail, so the collector outputs a high voltage when the transistor is on or is hi-Z when off. This is sometimes called "open collector, drives high".

### Open emitter

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Open emitter output exposes the emitter as the output.[2]

For an NPN open emitter output, the collector is connected to the positive voltage rail, so the emitter outputs a high voltage when the transistor is on and is hi-Z when off.

For a PNP open emitter output, the collector is connected to the low voltage supply, so the emitter outputs a low voltage when the transistor is on and is hi-Z when off.

## Open drain

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nMOS open drain output is pulled Low when the nMOS is conducting. In the nonconducting hi-Z state, an external resistor pulls the output High so the output's voltage does not float.

Open drain output uses MOS transistor (MOSFET) instead of BJTs, and expose the MOSFET's drain as output.[1]: 488ff

An nMOS open drain output connects to ground when a high voltage is applied to the MOSFET's gate, or presents a high impedance when a low voltage is applied to the gate. The voltage in this high impedance state would be floating (undefined) because the MOSFET is not conducting, which is why nMOS open drain outputs require a pull-up resistor connected to a positive voltage rail for producing a high output voltage.

Microelectronic devices using nMOS open drain output may provide a 'weak' (high-resistance, often on the order of 100 kΩ) internal pull-up resistor to connect the terminal in question to the positive power supply of the device so their output voltage doesn't float. Such weak pullups reduce power consumption due to their lower  V 2 / R {\displaystyle V^{2}/R} ohmic heating and possibly avoid the need for an external pull-up. External pullups may be 'stronger' (lower resistance, perhaps 3 kΩ) to reduce signal rise times (like with I²C) or to minimize noise (like on system RESET inputs).

Modern microcontrollers may allow programming particular output pins to use open drain instead of push–pull output, the strength of the internal pull-up, and allow disabling internal pullups when not desired.[3]

For pMOS open drain, the output instead connects to the positive power rail when the transistor is on, and is hi-Z when off. This is sometimes called "open drain, drives high".

### Open source

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Open source output exposes the MOSFET's source as the output.

For a nMOS open source output, the drain is internally connected to the positive voltage rail, so the source outputs a high voltage when the transistor is on and is hi-Z when off.

For a pMOS open source output, the drain is internally connected to the low voltage rail, so the output instead connects to the low voltage rail when the transistor is on, or is hi-Z when off.

## Summary of configurations

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Summary of different open configurations  transistor  | exposed terminal  | internal voltage supply connection

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NPN  | open collector  | LOW voltage connected to emitter
open emitter  | HIGH voltage connected to collector
nMOS  | open drain  | LOW voltage connected to source
open source  | HIGH voltage connected to drain
PNP  | open collector  | HIGH voltage connected to emitter
open emitter  | LOW voltage connected to collector
pMOS  | open drain  | HIGH voltage connected to source
open source  | LOW voltage connected to drain

Configurations that internally connect to a high voltage are source drivers.[4] Configurations that internally connect to a low voltage are sink drivers.[5]

## Schematic symbol

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Schematic symbol for a buffer with open-collector output[6]

Open output is indicated on schematics with these IEEE symbols:[7]

⎐ – NPN open collector or similar output that can supply a relatively low-impedance low voltage when not turned off. Requires external pullup. Capable of positive-logic wired-AND connection.

⎒ – variant with internal pull-up resistor to provide a high voltage when off.
⎏ – NPN open emitter or similar output that can supply a relatively low-impedance high voltage when not turned off. Requires external pulldown. Capable of positive-logic wired-OR connection.

⎑ – variant with an internal pull-down resistor to provide a low voltage when off.

## Applications

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Note: this section primarily deals with npn open collectors, however nMOS open drain generally applies as well.

### Logic-level conversion

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Because the pull-up resistor is external and does not need to be connected to the chip supply voltage, a lower or higher voltage than the chip supply voltage can be used instead (provided it does not exceed the absolute maximum rating of the chip's output). Open outputs are therefore sometimes used to interface different families of devices that have different operating voltage levels. The open collector transistor can be rated to withstand a higher voltage than the chip supply voltage. This technique is commonly used by logic circuits operating at 5 V or lower to drive higher voltage devices such as electric motors, LEDs in series,[8] 12 V relays, 50 V vacuum fluorescent displays, or Nixie tubes requiring more than 100 V.

### Wired logic

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Four inputs are connected to open-collector buffers. If all inputs are low, each buffer will be in a high-impedance state and the pull-up resistor will pull the output high. But if any input is high, the output will be pulled low by the buffer for that input. This corresponds to wired AND in active-high logic, or to wired OR in active-low logic, and allows multiple inputs to share the same output wire.

Main article: Wired logic connection

Another advantage is that more than one open-collector output can be connected to a single line. If all open collector outputs attached to a line are off (i.e. in the high-impedance state), the pull-up resistor will be the only device setting the line's voltage and will pull the line voltage high. But if one or more open-collector outputs attached to the line are on (i.e. conducting to ground), since any one of them are strong enough to overcome the pull-up resistor's limited ability to hold the voltage high, the line voltage will instead be pulled low. This wired logic connection has several uses.

By tying the output of several open collectors together and connecting to a pull-up resistor, the common line becomes a wired AND in active high logic. The output will be high (true) only when all gates are in the high-impedance state, and will be low (false) otherwise, like Boolean AND. When treated as active-low logic, this behaves like Boolean OR, since the output is low (true) when any input is low. See Transistor–transistor logic § Open collector wired logic.

#### Line sharing

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Line sharing is used for interrupts and buses (such as I²C or 1-Wire). Open-collector output enables one active device to drive the shared line without interference from the other inactive devices. If push–pull output was mistakenly used instead, the active device attempting to set the line voltage low would be in competition with the other devices attempting to set the line voltage high, which would result in unpredictable output and heat.

SCSI-1 devices use open collector for electrical signaling.[9] SCSI-2 and SCSI-3 may use EIA-485.

### Analog

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Open collector outputs can also be useful for analog weighting, summing, limiting, digital-to-analog converters, etc., but such applications are not discussed here.

## Disadvantages

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One problem such open-collector and similar devices with a pull-up resistor is the resistor consumes power constantly while the output is low. Higher operating speeds require lower resistor values for faster pull-up, which consume even more power.

Also when driving a load, current through the pull-up resistor reduces the output high voltage by a voltage drop equal to the current times resistance, according to Ohm's law.

## Pseudo open drain (POD)

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Pseudo open drain usage in DDR interfaces

Pseudo open drain (POD) drivers have a strong pull-down strength but a weaker pull-up strength. The purpose is to reduce the overall power demand compared to using both a strong pull-up and a strong pull-down.[10] A pure open-drain driver, by comparison, has no pull-up strength except for leakage current: all the pull-up action is on the external termination resistor. This is why the term "pseudo" has to be used here: there is some pull-up on the driver side when output is at high state, the remaining pull-up strength is provided by parallel-terminating the receiver at the far end to the high voltage, often using a switchable, on-die terminator instead of a separate resistor.

JEDEC standardized the terms POD15,[11] POD125,[12] POD135,[13] and POD12[14] for 1.5 V, 1.25 V, 1.35 V, and 1.2 V interface supply voltages respectively.

### DDR memory

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DDR4 memory uses POD12 drivers but with the same driver strength (34 Ω/48 Ω) for pull-down (RonPd) and pull-up (RonPu). The term POD in DDR4 referring only for termination type that is only parallel pull-up without the pull-down termination at the far end.[clarification needed] The reference point (VREF) for the input is not half-supply as was in DDR3 and may be higher. A comparison[15] of both DDR3 and DDR4 termination schemes in terms of skew, eye aperture and power consumption was published in late 2011.[relevant?]

## See also

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Wikimedia Commons has media related to Open collectors.

* Common collector and other common terminal transistor amplifiers: Used more for analog voltages than digital.
* Push–pull output: Consists of transistors to source and sink current in both logic states, not just one.
* Three-state logic: Consists of transistors to source and sink current in both logic states, as well as a control to turn off both transistors to isolate the output. This differs from open collector/drain output, which only use a single transistor that can only disconnect the output or connect it to ground.

## References

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1. ^ a b Paul Horowitz; Winfield Hill (1989). The Art of Electronics (2nd ed.). Cambridge University Press.
2. ^ "open-emitter output | JEDEC". www.jedec.org. Retrieved 2023-06-27.
3. ^ Kotzian, Jiri (2015). "Influence of Pin Setting on System Function and Performance" (PDF). NXP. Archived (PDF) from the original on 2022-10-23. Retrieved 2022-12-27.
4. ^ "source driver, (current-) | JEDEC". JEDEC. Archived from the original on 2023-09-05. Retrieved 2023-09-06.
5. ^ "sink driver, (current-) | JEDEC". JEDEC. Archived from the original on 2023-09-05. Retrieved 2023-09-06.
6. ^ "SNx407 and SNx417 Hex Buffers and Drivers With Open-Collector" (PDF). Texas Instruments. 1983. Retrieved 2023-01-18.
7. ^ "Overview of IEEE Standard 91-1984 Explanation of Logic Symbols" (PDF). Texas Instruments. 1996. Retrieved February 12, 2020.
8. ^ Oskay, Windell (2012-02-29). "Basics: Open Collector Outputs". Evil Mad Scientist. Archived from the original on 2022-12-20. Retrieved 2023-01-15.
9. ^ "Overview of SCSI Standards & Cables". Archived from the original on 2008-12-10. 081214 scsita.org
10. ^ Addenddum No. 6 to JESD8 – High Speed Transceiver Logic (HSTL) – A 1.5 V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits (August 1995).
11. ^ POD15 – 1.5 V Pseudo Open Drain Interface (October 2009).
12. ^ Pseudo Open Drain Interface (September 2017).
13. ^ POD135 – 1.35 V Pseudo Open Drain Interface (March 2018).
14. ^ POD12 – 1.2 V Pseudo Open Drain Interface (August 2011).
15. ^ Pseudo-open drain and Center-tab termination type termination schemes.

## External links

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Logic families

MOS technology|

* PMOS logic
* NMOS logic
* Depletion-load NMOS logic (including HMOS)
* Complementary MOS (CMOS)
* Pass transistor logic (PTL)
* Bipolar–CMOS (BiCMOS)

Other technologies|

* Diode logic
* Diode–transistor logic (DTL)
* Open collector (OC)
* Direct-coupled transistor logic (DCTL)
* Emitter-coupled logic (ECL)
* Gunning transceiver logic (GTL)
* Integrated injection logic (I2L)
* Resistor–transistor logic (RTL)
* Transistor–transistor logic (TTL)
* Current mode logic / Source-coupled logic (CML/SCL)

Types|

* Static
* Dynamic
* Domino logic
* Four-phase logic

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