Power ISA

Computer instruction set architecture

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|

Power ISADesigner|

* Power.org
* OpenPOWER Foundation

|

Bits| 32-bit/64-bit (32 → 64)
Introduced| 2006; 19 years ago (2006)
Version| 3.1
Design| RISC
Type| Load–store
Encoding| Fixed/Variable
Branching| Condition code
Endianness| Big/Bi
Extensions| AltiVec, PowerPC AS, APU, DSP, CBEA
Open| Yes, and royalty free
Registers

* 32× 64/32-bit general-purpose registers
* 32× 64-bit floating-point registers
* 64× 128-bit vector registers
* 32-bit condition code register
* 32-bit link register
* 32-bit count register

\+ more
A very high level schematic diagram of a generic Power ISA processor

Power ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA) currently developed by the OpenPOWER Foundation, led by IBM. It was originally developed by IBM and the now-defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor.

Prior to version 3.0, the ISA is divided into several categories. Processors implement a set of these categories as required for their task. Different classes of processors are required to implement certain categories, for example a server-class processor includes the categories: Base, Server, Floating-Point, 64-Bit, etc. All processors implement the Base category.

Power ISA is a RISC load/store architecture. It has multiple sets of registers:

* 32 × 32-bit or 64-bit general-purpose registers (GPRs) for integer operations.
* 64 × 128-bit vector scalar registers (VSRs) for vector operations and floating-point operations.
* 32 × 64-bit floating-point registers (FPRs) as part of the VSRs for floating-point operations.
* 32 × 128-bit vector registers (VRs) as part of the VSRs for vector operations.
* 8 × 4-bit condition register fields (CRs) for comparison and control flow.
* 11 special registers of various sizes: Counter Register (CTR), link register (LR), time base (TBU, TBL), alternate time base (ATBU, ATBL), accumulator (ACC), status registers (XER, FPSCR, VSCR, SPEFSCR).

Instructions up to version 3.0 have a length of 32 bits, with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications, and version 3.1 which introduced prefixing to create 64-bit instructions. Most instructions are triadic, i.e. have two source operands and one destination. Single- and double-precision IEEE 754 compliant floating-point operations are supported, including additional fused multiply–add (FMA) and decimal floating-point instructions. There are provisions for single instruction, multiple data (SIMD) operations on integer and floating-point data on up to 16 elements in one instruction.

Power ISA has support for Harvard cache, i.e. split data and instruction caches, and support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. There is also support for both big and little-endian addressing with separate categories for moded and per-page endianness, and support for both 32-bit and 64-bit addressing.

Different modes of operation include user, supervisor and hypervisor.

## Categories

[edit]

* Base – Most of Book I and Book II
* Server – Book III-S
* Embedded – Book III-E
* Misc – floating point, vector, signal processing, cache locking, decimal floating point, etc.

## Books

[edit]

The Power ISA specification is divided into five parts, called "books":

* Book I – User Instruction Set Architecture covers the base instruction set available to the application programmer. Memory reference, flow control, Integer, floating point, numeric acceleration, application-level programming. It includes chapters regarding auxiliary processing units like digital signal processors (DSPs) and the AltiVec extension.
* Book II – Virtual Environment Architecture defines the storage model available to the application programmer, including timing, synchronization, cache management, storage features, byte ordering.
* Book III – Operating Environment Architecture includes exceptions, interrupts, memory management, debug facilities and special control functions. It is divided into two parts.
* Book III-S – Defines the supervisor instructions used for general-purpose/server implementations. It is mainly the contents of the Book III of the former PowerPC ISA.
* Book III-E – Defines the supervisor instructions used for embedded applications. It is derived from the former PowerPC Book E.
* Book VLE – Variable Length Encoded Instruction Architecture defines alternative instructions and definitions from Books I–III, intended for higher instruction density and very-low-end applications. They use 16-bit instructions and big-endian byte ordering.

### Compliancy

[edit]

New in version 3 of the Power ISA is that you don't have to implement the entire specification to be compliant. The sprawl of instructions and technologies has made the complete specification unwieldy, so the OpenPOWER Foundation have decided to enable tiered compliancy.

These levels include optional and mandatory requirements, however one common misunderstanding is that there is nothing stopping an implementation from being compliant at a lower level but having additional selected functions from higher levels and custom extensions. It is however recommended that an option be provided to disable any added functions beyond the design's declared subset level.

A design must be compliant at its declared subset level to make use of the Foundation's protection regarding use of intellectual property, be it patents or trademarks. This is explained in the OpenPOWER EULA.[1]

A compliant design must:[2]

* Support the Base architecture
* And support at least one of the subsets
* SFS – Scalar Fixed-point Subset. 129 instructions. Basic fixed point and load/store instructions, which is really the Base architecture.
* SFFS – Scalar Fixed-point + Floating-point Subset. 214 instructions. Adding floating-point operations to the Base.
* LCS – Linux Compliancy Subset. 962 instructions. Intended for server grade Linux, adding features like 64-bit, optional SIMD/VSX, Radix MMU, little-endian mode and hypervisor support.
* ACS – AIX Compliancy Subset. 1099 instructions. Intended to run AIX, adding features like decimal and quad-precision floating point, big-endian mode and symmetric multiprocessing.
* May include any of the features of the LCS and ACS as Optional or pick from the Always Optional features like matrix math and power management.
* Optional features, if chosen, must be implemented in their entirety (partial implementation of an Optional feature is not permitted)
* May include Custom extensions, specific to the implementation, implemented in the Architecture Sandbox.

If the extension is general-purpose enough, the OpenPOWER Foundation asks that implementors submit it as a Request for Comments (RFC) to the OpenPOWER ISA Workgroup. Note that it is not strictly necessary to join the OpenPOWER Foundation to submit RFCs.[3]

* Much may be implemented in either hardware or firmware.

#### EABI and Linux Compliancy discrepancy

[edit]

This section possibly contains original research. Please improve it by verifying the claims made and adding inline citations. Statements consisting only of original research should be removed. (January 2024) (Learn how and when to remove this message)

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The EABI specifications predate the announcement and creation of the Compliancy subsets.

Regarding the Linux Compliancy subset having VSX (SIMD) optional: in 2003–4, 64-bit EABI v1.9 made SIMD optional,[4] but in July 2015, to improve performance for IBM POWER9 systems, SIMD was made mandatory in EABI v2.0.[5] This discrepancy between SIMD being optional in the Linux Compliancy level but mandatory in EABI v2.0 cannot be rectified without considerable effort: backwards incompatibility for Linux distributions is not a viable option. At present this leaves new OpenPOWER implementors wishing to run standard Linux distributions having to implement a massive 962 instructions. By contrast, RISC-V RV64GC, the minimum to run Linux, requires only 165.[6]

## Specifications

[edit]

### Power ISA v.2.03

[edit]

The specification for Power ISA v.2.03[7] is based on the former PowerPC ISA v.2.02[8] in POWER5\+ and the Book E[9] extension of the PowerPC specification. The Book I included five new chapters regarding auxiliary processing units like DSPs and the AltiVec extension.

Compliant cores

* Freescale PowerPC e200, e500
* IBM PowerPC 405, 440, 460, 970, POWER5 and POWER6

### Power ISA v.2.04

[edit]

The specification for Power ISA v.2.04[10] was finalized in June 2007. It is based on Power ISA v.2.03 and includes changes primarily to the Book III-S part regarding virtualization, hypervisor functions, logical partitioning and virtual page handling.

Compliant cores

* All cores that comply with prior versions of the Power ISA
* The PA6T core from P.A. Semi
* Titan from AMCC

### Power ISA v.2.05

[edit]

The specification for Power ISA v.2.05[11] was released in December 2007. It is based on Power ISA v.2.04 and includes changes primarily to Book I and Book III-S, including significant enhancements such as decimal arithmetic (Category: Decimal Floating-Point in Book I) and server hypervisor improvements.

Compliant cores

* All cores that comply with prior versions of the Power ISA
* POWER6
* PowerPC 476

### Power ISA v.2.06

[edit]

The specification for Power ISA v.2.06[12] was released in February 2009, and revised in July 2010.[13] It is based on Power ISA v.2.05 and includes extensions for the POWER7 processor and e500-mc core. One significant new feature is vector-scalar floating-point instructions (VSX).[14] Book III-E also includes significant enhancement for the embedded specification regarding hypervisor and virtualisation on single and multi core implementations.

The spec was revised in November 2010 to the Power ISA v.2.06 revision B spec, enhancing virtualization features.[13][15]

Compliant cores

* All cores that comply with prior versions of the Power ISA
* POWER7
* A2I
* e500-mc
* e5500
* e6500

### Power ISA v.2.07

[edit]

The specification for Power ISA v.2.07[16] was released in May 2013. It is based on Power ISA v.2.06 and includes major enhancements to logical partition functions, transactional memory, expanded performance monitoring, new storage control features, additions to the VMX and VSX vector facilities (VSX-2), along with AES[16]: 257 [17] and Galois Counter Mode (GCM), SHA-224, SHA-256,[16]: 258 SHA-384 and SHA-512[16]: 258 (SHA-2) cryptographic extensions and cyclic redundancy check (CRC) algorithms.[18]

The spec was revised in April 2015 to the Power ISA v.2.07 B spec.[19][20]

Compliant cores

* All cores that comply with prior versions of the Power ISA
* POWER8
* A2O

### Power ISA v.3.0

[edit]

The specification for Power ISA v.3.0[21][22] was released in November 2015. It is the first to come out after the founding of the OpenPOWER Foundation and includes enhancements for a broad spectrum of workloads and removes the server and embedded categories while retaining backwards compatibility and adds support for VSX-3 instructions. New functions include 128-bit quad-precision floating-point operations, a random number generator, hardware-assisted garbage collection and hardware-enforced trusted computing.

The spec was revised in March 2017 to the Power ISA v.3.0 B spec,[19][23] and revised again to v3.0C in May 2020.[19][24][25] One major change from v3.0 to v3.0B is the removal of support for hardware assisted garbage collection. The key difference between v3.0B and v3.0C is that the Compliancy Levels listed in v3.1 were also added to v3.0C.

Compliant cores

* All cores that comply with prior versions of the Power ISA
* POWER9[26]
* OpenPOWER Microwatt
* Libre-SOC is aiming for Embedded FP compliancy with Power ISA 3.0 only

### Power ISA v.3.1

[edit]

The specification for Power ISA v.3.1[19][27] was released in May 2020. Mainly giving support for new functions introduced in Power10, but also includes the notion of optionality to the PowerISA specification. Instructions can now be eight bytes long, "prefixed instructions", compared to the usual four byte "word instructions". A lot of new functions to SIMD and VSX instructions are also added. VSX and the SVP64 extension provide hardware support for 16-bit half precision floats.[28][29]

One key benefit of the new 64-bit prefixed instructions is the extension of immediates in branches to 34-bit.

The spec was revised in September 2021 to the Power ISA v.3.1B spec.[19][30]

The spec was revised in May 2024 to the Power ISA v.3.1C spec.[19][31]

Compliant cores

* All cores that comply with prior versions of the Power ISA
* Power10[32]

## See also

[edit]

* Open-source computing hardware

## References

[edit]

1. ^ Final draft of Power ISA EULA
2. ^ The Open Power ISA: Architecture Compliancy and Future Foundations
3. ^ Section 2.2 of OPF Power ISA EULA
4. ^ Ian Lance Taylor. "64-bit PowerPC ELF Application Binary Interface Supplement 1.9".
5. ^ "Power Architecture 64-Bit ELF V2 ABI Specification, OpenPOWER ABI for Linux Supplement" (PDF). 16 July 2015. Archived from the original (PDF) on 2019-10-24.
6. ^ Krste Asanović (October 14, 2017). "Computer Architecture Research with RISC-V" (PDF). p. 18.
7. ^ "Power ISA v.2.03" (PDF). Power.org. 2006-09-29. Archived from the original (PDF) on 2011-07-27.
8. ^ "PowerPC Architecture Book, Version 2.02". IBM. 2005-02-24. Archived from the original on 2007-10-18. Retrieved 2007-03-16.
9. ^ "PowerPC Book E v.1.0" (PDF). IBM. 2002-05-07. Archived (PDF) from the original on 2018-03-10. Retrieved 2007-03-16.
10. ^ "Power ISA Version 2.04" (PDF). Power.org. 2007-06-12. Archived from the original (PDF) on 2007-09-27. Retrieved 2007-06-14.
11. ^ "Power ISA Version 2.05". Power.org. 2007-10-23. Archived from the original on 2012-11-24. Retrieved 2007-12-18.
12. ^ "Power.org Debuts Specification Advances and New Services At Power Architecture Developer Conference" (Press release). Power.org. 2007-09-24. Archived from the original on 2007-10-12. Retrieved 2007-09-24.
13. ^ a b "Power ISA Version 2.06 Revision B". Power.org. 2010-07-23. Archived from the original on 2012-11-24. Retrieved 2011-02-12.
14. ^ "Workload acceleration with the IBM POWER vector-scalar architecture". IBM. 2016-03-01. Retrieved 2017-05-02.
15. ^ "Power ISA 2.06 Rev. B enables full hardware virtualization for embedded space". EETimes. 2010-11-03. Retrieved 2011-06-08.
16. ^ a b c d "Power ISA Version 2.07" (PDF). Power.org. 2013-05-15. Retrieved 2023-11-02.
17. ^ Barbosa, Leonidas (2014-09-21). "POWER8 in-core cryptography". IBM.
18. ^ Performance Optimization and Tuning Techniques for IBM Power Systems Processors Including IBM POWER8. IBM. August 2015. p. 48\. ISBN 9780738440927.
19. ^ a b c d e f "Instruction Set Architecture". OpenPOWER Foundation.
20. ^ "Power ISA Version 2.07 B". Power.org. 2015-04-09. Retrieved 2023-02-23.
21. ^ Announcing a New Era of Openness with Power 3.0
22. ^ "Power ISA Version 3.0". openpowerfoundation.org. 2016-11-30. Archived from the original on August 3, 2017. Retrieved 2017-01-06.
23. ^ "Power ISA Version 3.0 B". IBM. 2017-03-29. Retrieved 2023-02-23.
24. ^ "Power ISA Version 3.0 C". OpenPOWER Foundation. 2020-05-01. Retrieved 2023-02-23.
25. ^ list of Power ISA specifications
26. ^ [PATCH, COMMITTED] Add full Power ISA 3.0 / POWER9 binutils support
27. ^ "Power ISA Version 3.1". OpenPOWER Foundation. 2020-05-01. Retrieved 2023-02-23.
28. ^ "OPF_PowerISA_v3.1B.pdf". OpenPOWER Files. OpenPOWER Foundation. Retrieved 2023-07-02.
29. ^ "ls005.xlen.mdwn". libre-soc.org Git. Retrieved 2023-07-02.
30. ^ "Power ISA Version 3.1B". OpenPOWER Foundation. 2021-09-14. Retrieved 2023-02-23.
31. ^ "Power ISA Version 3.1C". OpenPOWER Foundation. 2024-05-26. Retrieved 2024-07-04.
32. ^ Seo, Carlos Eduardo (2020-05-12). "We released the Instruction Set Architecture for POWER10. Power ISA v3.1 is available at the IBM Portal for OpenPOWER". twitter.com. Retrieved 2020-05-23.

* v
* t
* e

Reduced instruction set computer (RISC) architectures

Origins|

* IBM 801
* Berkeley RISC
* Stanford MIPS

Development
active|

* Analog Devices Blackfin
* ARC
* ARM
* AVR
* eSi-RISC
* LatticeMico8, LatticeMico32
* MIPS
* OpenRISC
* Power ISA
* Renesas M32R, SuperH, V850
* RISC-V
* SPARC
* Sunway
* Unicore
* Xilinx MicroBlaze, PicoBlaze

Development
discontinued|

* Alpha
* AMD Am29000
* Apollo PRISM
* Atmel AVR32
* Clipper
* CR16
* CRISP
* DEC PRISM
* Intel i860, i960
* META
* MIPS-X
* Motorola 88000, M·CORE
* PA-RISC
* POWER, PowerPC (active use in space exploration as RAD750), ROMP

* v
* t
* e

Processor technologies

Models|

* Abstract machine
* Stored-program computer
* Finite-state machine
* with datapath
* Hierarchical
* Deterministic finite automaton
* Queue automaton
* Cellular automaton
* Quantum cellular automaton
* Turing machine
* Alternating Turing machine
* Universal
* Post–Turing
* Quantum
* Nondeterministic Turing machine
* Probabilistic Turing machine
* Hypercomputation
* Zeno machine
* Belt machine
* Stack machine
* Register machines
* Counter
* Pointer
* Random-access
* Random-access stored program

Architecture|

* Microarchitecture
* Von Neumann
* Harvard
* modified
* Dataflow
* Transport-triggered
* Cellular
* Endianness
* Memory access
* NUMA
* HUMA
* Load–store
* Register/memory
* Cache hierarchy
* Memory hierarchy
* Virtual memory
* Secondary storage
* Heterogeneous
* Fabric
* Multiprocessing
* Cognitive
* Neuromorphic

Instruction set
architectures|

| Types|

* Orthogonal instruction set
* CISC
* RISC
* Application-specific
* EDGE
* TRIPS
* VLIW
* EPIC
* MISC
* OISC
* NISC
* ZISC
* VISC architecture
* Quantum computing
* Comparison
* Addressing modes

|

Instruction
sets|

* Motorola 68000 series
* VAX
* PDP-11
* x86
* ARM
* Stanford MIPS
* MIPS
* MIPS-X
* Power
* POWER
* PowerPC
* Power ISA
* Clipper architecture
* SPARC
* SuperH
* DEC Alpha
* ETRAX CRIS
* M32R
* Unicore
* Itanium
* OpenRISC
* RISC-V
* MicroBlaze
* LMC
* System/3x0
* S/360
* S/370
* S/390
* z/Architecture
* Tilera ISA
* VISC architecture
* Epiphany architecture
* Others

Execution|

| Instruction pipelining|

* Pipeline stall
* Operand forwarding
* Classic RISC pipeline

|

Hazards|

* Data dependency
* Structural
* Control
* False sharing

Out-of-order|

* Scoreboarding
* Tomasulo's algorithm
* Reservation station
* Re-order buffer
* Register renaming
* Wide-issue

Speculative|

* Branch prediction
* Memory dependence prediction

Parallelism|

| Level|

* Bit
* Bit-serial
* Word
* Instruction
* Pipelining
* Scalar
* Superscalar
* Task
* Thread
* Process
* Data
* Vector
* Memory
* Distributed

|

Multithreading|

* Temporal
* Simultaneous
* Hyperthreading
* Simultaneous and heterogenous
* Speculative
* Preemptive
* Cooperative

Flynn's taxonomy|

* SISD
* SIMD
* Array processing (SIMT)
* Pipelined processing
* Associative processing
* SWAR
* MISD
* MIMD
* SPMD

Processor
performance|

* Transistor count
* Instructions per cycle (IPC)
* Cycles per instruction (CPI)
* Instructions per second (IPS)
* Floating-point operations per second (FLOPS)
* Transactions per second (TPS)
* Synaptic updates per second (SUPS)
* Performance per watt (PPW)
* Cache performance metrics
* Computer performance by orders of magnitude

Types|

* Central processing unit (CPU)
* Graphics processing unit (GPU)
* GPGPU
* Vector
* Barrel
* Stream
* Tile processor
* Coprocessor
* PAL
* ASIC
* FPGA
* FPOA
* CPLD
* Multi-chip module (MCM)
* System in a package (SiP)
* Package on a package (PoP)

| By application|

* Embedded system
* Microprocessor
* Microcontroller
* Mobile
* Ultra-low-voltage
* ASIP
* Soft microprocessor

|

Systems
on chip|

* System on a chip (SoC)
* Multiprocessor (MPSoC)
* Cypress PSoC
* Network on a chip (NoC)

Hardware
accelerators|

* Coprocessor
* AI accelerator
* Graphics processing unit (GPU)
* Image processor
* Vision processing unit (VPU)
* Physics processing unit (PPU)
* Digital signal processor (DSP)
* Tensor Processing Unit (TPU)
* Secure cryptoprocessor
* Network processor
* Baseband processor

Word size|

* 1-bit
* 4-bit
* 8-bit
* 12-bit
* 15-bit
* 16-bit
* 24-bit
* 32-bit
* 48-bit
* 64-bit
* 128-bit
* 256-bit
* 512-bit
* bit slicing
* others
* variable

Core count|

* Single-core
* Multi-core
* Manycore
* Heterogeneous architecture

Components|

* Core
* Cache
* CPU cache
* Scratchpad memory
* Data cache
* Instruction cache
* replacement policies
* coherence
* Bus
* Clock rate
* Clock signal
* FIFO

| Functional
units|

* Arithmetic logic unit (ALU)
* Address generation unit (AGU)
* Floating-point unit (FPU)
* Memory management unit (MMU)
* Load–store unit
* Translation lookaside buffer (TLB)
* Branch predictor
* Branch target predictor
* Integrated memory controller (IMC)
* Memory management unit
* Instruction decoder

|

Logic|

* Combinational
* Sequential
* Glue
* Logic gate
* Quantum
* Array

Registers|

* Processor register
* Status register
* Stack register
* Register file
* Memory buffer
* Memory address register
* Program counter

Control unit|

* Hardwired control unit
* Instruction unit
* Data buffer
* Write buffer
* Microcode ROM
* Counter

Datapath|

* Multiplexer
* Demultiplexer
* Adder
* Multiplier
* CPU
* Binary decoder
* Address decoder
* Sum-addressed decoder
* Barrel shifter

Circuitry|

* Integrated circuit
* 3D
* Mixed-signal
* Power management
* Boolean
* Digital
* Analog
* Quantum
* Switch

Power
management|

* PMU
* APM
* ACPI
* Dynamic frequency scaling
* Dynamic voltage scaling
* Clock gating
* Performance per watt (PPW)

Related|

* History of general-purpose CPUs
* Microprocessor chronology
* Processor design
* Digital electronics
* Hardware security module
* Semiconductor device fabrication
* Tick–tock model
* Pin grid array
* Chip carrier

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