Digital Electronics

Digital Electronics in Electrical/Electronics Engineering

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Welcome to the course EE 111.

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* Electronic Engineering
* EE Digital Electronics
* Lecture, Number systems and logic states
* Lecture, Digital Logic Gates
* Lecture, Combinatorial Functions
* Lecture, Karnaugh Map Reductions
* Lecture, Arithmetic
* Lecture, Flip-flops
* Mid-term Exam
* Lecture, Sequential Logic
* Lecture, Memory Elements
* Lecture, Registers and Counters
* Lecture, Advanced Sequential Circuits
* Lecture, Logic Simulation
* Lecture, High Level Language Logic Modelling and Synthesis
* Final Exam

## Syllabus

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## Lab Materials

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## Lecture plan

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* EE 111 Digital Electronics
* Lecture 1, Introduction to Binary, Octal and Hexadecimal Mathematics
* Lecture 2, Digital Logic
* Analysis of the inside of the basic logic types TTL MOS CMOS
* Lecture 3, Combinatorial Functions
* Basic logic gates
* Lecture 4, Karnaugh Map Reductions
* Lecture 5, Arithmetic
* Half Adder, Full Adder
* Lecture 6, Flip-flops
* JK SR D T flipflops/latches
* Mid-term Exam
* Lecture 7, Sequential Logic
*     * Lecture 8, Memory Elements
*     * Lecture 9, Registers and Counters
*     * Lecture 10, Advanced Sequential Circuits
*     * Lecture 11, Logic Simulation
*     * Lecture 12, High Level Language Logic Modelling and Synthesis
* Final Exam

## Datasheets Relevant

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74=Lower Voltage 40=Higher Voltage

### Gates

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Unless noted  | 2-6V  | 2-6V  | 2-6V  | 2-6V  | 3-18V  | 3-18V  | 3-18V  | 3-18V

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Unless noted  | DUAL  | TRIPLE  | QUAD  | OCTAL  | DUAL  | TRIPLE  | QUAD  | OCTAL
NOT  |  |  | 6 Inverters
(TI CD74HC04)  | (TI CD74HC240)  |  |  | 6 Inverters
(TI CD4009UB)  |
AND  | 4 Input
(TI SN74HC21)  | 3 Input
(TI SN74HC11)  | 2 Input
(TI SN74HC08)  |  | 4 Input
(TI CD4081B)  | 3 Input
(TI CD4073B)  | 2 Input
(TI CD4082B)  | 1 Gate 8 Input
(TI CD4068B)
NAND  | 4 Input
(TI CD74HC20)  | 3 Input
(TI CD74HC10)  | 2 Input
(TI CD74HC00)  | 1 Gate 8 Input
(TI CD74HC30)  | 2 Input
(TI CD40107B)  |  | 2 Input
(TI CD4011B)  | 1 Gate 8 Input
(TI CD4068B)
OR  |  | 3 Input
(TI CD74HC4075)  | 2 Input
(TI SN74HC32)  |  | 4 Input
(TI CD4072B)  | 3 Input
(TI CD4075B)  | 2 Input
(TI CD4071B)  | 1 Gate 8 Input
(TI CD4078B)
NOR  | 4 Input
(TI CD74HC4002)  | 3 Input
(TI CD74HC27)  | 2 Input
(TI CD74HC02)  |  | 4 Input
(TI CD4002B)  | 3 Input
(TI CD4025B)  | 2 Input
(TI CD4001B)  | 1 Gate 8 Input
(TI CD4078B)
XOR  |  |  | 2 Input
(TI SN74HC86)  |  |  |  | 2 Input
(TI CD4030B)  |
XNOR  |  |  | 2 Input
(TI SN74HC266)  |  |  |  | 2 Input
(TI CD4077B)  |
JK Flip Flop
/SR latch  | (TI CD74HC112)  |  |  |  | (TI CD4027)  |  |  |
D Flip Flop  | (TI CD74HC74)  |  | (TI CD74HC175)  | (TI CD74HC273)  | (TI CD4013)  |  | (TI CD40175)  |

### specialty

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3-18V  |  |  |  | 4-Bit
Magnitude Comparator
(TI CD4063B)

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2-6V  | Full Adder 4bit
(TI CD74HC283)  | 9-Bit Odd/Even
Parity Generator/Checker
(TI CD74HC280)  | 8-Bit Identity/
Magnitude Comparators
(TI SN74HC682)  | 4-Bit
Magnitude Comparator
(TI CD74HC85)
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3-18V  | Presettable
Up/Down Counter
(TI CD4029B)  | Presettable
Divide-By-N Counter(TI CD4018B)  |  |
2-6V  | Presettable
Up/Down Counter
(TI SN74HC191)  |  | 12-Bit Asynchronous
Bin Counter
(TI SN74HC4040)  |
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3-18V  | BCD-to-Decimal or
Binary-to-Octal
4to10 demux
(TI CD4028B)  | BCD-to-hex or
4to16 demux
(TI CD4515B)  | 2bit to 1-4 selector
demux DUAL
(TI CD4556B)  |
2-6V  | BCD-to-Decimal or
Binary-to-Octal
4to10 demux
(TI SN74HC42)  | BCD-to-hex or
4to16 demux
(TI CD74HC154)  | 2bit to 1-4 selector
demux DUAL
(TI CD74HC139)  | BCD-to-7 Segment LED
Latch/Decoder/Driver
(TI CD74HC4511)

## Reference books

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Digital Principles And Design - Donald D Givone Sanador 11:38, 13 March 2009 (UTC)Santosh A G

## Online resources

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## Learning projects

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## Research projects

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Debugging for RedHawk Duels: When trying to compile ship_proto.v first open ship_proto_assignment_defaults.qdf. Then change INCREMENTAL_COMPILATION to off (line 595). The code should then compile.

If this does not work, you may have to add the statement >>set_global_assignment -name INCREMENTAL_COMPILATION OFF<< in the .qdf file

## News

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## Wikiversity activities

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### Active participants

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* Kaushani123 18:50, 5 April 2009 (UTC)

### To do

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## See also

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Back to: Topic:Electronic Engineering

EE111 Edit/View

* Electronic Engineering * EE Digital Electronics * Lecture, Number systems and logic states * Lecture, Digital Logic Gates * Lecture, Combinatorial Functions * Lecture, Karnaugh Map Reductions * Lecture, Arithmetic * Lecture, Flip-flops * Mid-term Exam * Lecture, Sequential Logic * Lecture, Memory Elements * Lecture, Registers and Counters * Lecture, Advanced Sequential Circuits * Lecture, Logic Simulation * Lecture, High Level Language Logic Modelling and Synthesis * Final Exam

| Educational level: this is a tertiary (university) resource.

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| Type classification: this resource is a course.

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| Subject classification: this is an engineering resource.

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