HDL Coding Guidelines

Coding of circuit behaviour and architecture is one of the most critical steps in the whole chip development project. It has a major impact on logic synthesis, routing results, timing robustness, verifiability and testability. The HDL Coding Guidelines help chip and macro developers/teams to rapidly understand each other's code. Macro based designs integrate easier if these common coding styles are followed. This also applies to externally developed softcores. Codes will not need modification if simulator, synthesis tool, or technology is exchanged. Code invariants with respect to Synthesis tool is given in case of a similar HDL synthesis subset. Code invariants with respect to technology is given in case of similar performance and cell set. In addition, the given guidelines enable high synthesis quality and simulation performance.

The HDL Coding Guidelines need continuous adaptation according to new tool properties and new upcoming methodologies. Please participate in this process with your design know-how. Contribute rules for HDL coding that turned out to prevent errors in the downstream flow, or recommendations that alleviate further design, re-use or maintenance.

The HDL Coding Guidelines may be passed to sub-contractors or cooperation partners. Ideally their coding works should comply to these guidelines, enabling rapid and safe integration with internally developed modules.

Reading of the HDL Coding Guidelines is most efficient at the beginning of a chip-design-project. Furthermore a code review should be considered in a very early phase of HDL coding.

## External Links

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* Delay Modelling & Coding Guidelines
* Good Verilog Coding Guidelines