Superscalar

This material is still under construction. Outline below:

## Superscalar Microprocessor

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Superscalar processors simply mean that they execute more than one instruction per clock cycle. However, the dataflow in most software programs tends to be serial in nature. Instructions that have a dataflow dependency on each other cannot execute in parallel. For example, the classical IF statement will compile down the sequence shown below in machine assembly language:

IF ( condition ) THEN

some code

ELSE

other code

ENDIF

LOAD COMPARE BRANCH.CONDITIONAL

All three instructions must execute serially. The COMPARE depends on the completion of the LOAD instruction. The BRNACH in turn depends on the completion of the COMPARE operation.

Superscalar microprocessors depend heavily on the compiler's ability to re-order the instruction stream at compile time in order to maximize the opportunity for instruction level parallelism.

## Degrees of Parallelism

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## Out of Order Execution

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## Speculative Execution

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Branch following

Branch folding

Speculative Memory read

Speculative Memory store

## Industry Examples

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MIPS Architecture

Intel Architecture

Precision Architecture

Power Architecture

Sparc Architecture

ARM Architecture