The necessities in Computer Design

* control and data paths
* pipeline design
* cache design

## Contents

* 1 Introduction
* 1.1 Combinational Circuits
* 1.2 Sequential Circuits
* 1.3 FSM (Finite State Machine)
* 2 Control Unit Design Techniques
* 2.1 ASM (Algorithmic State Machine)
* 2.2 One Hot Designs
* 2.3 Microprogramming
* 3 Data Unit Design Techniques
* 3.1 Pipeline
* 3.2 Multiplier
* 4 Memory System Design Techniques
* 4.1 Cache Memories
* 4.2 Virtual Memories
* 4.3 Memory Banks
* 4.4 Interleaved Banks
* 5 IO Design Techniques
* 5.1 Interrupt
* 5.2 Memory Mapped IO
* 5.3 Intersystem Communication
* 5.4 Peripherals and Interfacing
* 6 Practicing Design
* 6.1 Implementation Techniques
* 6.2 Tiny CPU Architecture Examples
* 6.3 C to HDL Exercises
* 7 External links

##  Introduction [edit | edit source]

### Combinational Circuits[edit | edit source]

* Bubble Pushing (pdf)

* See Understanding Arithmetic Circuits

\- Carry Look-ahead Adder (CLA)
\- Carry Save Adder (CSA)
\- Prefix Adder (Prefix)* Multiplier
\- Divider

* ALU (Arithmetic Logical Unit)

### Sequential Circuits[edit | edit source]

* Types of Flip-Flops (1A.pdf)

* FF Metastability (pdf)
* FF Min Max Timing Constraints (pdf)
* FF Clock Skew Timing Constraints (pdf)

* Synchronizer (pdf)
* Resolution Time Analysis (pdf)

### FSM (Finite State Machine)[edit | edit source]

* FSM State Encoding
* FSM Types : Mealy and Moore Machines
* FSM Example (pdf)

##  Control Unit Design Techniques [edit | edit source]

### ASM (Algorithmic State Machine)[edit | edit source]

* ASM (pdf)

\- Reese's Lecture Note

### One Hot Designs[edit | edit source]

* One Hot Design (pdf)

### Microprogramming[edit | edit source]

* Microprogramming Design (pdf)

##  Data Unit Design Techniques [edit | edit source]

### Pipeline[edit | edit source]

* Pipeline (4A.pdf)
* Latch Based Pipeline (4B.pdf)

* Latch Time Borrow (4C.pdf)

### Multiplier[edit | edit source]

* Barrel Shifter (3A.pdf)
* Booth Multiplier

##  Memory System Design Techniques [edit | edit source]

### Cache Memories[edit | edit source]

* Content Addressable Memory (pdf)
* Address Partition (pdf)
* Cache Mapping (pdf)

### Virtual Memories[edit | edit source]

### Memory Banks[edit | edit source]

### Interleaved Banks[edit | edit source]

##  IO Design Techniques [edit | edit source]

### Interrupt[edit | edit source]

* Interrupt (pdf)

### Memory Mapped IO[edit | edit source]

* Memory Mapped IO (pdf)

### Intersystem Communication[edit | edit source]

* Intersystem Communication (pdf)

### Peripherals and Interfacing[edit | edit source]

##  Practicing Design [edit | edit source]

### Implementation Techniques[edit | edit source]

* (HW/SW Implementation Overview )

Implementation in Hardware

* (RTL Design Examples)
* (Gate Level Design Examples)
* (Transistor Level Design Examples)

Implementation in Software

* (SW Implementation Without an OS (Bare Machine))
* (SW Implementation with an RTOS)

* valvano

### Tiny CPU Architecture Examples[edit | edit source]

* Instruction Set (pdf)
* Data Path (pdf)
* Control Path (pdf)
* FPGA Implementation (pdf)

### C to HDL Exercises[edit | edit source]

* HDL Exercises (A.pdf)

go to [ Electrical_&_Computer_Engineering_Studies ]

## External links[edit | edit source]

* Qucs
* tkgate