LEON

LEON (from Spanish: león meaning lion) is a radiation-tolerant 32-bit central processing unit (CPU) microprocessor core that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems. It was originally designed by the European Space Research and Technology Centre (ESTEC), part of the European Space Agency (ESA), without any involvement by Sun. Later versions have been designed by Gaisler Research, under a variety of owners. It is described in synthesizable VHSIC Hardware Description Language (VHDL). LEON has a dual license model: An GNU Lesser General Public License (LGPL) and GNU General Public License (GPL) free and open-source software (FOSS) license that can be used without licensing fee, or a proprietary license that can be purchased for integration in a proprietary product.^[3][4] The core is configurable through VHDL generics, and is used in system on a chip (SOC) designs both in research and commercial settings.^[5]

History

The LEON project was begun by the European Space Agency (ESA) in late 1997 to study and develop a high-performance processor to be used in European space projects.^[6] The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost. Another objective was to be able to manufacture in a single-event upset (SEU) tolerant sensitive semiconductor process. To maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed. The goals have been to detect and tolerate one error in any register without software intervention, and to suppress effects from Single Event Transient (SET) errors in combinational logic.

The LEON family includes the first LEON1 VHSIC Hardware Description Language (VHDL) design that was used in the LEONExpress test chip developed in 0.25 μm technology to prove the fault-tolerance concept. The second LEON2 VHDL design was used in the processor device AT697 from Atmel (F) and various system-on-chip devices. These two LEON implementations were developed by ESA. Gaisler Research, now part of Cobham (and previously Aeroflex Gaisler), developed the third LEON3 design and has announced the availability of the fourth generation LEON, the LEON4 processor.^[7]

LEON processor models and distributions

A LEON processor can be implemented in programmable logic such as a field-programmable gate array (FPGA) or manufactured into an application-specific integrated circuit (ASIC). This section and the subsequent subsections focus on the LEON processors as soft IP cores and summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution.

All processors in the LEON series use the SPARC V8 reduced instruction set computer (RISC) ISA. LEON2(-FT) has a five-stage pipeline while later versions have a seven-stage pipeline. LEON2 and LEON2-FT are distributed as a system-on-chip design that can be modified using a graphical configuration tool. While the LEON2(-FT) design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design.

The standard LEON2(-FT) distribution includes the following support cores:^[8]

• Interrupt controller
• Debug support unit with trace buffer
• Two 24-bit timers
• Two universal asynchronous receiver-transmitters (UARTs)
• 16-bit I/O port
• Memory controller.

The LEON3, LEON3FT, and LEON4 cores are typically used together with the GRLIB IP Library. While the LEON2 distributions contain one design that can be used on several target technologies, GRLIB contains several template designs, both for FPGA development boards and for ASIC targets that can be modified using a graphical configuration tool similar to the one in the LEON2 distribution. The LEON/GRLIB package contains a larger number of cores compared to the LEON2 distributions and also include a plug and play (PnP) extension to the on-chip Advanced Microcontroller Bus Architecture (AMBA) bus. IP cores available in GRLIB also include:^[9]

• 32-bit PC133 synchronous dynamic random-access memory (SDRAM) controller
• 32-bit Peripheral Component Interconnect (PCI) bridge with direct memory access (DMA)
• 10/100/1000 Mbit Ethernet media access control address (MAC address)
• 8/16/32-bit programmable read-only memory (PROM) and static random-access memory (SRAM) controller
• 16/32/64-bit DDR/DDR2 controllers
• Universal Serial Bus (USB) 2.0 host and device controllers
• Controller area network (CAN) controller
• JTAG TAP controller
• Serial Peripheral Interface (SPI) controller
• Inter-Integrated Circuit (I²C) controller
• Universal asynchronous receiver-transmitter (UART) with first in, first out (FIFO)
• Modular timer unit
• Interrupt controller
• 32-bit general-purpose I/O (GPIO) port

FPGA design flow

Design flow documentation for the LEON into FPGA are available from the manufacturer^[10] and from third party resources.^[11]

Terminology

The term LEON2/LEON2-FT often refer to the LEON2 system-on-chip design, which is the LEON2 processor core together with the standard set of peripherals available in the LEON2(-FT) distribution. Later processors in the LEON series are used in a wide range of designs and are therefore not as tightly coupled with a standard set of peripherals. With LEON3 and LEON4 the name typically refers to only the processor core, while LEON/GRLIB is used to refer to the complete system-on-chip design.

LEON2 processor core

LEON2 has the following characteristics:

• The GNU LGPL allows a high degree of freedom of intervention on the freely available source code.
• Configurability is a key feature of the project,^[12] and is achieved through the usage of VHDL generics.^[13]
• It offers all basic functions of a pipelined in-order processor.
• It is a fairly sized VHDL project (about 90 files, for the complete LEON2 distribution, including peripheral IP cores)

LEON2-FT processor core

The LEON2-FT processor is the single-event upset fault tolerant (FT) version of the LEON2 processor. Flip-flops are protected by triple modular redundancy and all internal and external memories are protected by EDAC or parity bits. Special licence restrictions apply to this IP (distributed by the European Space Agency^[8]). Among other satellites, the processor was used in ESA's Intermediate eXperimental Vehicle (IXV) in 2015^[14] and China's Chang'e 4 lunar lander.^[15]

LEON3 processor core

The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SoC) designs. The full source code is available under the GNU GPL license, allowing use for any purpose without licensing fee. LEON3 is also available under a proprietary license, allowing it to be used in proprietary applications.

There are several differences between the two LEON2 processor models and the LEON3. LEON3 includes SMP support and a seven-stage pipeline, while LEON2 does not support SMP and has a five-stage pipeline.

LEON3FT processor core

The LEON3FT is a fault-tolerant version of the standard LEON3 SPARC V8 Processor. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct single-event upset (SEU) errors in all on-chip RAM memories. The LEON3FT processor supports most of the functionality in the standard LEON3 processor, and adds the following features:

• Register file SEU error-correction of up to 4 errors per 32-bit word
• Cache memory error-correction of up to 4 errors per tag or 32-bit word
• Autonomous and software transparent error handling
• No timing impact due to error detection or correction

The following features of the standard LEON3 processor are not supported by LEON3FT

• Local scratchpad RAM (neither for instruction nor for data)
• Cache locking
• LRR (least recently replaced) cache replacement algorithm

The LEON3FT core is distributed together with a special FT version of the GRLIP IP library. Only netlist distribution is possible.

An FPGA implementation called LEON3FT-RTAX was proposed for critical space applications.^[16]

LEON4 processor core

In January 2010, the fourth version of the LEON processor was released.^[7] This release has the following new features:

• Static branch prediction added to pipeline
• Optional level-2 cache
• 64-bit or 128-bit path to AMBA AHB interface
• Higher performance possible (claimed by manufacturer: 1.7 DMIPS/MHz as opposed to 1.4 DMIPS/MHz of LEON3)
• Rad hardened.^[1]

LEON5 processor core

Under development.^[17]

Real-time OS support

The Real-time operating systems that support the LEON core are currently RTLinux, PikeOS, eCos, RTEMS, Nucleus, ThreadX, OpenComRTOS, VxWorks (a port by Gaisler Research), LynxOS (also a port by Gaisler Research), POK^[18] (a free ARINC653 implementation released under the BSD licence) and ORK+,^[19] an open-source real-time kernel for high-integrity real-time applications with the Ravenscar Profile, Embox^[20] an open-source configurable real-time OS which allows using Linux software without Linux.

See also

• OpenSPARC
• S1 Core
• OpenRISC
• ERC32
• FeiTeng-1000
• Soft microprocessor
• Schiaparelli EDM lander

References

External links

• SPARC: Open Source at Curlie
• Cobham Gaisler
• GR740: The ESA Next Generation Microprocessor (NGMP)
• Cobham: Radiation Hardened Solutions and High Reliability Components
• LEON3 tutorial
• GNU/Linux on the SPARC architecture with original port on LEON

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