Table of Contents Categories
  Encyclosphere.org ENCYCLOREADER
  supported by EncyclosphereKSF

SHAKTI (microprocessor)

Topic: Engineering

 From HandWiki - Reading time: 6 min
Short description: Technology project funded by the Government of India
Shakti
General Info
Designed byIndian Institute of Technology, Madras
Common manufacturer(s)
Architecture and classification
ApplicationSoC, development boards, based software platform, IOT
Instruction setRISC-V
Model(s)
  • E-Class
  • C-Class
  • I-Class
  • M-Class
  • S-Class
  • H-Class
History

SHAKTI is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at Indian Institute of Technology, Madras to develop the first indigenous Indian industrial-grade processor.[1] The aim of SHAKTI initiative includes building an opensource production-grade processor, complete system on chips (SoCs), development boards and SHAKTI based software platform. The primary focus of the team is architecture research to develop SoCs, which is competitive with commercial offerings in the market concerning area, power and performance. All the source codes for SHAKTI are open-sourced under the Modified BSD License. The project was funded by the Ministry of Electronics and Information Technology (MeITY), Government of India.[2][1]

A prototype version of the new shakti microcontroller.

Processors

SHAKTI processors are based on the RISC-V ISA. The processors are designed to have either 22 nm FinFET or 180 nm CMOS technology nodes depending on the manufacturing foundry.

SHAKTI has envisioned a family of processors as part of its road-map, catering to different segments of the market. They have been broadly categorized into "Base Processors", "Multi-Core Processors" and "Experimental Processors".

The E and C-classes core are aimed at Internet of things (IoT), embedded and desktop markets. The processor design is free of any royalty and is open-sourced under the modified BSD License.[3]

E-class and C-class core are both implemented in Bluespec SystemVerilog (BSV) language.[1]

The SHAKTI project aims to build 6 variants of processors based on the RISC-V ISA.

Base classes of processors

E-class

The E-class are 32/64 bit microcontrollers capable of supporting all extensions of the RISC-V ISA, aimed at low-power and low computer applications. The E-class is an in-order 3 stage pipeline having an operational frequency of less than 200 MHz on silicon. It is positioned against ARM’s M-class (Cortex-M series) cores. It is capable of running real-time operating systems like FreeRTOS, Zephyr and eChronos. Market segments of E-class processor support smart cards, IoT devices, motor controls and robotic platforms.[4][5]

E-arty35T is a SoC built around E-class. The E-arty35T SoC is a single-chip 32-bit E-class microcontroller with 128kB RAM. It has 32 General-purpose input/output (GPIO) pins (out of which upper 16 GPIO pins are dedicated to onboard LEDs and switches), a Platform Level Interrupt Controller (PLIC), a Counter, 2 Serial Peripheral Interface (SPI), 2 universal asynchronous receiver-transmitter (UART), 1 Inter-Integrated Circuit (I2C), 6 Pulse-width modulator (PWM) and an inbuilt Xilinx analog-to-digital converter (X-ADC).[6]

C-class

The C-class is a 64-bit controller class of processor, aimed at mid-range embedded application. The core is highly optimized, 6-stage in-order design with MMU support and the capability to run operating systems like Linux and Sel4. It is extremely configurable with the support of the standard RV64GC ISA extensions. It targets mid-range compute systems running over 200-800 MHz. It can also be customized up to 2 GHz. It is positioned against ARM's Cortex A35/A55. The application domain of this class ranges from embedded systems, motor-control, IoT, storage, industrial applications to low-cost high-performance Linux based applications such as networking, gateways etc.[4][5]

C-arty100T is a SoC built around the C-class. The C-arty100T SoC is a single-chip 64-bit C-class microcontroller with 128MB DDR3 RAM, 16 General Purpose Input Output (GPIO) pins, a Platform Level Interrupt Controller (PLIC), a Counter, 1 Universal Asynchronous Receiver Transmitter (UART) and 1 Inter-Integrated Circuit (I2C). It is aimed at mid-range application workloads with a very low power consumption and has support for optional memory protection.[7]

I-class

The I-class is a 64-bit processor which targets the compute, mobile, storage and networking platforms. Its features include out-of-order execution, multithreading, aggressive branch prediction, non-blocking caches and deep pipeline stages. The operational clock frequency of this processor is 1.5-2.5 GHz. The team is currently working on implementing atomics, Memory dependence prediction, Instruction Window/Scheduler optimizations, Implementation of some functional units, Performance analysis/projections, Optimizations to meet first-cut target frequency on 1 GHz on 22 nm processor.[5][8][9]

Multicore processors

M-class

A mobile class processor with a maximum of eight cores, the cores being a combination of C and I class cores. The M-class processors are aimed at general-purpose compute, low-end server and mobile applications. The operation frequency ranges up to 2.5 GHz. It supports large issue size, quad-threaded and optional NoC fabric. The M-class processors are optimized for various power and performance targets.[8]

S-class

The S-Class is a 64-bit superscalar, multi-threaded variant aimed at Desktop and Enterprise server Application. Its supports 2-16 cores with a clock frequency of about 1.2–3 GHz.[8]

H-class

The H-class is a 64-bit processor aimed at highly parallel enterprise, HPC and analytics applications. The cores can be a combination of C or I class, single-thread performance driving the core choice. The H-class has up to 128 cores with multiple accelerators per core.[8]

Experimental processors

These are experimental/research projects which focus on developing a high security and fault tolerant processor.

T-class

The T-class is aimed to provide additional hardware support for securing information from memory-based attacks. Its design focuses on a unified hardware framework for mitigating spatial and temporal memory attacks.[10]

F-class

The F-class is a fault-tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics.[11]

Tapeouts

Two C-class processors (codenamed RIMO and Risecreek) and one E-class processor (Moushik) have been taped-out so far.

RIMO

RIMO is the code name of the SHAKTI C-class based SoC that has been taped-out at Semi-Conductor Laboratory (SCL) at Mohali using 180 nm process technology. The 144 sq.mm. chip has been tested to operate at a frequency of up to 70 MHz. The chip has been packaged on a 208-pin Ceramic Quad Flat Pack (CQFP).[4]

Risecreek

CREEK is the code name of the SHAKTI C-class based SoC that has been taped-out at Intel's Oregon fab using a 22nm FinFET process. The 16mm² chip has been tested to operate at a frequency of up to 350 MHz. The chip has been packaged on a 208-pin Ball Grid Array (BGA).[4]

Moushik

Moushik is the code name of the SHAKTI E-class based SoC that has been taped-out at SCL using 180 nm process technology. It operates in frequency of 100 MHz and developed along with a motherboard called Ardonyx 1.0.[12]

Features of RIMO and Risecreek

Some of the features of RIMO and Risecreek are as follows:

  • In-order 5 stage 64-bit microcontroller supporting the entire stable RISC-V ISA(RV64IMAFD).
  • Compatible with privilege spec (v1.10) of RISC-V ISA and supports the sv39 virtualisation scheme.
  • Includes a branch predictor with a Return-Address-Stack.
  • Pipelined IEEE-754 compliant single and double-precision floating point units and Multi-channel Direct Memory Access (DMA) support.
  • Peripherals like 2 x I2C, 2 x UART, 2 x QSPI, a Debugger, a 256KB tightly coupled memory, 32-bit GPIOs and an expansion bus that can be connected to an FPGA.[4]

Development boards

There are development boards for both E and C class of processors. The details on the board support for different classes of processors are given below.

E-arty35T

  • E-arty35Tis a SoC based on SHAKTI E class [14].
  • E-arty35Tis supported on Artix 7 35T board.
  • It has an abridged version of 32 bit E class. It includes I, M, A and C.[6]

C-arty100T

  • C-arty100Tis a SoC based on SHAKTI C class.
  • C-arty100Tis supported on Artix 7 100T board.
  • It has an abridged version of 64 bit C class. It includes I, M, A, F, D and C.[7]

Commercial support

Altair Engineering from July 2021, included E-Class processor in its embedded system firmware support portfolio for its global customers.[13]

References

  1. ↑ 1.0 1.1 1.2 Veezhinathan, Kamakoti. "Building the SHAKTI Microprocessor" (in en). https://cacm.acm.org/magazines/2022/11/265822-building-the-shakti-microprocessor/fulltext. 
  2. ↑ "IIT-Madras Develops 'India's First Microprocessor', Shakti" (in en). 2 November 2018. https://gadgets.ndtv.com/mobiles/news/iit-madras-develops-indias-first-microprocessor-shakti-1941909. 
  3. ↑ Gala, Neel; Menon, Arjun; Bodduna, Rahul; Madhusudan, G. S.; Kamakoti, V. (January 2016). "SHAKTI Processors: An Open-Source Hardware Initiative". 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID). pp. 7–8. doi:10.1109/VLSID.2016.130. ISBN 978-1-4673-8700-2. https://ieeexplore.ieee.org/document/7434907. 
  4. ↑ 4.0 4.1 4.2 4.3 4.4 "SHAKTI DEVELOPMENT BOARD USER MANUAL". https://shakti.org.in/docs/user_manual.pdf. 
  5. ↑ 5.0 5.1 5.2 "Shakti - The Open Source Indian Microprocessor & Microcontroller" (in en-US). 2020-04-07. https://engineersasylum.com/t/shakti-the-open-source-indian-microprocessor-microcontroller/664. 
  6. ↑ 6.0 6.1 "E-Class on ARTY-A7-35t Board" (in en). https://gitlab.com/shaktiproject/cores/shakti-soc/tree/master/fpga/boards/artya7-35t/e-class. 
  7. ↑ 7.0 7.1 "C-Class on ARTY-A7-100t Board" (in en). https://gitlab.com/shaktiproject/cores/shakti-soc/tree/master/fpga/boards/artya7-100t/c-class. 
  8. ↑ 8.0 8.1 8.2 8.3 "Processors". https://shakti.org.in/processors.html. 
  9. ↑ Ranganathan, Nitya. "Shakti I Class: Introduction". https://shakti.org.in/docs/shaktiweek-i-class.pdf. 
  10. ↑ "Shakti-T: A RISC-V Processor with Light Weight Security Extensions" (in EN). 25 June 2017. pp. 1–8. doi:10.1145/3092627.3092629. ISBN 9781450352666. https://dl.acm.org/doi/abs/10.1145/3092627.3092629. Retrieved 2020-04-10. 
  11. ↑ Gupta, Sukrat; Gala, Neel; Madhusudan, G. S.; Kamakoti, V. (November 2015). "SHAKTI-F: A Fault Tolerant Microprocessor Architecture". 2015 IEEE 24th Asian Test Symposium (ATS). pp. 163–168. doi:10.1109/ATS.2015.35. ISBN 978-1-4673-9739-1. https://ieeexplore.ieee.org/document/7422253. 
  12. ↑ "Meet India's Atmanirbhar Microprocessor chip 'Moushik', meant for IoT devices" (in en). https://www.wionews.com/india-news/meet-indias-atmanirbhar-microprocessor-chip-moushik-meant-for-iot-devices-329966. 
  13. ↑ MP, Sidharth (6 July 2021). "India's home-grown microprocessor Shakti is now part of tech-giant Altair's offerings" (in en). https://www.wionews.com/technology/indias-home-grown-microprocessor-shakti-is-now-part-of-tech-giant-altairs-offerings-396147. 

External links



Retrieved from "https://handwiki.org/wiki/index.php?title=Engineering:SHAKTI_(microprocessor)&oldid=3717103"
Licensed under CC BY-SA 3.0 | Source: https://handwiki.org/wiki/Engineering:SHAKTI_(microprocessor)
9 views | Status: cached on August 14 2024 03:43:14
↧ Download this article as ZWI file
Encyclosphere.org EncycloReader is supported by the EncyclosphereKSF