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Semiconductor device fabrication

Topic: Engineering

 From HandWiki - Reading time: 22 min
Short description: Manufacturing process used to create integrated circuits
NASA's Glenn Research Center clean room
External image
Photo of the interior of a clean room of a 300mm fab run by TSMC

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips (such as NAND flash and DRAM) that are present in everyday electronic devices. It is a multiple-step photolithographic and physio-chemical process (with steps such as thermal oxidation, thin-film deposition, ion-implantation, etching) during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

The fabrication process is performed in highly specialized semiconductor fabrication plants, also called foundries or "fabs",[1] with the central part being the "clean room". In more advanced semiconductor devices, such as modern 14/10/7 nm nodes, fabrication can take up to 15 weeks, with 11–13 weeks being the industry average.[2] Production in advanced fabrication facilities is completely automated, with automated material handling systems taking care of the transport of wafers from machine to machine.[3]

A wafer often has several integrated circuits which are called dies as they are pieces diced from a single wafer. Individual dies are separated from a finished wafer in a process called die singulation, also called wafer dicing. The dies can then undergo further assembly and packaging.[4]

Within fabrication plants, the wafers are transported inside special sealed plastic boxes called FOUPs.[3] FOUPs in many fabs contain an internal nitrogen atmosphere[5][6] which helps prevent copper from oxidizing on the wafers. Copper is used in modern semiconductors for wiring.[7] The insides of the processing equipment and FOUPs is kept cleaner than the surrounding air in the cleanroom. This internal atmosphere is known as a mini-environment and helps improve yield which is the amount of working devices on a wafer. This mini environment is within an EFEM (equipment front end module)[8] which allows a machine to receive FOUPs, and introduces wafers from the FOUPs into the machine. Additionally many machines also handle wafers in clean nitrogen or vacuum environments to reduce contamination and improve process comtrol.[3] Fabrication plants need large amounts of liquid nitrogen to maintain the atmosphere inside production machinery and FOUPs, which are constantly purged with nitrogen.[5][6] There can also be an air curtain between the FOUP and the EFEM which helps reduce the amount of humidity that enters the FOUP and improves yield.[9][10]

Companies that manufacture machines used in the industrial semiconductor fabrication process include ASML, Applied Materials, and Lam Research.

Feature size

A specific semiconductor process has specific rules on the minimum size (width or CD) and spacing for features on each layer of the chip.[11] Normally a new semiconductor process has smaller minimum sizes and tighter spacing. In some cases, this allows a simple die shrink of a currently produced chip design to reduce costs, improve performance,[11] and increase transistor density (number of transistors per square millimeter) without the expense of a new design.

Early semiconductor processes had arbitrary names for generations (viz., HMOS I/II/III/IV and CHMOS III/III-E/IV/V). Later each new generation process became known as a technology node[12] or process node,[13][14] designated by the process' minimum feature size in nanometers (or historically micrometers) of the process's transistor gate length, such as the "90 nm process". However, this has not been the case since 1994,[15] and the number of nanometers used to name process nodes (see the International Technology Roadmap for Semiconductors) has become more of a marketing term that has no standardized relation with functional feature sizes or with transistor density (number of transistors per square millimeter).[16]

Initially transistor gate length was smaller than that suggested by the process node name (e.g. 350 nm node); however this trend reversed in 2009.[15] Feature sizes can have no connection to the nanometers (nm) used in marketing. For example, Intel's former 10 nm process actually has features (the tips of FinFET fins) with a width of 7 nm, so the Intel 10 nm process is similar in transistor density to TSMC's 7 nm process. As another example, GlobalFoundries' 12 and 14 nm processes have similar feature sizes.[17][18][16]

History

20th century

An improved type of MOSFET technology, CMOS, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963.[19][20] CMOS was commercialised by RCA in the late 1960s.[19] RCA commercially used CMOS for its 4000-series integrated circuits in 1968, starting with a 20 µm process before gradually scaling to a 10 µm process over the next several years.[21]

Semiconductor device manufacturing has since spread from Texas and California in the 1960s to the rest of the world, including Asia, Europe, and the Middle East.

21st century

The semiconductor industry is a global business today. The leading semiconductor manufacturers typically have facilities all over the world. Samsung Electronics, the world's largest manufacturer of semiconductors, has facilities in South Korea and the US. Intel, the second-largest manufacturer, has facilities in Europe and Asia as well as the US. TSMC, the world's largest pure play foundry, has facilities in Taiwan, China, Singapore, and the US. Qualcomm and Broadcom are among the biggest fabless semiconductor companies, outsourcing their production to companies like TSMC.[22] They also have facilities spread in different countries.

Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.[23][24][25] For example, GlobalFoundries' 7 nm process is similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred.[26] Additionally, TSMC and Samsung's 10 nm processes are only slightly denser than Intel's 14 nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the exact same as that of Intel's 14 nm process: 42 nm).[27][28]

As of 2019, 14 nanometer and 10 nanometer chips are in mass production by Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory and GlobalFoundries, with 7 nanometer process chips in mass production by TSMC and Samsung, although their 7 nanometer node definition is similar to Intel's 10 nanometer process. The 5 nanometer process began being produced by Samsung in 2018.[29] As of 2019, the node with the highest transistor density is TSMC's 5 nanometer N5 node,[30] with a density of 171.3 million transistors per square millimeter.[31] In 2019, Samsung and TSMC announced plans to produce 3 nanometer nodes. GlobalFoundries has decided to stop the development of new nodes beyond 12 nanometers in order to save resources, as it has determined that setting up a new fab to handle sub-12 nm orders would be beyond the company's financial abilities.[32] Intel has changed the name of its 10 nm process to position it as a 7 nm process.[33]

List of steps

This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order, nor that all techniques are taken during manufacture as, in practice the order and which techniques are applied, are often specific to process offerings by foundries, or specific to an integrated device manufacturer (IDM) for their own products, and a semiconductor device might not need all techniques. Equipment for carrying out these processes is made by a handful of companies. All equipment needs to be tested before a semiconductor fabrication plant is started.[34] These processes are done after integrated circuit design. A semiconductor fab operates 24/7.[35]

Additionally steps such as Wright etch may be carried out.

Progress of miniaturization, and comparison of sizes of semiconductor manufacturing process nodes with some microscopic objects and visible light wavelengths

Prevention of contamination and defects

Main page: Engineering:Cleanroom

When feature widths were far greater than about 10 micrometres, semiconductor purity was not as big of an issue as it is today in device manufacturing. As devices become more integrated, cleanrooms must become even cleaner. Today, fabrication plants are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The ceilings of semiconductor cleanrooms have fan filter units (FFUs) at regular intervals to constantly replace and filter the air in the cleanroom; semiconductor capital equipment may also have their own FFUs to clean air in the equipment's EFEM which allows the equipment to receive wafers in FOUPs. The FFUs, combined with raised floors with grills, help ensure a laminar air flow, to ensure that particles are immediately brought down to the floor and do not stay suspended in the air due to turbulence. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from contamination by humans.[51] Tto increase yield, FOUPs and semiconductor capital equipment may have a mini environment with ISO class 1 level of dust, and FOUPs can have an even cleaner micro environment.[10][8] FOUPs and SMIF pods isolate the wafers from the air in the cleanroom, increasing yield because they reduce the number of defects caused by dust particles. Also, fabs have as few people as possible in the cleanroom to make maintaining the cleanroom environment easier, since people, even when wearing cleanroom suits, shed large amounts of particles, especially when walking.[52][51][53]

Wafers

A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.

Processing

In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.

  • Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD) among others. Deposition can be understood to include oxide layer formation, by thermal oxidation or, more specifically, LOCOS.
  • Removal is any process that removes material from the wafer; examples include etch processes (either wet or dry) and chemical-mechanical planarization (CMP).
  • Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called an aligner or stepper focuses a mask image on the wafer using short-wavelength light; the exposed regions (for "positive" resist) are washed away by a developer solution. After Removal or other processing, the remaining photoresist is removed by "dry" plasma ashing or by "wet" chemistry.[54]
  • Modification of electrical properties has historically entailed doping transistor sources and drains and polysilicon (originally by diffusion furnaces and later by ion implantation). These doping processes are followed by furnace annealing or, in advanced devices, by rapid thermal annealing (RTA) to activate the dopants. Modification of electrical properties now also extends to the reduction of a material's dielectric constant in low-κ insulators via exposure to ultraviolet light in UV processing (UVP). Modification is frequently achieved by oxidation, which can be carried out to create semiconductor-insulator junctions, such as in the local oxidation of silicon (LOCOS) to fabricate metal oxide field effect transistors. Modern chips have up to eleven or more metal levels produced in over 300 or more sequenced processing steps.

Front-end-of-line (FEOL) processing

FEOL processing refers to the formation of the transistors directly in the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a straining step wherein a silicon variant such as silicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called silicon on insulator technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effects. Semiconductor equipment may have several chambers which process wafers in processes such as deposition and etching. Many pieces of equipment handle wafers between these chambers in an internal nitrogen or vacuum environment to improve process control.[3]


Gate oxide and implants

Main pages: Engineering:Self-aligned gate  and Physics:Doping (semiconductor)

Front-end surface engineering is followed by growth of the gate dielectric (traditionally silicon dioxide), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In dynamic random-access memory (DRAM) devices, storage capacitors are also fabricated at this time, typically stacked above the access transistor (the now defunct DRAM manufacturer Qimonda implemented these capacitors with trenches etched deep into the silicon surface).

Back-end-of-line (BEOL) processing

Metal layers

Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with back end of chip fabrication, which refers to the packaging and testing stages). BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material has traditionally been a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers. High-κ dielectrics such as Hafnium oxide[55][56] or hafnium silicon oxynitride[3] may be used instead starting from the 45nm node together with metal gates.[57][58]

Interconnect

Main page: Engineering:Interconnect (integrated circuits)
Synthetic detail of a standard cell through four layers of planarized copper interconnect, down to the polysilicon (pink), wells (greyish) and substrate (green)

Historically, the metal wires have been composed of aluminum. In this approach to wiring (often called subtractive aluminum), blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes (called "vias") in the insulating material and then depositing tungsten in them with a CVD technique using tungsten hexafluoride; this approach can still be (and often is) used in the fabrication of many memory chips such as dynamic random-access memory (DRAM), because the number of interconnect levels can be small (no more than four).

More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to copper interconnect layer) and a change in dielectric material (from silicon dioxides to newer low-κ insulators). This performance enhancement also comes at a reduced cost via damascene processing, which eliminates processing steps. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP (chemical-mechanical planarization) is the primary processing method to achieve such planarization, although dry etch back is still sometimes employed when the number of interconnect levels is no more than three. Copper interconnects use an electrically conductive barrier layer to prevent the copper from diffusing into ("poisoning") its surroundings, often made of tantalum nitride.[59]

Wafer test

The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index, and extinction coefficient of photoresist and other coatings.[60] Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself.[1]

Device test

Main page: Engineering:Wafer testing

Once the front-end process has been completed, the semiconductor devices or chips are subjected to a variety of electrical tests to determine if they function properly. The percent of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields,[61] but it can be as low as 30%, meaning that only 30% of the chips on the wafer work as intended. Process variation is one among many reasons for low yield. Testing is carried out to prevent faulty chips from being assembled into relatively expensive packages.

The yield is often but not necessarily related to device (die or chip) size. As an example, In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their 5nm test chips with a die size of 17.92 mm2. The yield went down to 32.0% with an increase in die size to 100 mm2.[62] The number of killer defects on a wafer, regardless of die size, can be noted as the defect density (or D0) of the wafer per unit area, usually cm2.

The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data (results) are logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to predetermined test limits such as maximum operating frequencies/clocks, number of working (fully functional) cores per chip, etc. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging. Binning allows chips that would otherwise be rejected to be reused in lower-tier products, as is the case with GPUs and CPUs, increasing device yield, especially since very few chips are fully functional (have all cores functioning correctly, for example). eFUSEs may be used to disconnect parts of chips such as cores, either because they did not work as intended during binning, or as part of market segmentation (using the same chip for low, mid and high-end tiers). Chips may have spare parts to allow the chip to fully pass testing even if it has several non-working parts.

Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test". Chips may also be imaged using x-rays.

Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible because many testers have the resources to perform most or all of the tests in parallel and on several chips at once.

Chips are often designed with "testability features" such as scan chains or a "built-in self-test" to speed testing and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during testing, in order to achieve tightly distributed resistance values as specified by the design.

Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.

Device yield

Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.

Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as iron, copper, nickel, zinc, chromium, gold, mercury and silver, alkali metals such as sodium, potassium and lithium, and elements such as aluminum, magnesium, calcium, chlorine, sulfur, carbon, and fluorine. It is important for these elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove these elements from the silicon; different mixtures are effective against different elements.

Several models are used to estimate yield. They are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.[63]

Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect, due to their lower surface area on the wafer. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.[61]

Die preparation

Main pages: Engineering:Wafer backgrinding and Engineering:Die preparation

Once tested, a wafer is typically reduced in thickness in a process also known as "backlap",[64] "backfinish", "wafer backgrind" or "wafer thinning"[65] before the wafer is scored and then broken into individual dies, a process known as wafer dicing. Only the good, unmarked chips are packaged.

Packaging

Main page: Engineering:Integrated circuit packaging

Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny bondwires are used to connect the pads to the pins. In the 'old days' (1970s), wires were attached by hand, but now specialized machines perform the task. Traditionally, these wires have been composed of gold, leading to a lead frame (pronounced "leed frame") of solder-plated copper; lead is poisonous, so lead-free "lead frames" are now mandated by RoHS.

Chip scale package (CSP) is another packaging technology. A plastic dual in-line package, like most packages, is many times larger than the actual die hidden inside, whereas CSP chips are nearly the size of the die; a CSP can be constructed for each die before the wafer is diced.

The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser then etches the chip's name and numbers on the package.

Hazardous materials

Many toxic materials are used in the fabrication process.[66] These include:

It is vital that workers not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment.

Timeline of commercial MOSFET nodes

See also


References

  1. ↑ 1.0 1.1 Neurotechnology Group, Berlin Institute of Technology, IEEE Xplore Digital Library. "Regression Methods for Virtual Metrology of Layer Thickness in Chemical Vapor Deposition." January 17, 2014. . Retrieved November 9, 2015.
  2. ↑ "8 Things You Should Know About Water & Semiconductors" (in en-US). 11 July 2013. https://www.chinawaterrisk.org/resources/analysis-reviews/8-things-you-should-know-about-water-and-semiconductors/. 
  3. ↑ 3.0 3.1 3.2 3.3 3.4 Yoshio, Nishi (2017), Handbook of Semiconductor Manufacturing Technology, CRC Press 
  4. ↑ Lei, Wei-Sheng; Kumar, Ajay; Yalamanchili, Rao (2012-04-06). "Die singulation technologies for advanced packaging: A critical review". Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 30 (4): 040801. doi:10.1116/1.3700230. ISSN 2166-2746. Bibcode: 2012JVSTB..30d0801L. https://doi.org/10.1116/1.3700230. 
  5. ↑ 5.0 5.1 "Advanced FOUP purge using diffusers for FOUP door-off application | IEEE Conference Publication | IEEE Xplore". doi:10.1109/ASMC.2014.6846999. https://ieeexplore.ieee.org/document/6846999. 
  6. ↑ 6.0 6.1 "450mm FOUP/LPU system in advanced semiconductor manufacturing processes: A study on the minimization of oxygen content inside FOUP when the door is opened | IEEE Conference Publication | IEEE Xplore". https://ieeexplore.ieee.org/document/7328897. 
  7. ↑ "Moisture Prevention in a Pre-Purged Front-Opening Unified Pod (FOUP) During Door Opening in a Mini-Environment | IEEE Journals & Magazine | IEEE Xplore". doi:10.1109/TSM.2018.2791985. https://ieeexplore.ieee.org/document/8254366. 
  8. ↑ 8.0 8.1 Kure, Tokuo; Hanaoka, Hideo; Sugiura, Takumi; Nakagawa, Shinya (2007). "Clean-room Technologies for the Mini-environment Age". Hitachi Review 56 (3): 70–74. https://www.hitachi.com/rev/pdf/2007/r2007_03_109.pdf. Retrieved 2021-11-01. 
  9. ↑ "A Numerical Study on the Effects of Purge and Air Curtain Flow Rates on Humidity Invasion Into a Front Opening Unified Pod (FOUP) | IEEE Journals & Magazine | IEEE Xplore". doi:10.1109/TSM.2022.3209221. https://ieeexplore.ieee.org/document/9903006. 
  10. ↑ 10.0 10.1 "Performance of Different Front-Opening Unified Pod (FOUP) Moisture Removal Techniques With Local Exhaust Ventilation System | IEEE Journals & Magazine | IEEE Xplore". doi:10.1109/TSM.2020.2977122. https://ieeexplore.ieee.org/document/9018065. 
  11. ↑ 11.0 11.1 Shirriff, Ken (June 2020). "Die shrink: How Intel scaled-down the 8086 processor". https://www.righto.com/2020/06/die-shrink-how-intel-scaled-down-8086.html. 
  12. ↑ "Overall Roadmap Technology Characteristics". Semiconductor Industry Association. https://www.semiconductors.org/wp-content/uploads/2018/08/2003Overall-Roadmap-Technology-Characteristics.pdf. 
  13. ↑ Shukla, Priyank. "A Brief History of Process Node Evolution". https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html. 
  14. ↑ "Technology Node - WikiChip". https://en.wikichip.org/wiki/technology_node#:~:text=The%20technology%20node%20(also%20process,process%20and%20its%20design%20rules.&text=Generally%2C%20the%20smaller%20the%20technology,faster%20and%20more%20power-efficient.. 
  15. ↑ 15.0 15.1 Moore, Samuel K. (21 July 2020). "A Better Way To Measure Progress in Semiconductors". https://spectrum.ieee.org/a-better-way-to-measure-progress-in-semiconductors. 
  16. ↑ 16.0 16.1 Ridley, Jacob (April 29, 2020). "Intel 10nm isn't bigger than AMD 7nm, you're just measuring wrong". https://www.pcgamer.com/chipmaking-process-node-naming-lmc-paper/. 
  17. ↑ Cutress, Ian. "Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review". https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3. 
  18. ↑ "VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP". 22 July 2018. https://fuse.wikichip.org/news/1497/vlsi-2018-globalfoundries-12nm-leading-performance-12lp/. 
  19. ↑ 19.0 19.1 "1963: Complementary MOS Circuit Configuration is Invented". https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/. 
  20. ↑ Sah, Chih-Tang; Wanlass, Frank (February 1963). "Nanowatt logic using field-effect metal-oxide semiconductor triodes". VI. pp. 32–33. doi:10.1109/ISSCC.1963.1157450. 
  21. ↑ Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. p. 330. ISBN 9783540342588. https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330. Retrieved 2019-07-21. 
  22. ↑ "Top 10 Worldwide Semiconductor Sales Leaders - Q1 2017 - AnySilicon" (in en-US). AnySilicon. 2017-05-09. http://anysilicon.com/top-10-worldwide-semiconductor-sales-leaders-q1-2017/. 
  23. ↑ Shukla, Priyank. "A Brief History of Process Node Evolution". https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html. 
  24. ↑ Hruska, Joel (23 June 2014). "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists…". https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists. 
  25. ↑ "Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". 2016-09-10. https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/. 
  26. ↑ "Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms". 2018-03-12. https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/. 
  27. ↑ "10 nm lithography process - WikiChip". https://en.wikichip.org/wiki/10_nm_lithography_process#Industry. 
  28. ↑ "14 nm lithography process - WikiChip". https://en.wikichip.org/wiki/14_nm_lithography_process#Industry. 
  29. ↑ Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology. 
  30. ↑ Cheng, Godfrey (14 August 2019). "Moore's Law is not Dead". TSMC. https://www.tsmc.com/english/news-events/blog-article-20190814. 
  31. ↑ Schor, David (2019-04-06). "TSMC Starts 5-Nanometer Risk Production" (in en-US). https://fuse.wikichip.org/news/2207/tsmc-starts-5-nanometer-risk-production/. 
  32. ↑ Shilov, Anton; Cutress, Ian. "GlobalFoundries Stops All 7nm Development: Opts To Focus on Specialized Processes". https://www.anandtech.com/show/13277/globalfoundries-stops-all-7nm-development. 
  33. ↑ Cutress, Ian. "Intel's Process Roadmap to 2025: With 4nm, 3nm, 20A and 18A?!". https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros. 
  34. ↑ "Power outage partially halts Toshiba Memory's chip plant". Reuters. June 21, 2019. https://www.reuters.com/article/toshiba-chips-idUSL4N23S1UT. 
  35. ↑ Labor, U. S. Dept of (February 19, 2000). Occupational Outlook Handbook. JIST Publishing. ISBN 978-1-56370-677-6. https://books.google.com/books?id=jNfHxbfsys4C&dq=semiconductor+12+hour+shift&pg=PA489. 
  36. ↑ 36.0 36.1 Reinhardt, Karen; Kern, Werner (March 16, 2018). Handbook of Silicon Wafer Cleaning Technology. William Andrew. p. 223. ISBN 978-0-323-51085-1. https://books.google.com/books?id=3JOZDgAAQBAJ&dq=wafer+spin+cleaning&pg=PA223. Retrieved 8 January 2024. 
  37. ↑ Natraj Narayanswami (1999). "A Theoretical Analysis of Wafer Cleaning Using a Cryogenic Aerosol". Journal of the Electrochemical Society 146 (2): 767–774. doi:10.1149/1.1391679. Bibcode: 1999JElS..146..767N. https://iopscience.iop.org/article/10.1149/1.1391679/pdf. Retrieved 8 January 2024. 
  38. ↑ Hars, Adele (October 20, 2022). "Wafer Cleaning Becomes Key Challenge In Manufacturing 3D Structures". https://semiengineering.com/wafer-cleaning-becomes-key-challenge-in-manufacturing-3d-structures/. 
  39. ↑ Hattori, Takeshi (September 30, 2009). Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing 11. The Electrochemical Society. ISBN 978-1-56677-742-1. https://books.google.com/books?id=emRGQ4Ts7BAC&dq=wafer+spin+cleaning&pg=PA10. 
  40. ↑ Pelé, A-F. (29 March 2022). "Unlocking the Potential of Molecular Beam Epitaxy". AspenCore. https://www.eetimes.eu/unlocking-the-potential-of-molecular-beam-epitaxy. 
  41. ↑ Vogler, D. (19 November 2008). "Ion beam deposition goes 300mm with Aviza's new tool". Gold Flag Media. https://sst.semiconductor-digest.com/2008/11/ion-beam-deposition-goes-300mm-with-avizas-new-tool. 
  42. ↑ "Characterization of thin carbonized photoresist layer and investigation of dry strip process through real-time monitored variable temperature control | IEEE Conference Publication | IEEE Xplore". doi:10.1109/ASMC.2017.7969207. https://ieeexplore.ieee.org/document/7969207. 
  43. ↑ Einspruch, Norman G.; Brown, Dale M. (December 1, 2014). Plasma Processing for VLSI. Academic Press. ISBN 978-1-4832-1775-8. https://books.google.com/books?id=ZzGoBQAAQBAJ&dq=photoresist+dry+strip&pg=PA8. 
  44. ↑ Verhaverbeke, S.; Beaudry, C.; Boelen, P. (2004). Aqueous Single Pass Single Wafer AI/Via Cleaning. Electrochemical Society. pp. 23–26. https://books.google.com/books?id=KSr1FWUgvz4C&dq=photoresist+dry+strip&pg=PA23. Retrieved 8 January 2024. 
  45. ↑ "Laser Lift-Off(LLO) Ideal for high brightness vertical LED manufacturing - Press Release - DISCO Corporation". https://www.disco.co.jp/eg/news/press/20151207.html. 
  46. ↑ "Product Information | Polishers - DISCO Corporation". https://www.disco.co.jp/eg/products/polisher_etcher/index.html. 
  47. ↑ "Product Information | DBG / Package Singulation - DISCO Corporation". https://www.disco.co.jp/eg/products/process/index.html. 
  48. ↑ "Plasma Dicing (Dice Before Grind) | Orbotech". https://www.orbotech.com/spts/about/resources/tech-insights/mems-tech-insights/plasma-dicing-dbg. [yes|permanent dead link|dead link}}]
  49. ↑ "Electro Conductive Die Attach Film(Under Development) | Nitto". https://www.nitto.com/us/en/products/group/semicon/dicing/007/. 
  50. ↑ "Die Attach Film Adhesives". https://www.henkel-adhesives.com/us/en/products/industrial-adhesives/die-attach-adhesives/die-attach-film-adhesives.html. 
  51. ↑ 51.0 51.1 "Study into human particle shedding". https://www.cleanroomtechnology.com/news/article_page/Study_into_human_particle_shedding/62768. 
  52. ↑ "The ASYST SMIF system - Integrated with the Tencor Surfscan 7200". https://www.chiphistory.org/159-asyst-smif-system. 
  53. ↑ Miller, Michael J. (February 15, 2018). "How a Chip Gets Made: Visiting GlobalFoundries". https://www.pcmag.com/news/how-a-chip-gets-made-visiting-globalfoundries. 
  54. ↑ "Wafer Cleaning Procedures; Photoresist or Resist Stripping; Removal of Films and Particulates". https://www.eesemi.com/wafer-cleaning.htm. 
  55. ↑ "High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates | IEEE Conference Publication | IEEE Xplore". doi:10.1109/IEDM.2006.346959. https://ieeexplore.ieee.org/document/4154394. 
  56. ↑ "High-k/Metal Gates- from research to reality | IEEE Conference Publication | IEEE Xplore". doi:10.1109/IWPSD.2007.4472451. https://ieeexplore.ieee.org/document/4472451. 
  57. ↑ "The High-k Solution - IEEE Spectrum". https://spectrum.ieee.org/the-highk-solution. 
  58. ↑ "High-K/Metal Gate Technology: A New Horizon | IEEE Conference Publication | IEEE Xplore". doi:10.1109/CICC.2007.4405765. https://ieeexplore.ieee.org/document/4405765. 
  59. ↑ Li, Z.; Tian, Y.; Teng, C.; Cao, H. (2020). "Recent Advances in Barrier Layer of Cu Interconnects". Materials 13 (21): 5049. doi:10.3390/ma13215049. PMID 33182434. Bibcode: 2020Mate...13.5049L. 
  60. ↑ Löper, Philipp; Stuckelberger, Michael; Niesen, Bjoern; Werner, Jérémie; Filipič, Miha; Moon, Soo-Jin; Yum, Jun-Ho; Topič, Marko et al. (2015). "Complex Refractive Index Spectra of CH3NH3PbI3 Perovskite Thin Films Determined by Spectroscopic Ellipsometry and Spectrophotometry". The Journal of Physical Chemistry Letters 6 (1): 66–71. doi:10.1021/jz502471h. PMID 26263093. https://doi.org/10.1021/jz502471h. Retrieved 2021-11-16. 
  61. ↑ 61.0 61.1 "Yield and Yield Management". Cost Effective Integrated Circuit Manufacturing. Integrated Circuit Engineering Corporation. 1997. ISBN 1-877750-60-3. https://smithsonianchips.si.edu/ice/cd/CEICM/SECTION3.pdf. Retrieved 2023-01-22. 
  62. ↑ Cutress, Dr Ian. "Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020". https://www.anandtech.com/show/15219/early-tsmc-5nm-test-chip-yields-80-hvm-coming-in-h1-2020. 
  63. ↑ "Advanced MOSFETs and Novel Devices". https://dokumente.unibw.de/pub/bscw.cgi/d10465215/%C3%9Cbung-1.pdf. 
  64. ↑ "Introduction to Semiconductor Technology". p. 6. https://www.st.com/content/ccc/resource/technical/document/application_note/f1/36/51/95/ff/f3/44/19/CD00003986.pdf/files/CD00003986.pdf/jcr:content/translations/en.CD00003986.pdf. 
  65. ↑ "Wafer Backgrind". https://eesemi.com/backgrind.htm. 
  66. ↑ CNET. "Why tech pollution's going global ." April 25, 2002. Retrieved November 9, 2015.

Further reading

  • Kaeslin, Hubert (2008), Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication, Cambridge University Press , section 14.2.
  • Wiki related to Chip Technology
  • Yoshio, Nishi (2017), Handbook of Semiconductor Manufacturing Technology, CRC Press 

External links



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