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| European Processor Initiative (EPI) | |
|---|---|
| File:EPI logo.svg | |
| Type of project | Research & Innovation |
| Country | European Union (10 EU countries[1]) |
| Ministry | EU Horizon 2020, EuroHPC JU |
| Established | December 2018[2][1] |
| Disestablished | March 2026[1] |
| Budget | €150,000,000[1] |
| Website | european-processor-initiative |
European Processor Initiative (EPI) was a strategic European project aiming to design and implement a roadmap for a new family of low-power European processors and accelerators for extreme scale computing, high-performance (HPC), Big Data, Edge and a range of emerging applications including AI and automotive.[3][4]
The EPI project was divided into two phases, often referred to as Phase1/SGA1[5] and Phase2/SGA2 referencing the Specific Grant Agreement legal framework. The first phase was implemented under the European Commission program Horizon 2020 (SGA1: 826647) from December 2018 to December 2021. The second phase was implemented following a EuroHPC Joint Undertaking call (H2020-JTI-EuroHPC-2020-02) by EuroHPC[6] under Specific Grant Agreement No 101036168 (EPI SGA2), from January 2022 to March 2026. The project was co-funded by the European Union, partners’ Member States and Financing Authorities, and by internal partners’ funding.
The Core EPI objectives[3] were the development of European microprocessors and accelerators to support European technological autonomy and sovereignty that will serve as central components of future European supercomputers to tackle societal challenges and boost innovation and the digital transformation of the European economy and science and compete on the global HPC market. In the second phase, the specific focus was to finalize the development of the first generation of low-power microprocessor units and accelerators to target the European Exascale machines, start developing the second generation, and ensure paths for industrialization and commercialization of these technologies.[7]
The project was concluded in 2026 with some significant outcomes.[8]
The consortium developed its general-purpose processors (GPP) using ARM architecture[3][9] and accelerators based on RISC-V ISA[3] and targeted integration in Bull Sequana systems. As part of EPI activities, in 2019, a company, SiPearl, was incorporated to become an industrial arm and commercialise the EPI GPP technology. EPI hardware design was strongly supported by collaborative hardware/software co-design[10] and was complemented with comprehensive, full-stack software ecosystem development to support both GPP and accelerators.[3] Together with flagship scientific applications that have been used to validate the developments,[10] specific application target domains were selected for Phase 1 (automotive) and Phase 2 (AI) that could both benefit from and provide validation of new architectures.
EPI demonstrated several results just after the Phase 2 end in 2026.[11] SiPearl demonstrated the Rhea1 chip running a complete HPC software stack. The system booted on a test board, with a standard Linux distribution running with high-speed HBM memories and their associated hardware performance monitoring counters. It successfully executed the HPL and STREAM benchmarks, demonstrating the readiness of the complete Rhea1 hardware and software ecosystem for HPC workloads to power Exascale systems. Rhea1 features 80 arm® Neoverse V1 cores, more than 61 billion transistors (7.8 billion equivalent gates), built-in High Bandwidth Memory, with 4 stacks of HBM, 4 DDR5 interfaces supporting 2 DIMMs Per Channel, and 104 lanes of PCIe Gen5 interface: up to 6 x 16 lanes + 2 x 4 lanes. Rhea1 was selected for implementation in Jupiter, Europe’s first exascale supercomputer. The next version, Rhea2, was selected for implementation in Alice Recoque, the second European exascale supercomputer.
The project also demonstrated the EPAC (European Processor Accelerator) test-chip family,[12] gathering several IPs from several providers on the same chip:
EPAC development resulted in the EPAC 1.5 test chip that was silicon-proven and in an additional full HPC cluster of the VEC accelerator mapped onto a multi-FPGA system built on the MEEP FPGA infrastructure.[12] The project rolled out the reuse of EPAC IPs and tools in the next EuroHPC projects, like the DARE project.

Consortium partners have also developed further hardware-related IPs (Menta Origami EDA tool, ZeroPoint DenseMem memory compression, and Kalray KVX accelerators) – without going to silicon, as well as provided an open-source release of VPSim, the Virtual Prototyping Simulator by CEA-List, used for early software-hardware co-validation and performance exploration.

Several European projects are using EPI results to implement further steps towards European technology sovereignty: EUPILOT, EUPEX and DARE.[7]
Consortium organized and participated in a large number of events. The most prominent events were the two editions of the EPI Forum (Barcelona in 2024,[13][14] Paris in 2025[15]) and the EPI Codesign Workshop in Heraklion in 2025.[16][17]
To execute the project, an EPI Consortium was built and then selected by the European Union’s Horizon 2020 programme, H2020-ICT-2017-2 calls under the topic ICT-42-2017 Framework Partnership Agreement in European low-power microprocessor technologies (FPA: 800928). The awarded Consortium consisted of European companies, universities, and research organisations, and was led by Bull in France. EPI is a non-legal entity, a consortium organized by 30 institutions from 10 countries in Europe. The members of the consortium were:[18]
| Organization | Type | Industry | Country |
|---|---|---|---|
| Bull | Company | High-performance computing, artificial intelligence, quantum innovation | |
| BSC | Public research center | Supercomputing | |
| Infineon[19] | Company | Semiconductors | |
| Semidynamics | Company | Semiconductors | |
| CEA | Public research center | Energy, defense, security, IT, health | |
| Chalmers University of Technology | Private university | Scientific and technological research, education | |
| ETH Zurich | Public university | Scientific and technological research, education | |
| Foundation for Research & Technology – Hellas | Public research center | Scientific and technological research | |
| GENCI | State-owned company | Supercomputing | |
| Tecnico Lisboa | Public university | Scientific and technological research, education | |
| Forschungszentrum Jülich | Public research center | Scientific and technological research | |
| University of Bologna | Public university | Scientific and technological research, education | |
| Faculty of Electrical Engineering and Computing, University of Zagreb | Public university | Scientific and technological research, education | |
| Fraunhofer | Public research center | Applied science | |
| STMicroelectronics Italy | Company | Semiconductors | |
| E4 Computer Engineering | Company | Engineering | |
| University of Pisa | Public university | Scientific and technological research, education | |
| Surf | Public research center | Scientific and technological research | |
| Kalray | Company | Semiconductors | |
| Extoll | Company | Semiconductors | |
| CINECA | Public research center | Scientific and technological research | |
| BMW Group[19] | Company | Automobile | |
| Elektrobit[19] | Company | Automobile, software | |
| Prove & Run | Company | Software | |
| Karlsruhe Institute of Technology | Public university | Scientific and technological research, education | |
| Menta | Company | Semiconductors | |
| SiPearl | Company | Semiconductors | |
| Kernkonzept | Company | Software | |
| Leonardo[20] | Company | Software | |
| ZeroPoint Technologies[20] | Company | Software |