Binary Representation
Binary Arithmetic
Interfacing Digital and Analog Signals
- Sampling and Quantization (A.pdf)
- Digital-to-Analog Conversion (A.pdf)
- Analog-to-Digital Conversion (A.pdf)
C Program Examples
- Binary Numbers in C programs (A.pdf)
- Binary Addition in C programs (A.pdf)
- Helpful Wikipedia Pages (C.pdf)
- Floating Point Representations (5A.pdf)
- See Floating Point Overview
- See Offset Binary Overview
- See Offset Binary & Sin / Cosine
- See Offset Binary & ADC / DAC
Analysis
Components
Analysis
- Latches and Flipflops (A1.pdf)
- State Transition Table (A2.pdf)
- FSM (Finite State Machine) (A3.pdf)
Components
Memory Arrays
Logic Arrays
- PLA
- PAL
- PLD
- FPGA
- FPGA Structure
- FPGA Configuration (B.pdf)
Synchronous SRAM Timing
Asynchronous SRAM Timing
DRAM Timing
FPGA Architectures
CPLD & FPGA
Design Methodology
Synthesis
- DTL (Diode-Transistor Logic)
- TTL (Transistor-Transistor Logic)
- ECL (Emitter-Coupled Logic)
- CMOS (Complementary MOS)
- Pseudo-nMOS
- Transmission Gate
- BiCMOS (Bipolr + CMOS)
- Domino
- Clocked-CMOS (C2MOS)
- TTL and LVTTL (Low Voltage TTL)
- CMOS and LVCMOS (Low Voltage CMOS)
- SSTL (Stub Series Terminated Logic)
- HSTL (High Speed Tranceiver Logic)
- LVDS (Low Voltage Differential Signaling)
- Wikipedia Pages for Logic Families (A.pdf)
See also
<The necessities in Computer Design>
<The necessities in Computer Architecture>
<The necessities in Computer Organization>
go to [ Electrical_&_Computer_Engineering_Studies ]
Until 2011.12
Chapter 1. Binary Numbers
Minterm, Maxterm, HW
Overflow HW
K-Map
Binary Adder
- Binary Adder (C, S) (pdf)
- Overflow detection circuit (V) (pdf)
BCD to Ex3 Code Coversion, Dont' Care
- BCD to Ex3 Code Conversion (pdf)
Prime Implicant, Dont' Care
- Prime Implicant, Don't Care (pdf)
- HW 3.6 - explain the method of combining 0's and X's
Multiplexer / Demultiplexer
- Multiplexer (pdf)
- HW (TBD)
Flip Flop / Latch
- FF & Latch (pdf)
- FF & Latch HW (pdf)
- Gated D Latch & Master-Slave D FlipFlop (pdf)
- HW (Forbidden state and Indeterminate state) (pdf) (note in #2, S' R' instead of S R)
- Classical Edge Triggered D FlipFlop (pdf)
- HW (addition in SW and HW) (pdf)
- FSM1 (pdf)
- FSM2 (pdf)
- HW (FSM Waveforms) (pdf)
Counter
- Sychronous Counter (pdf)
- Ripple Counter, Multiplexer, Tri-state buffer(pdf)
- Register (pdf)
- Timing (pdf)
- HW (Multiplexer, Shift Register) (pdf)
- Universal Shift Register, Memory Cell (pdf)
- HW (Bit Serial Adder) (pdf)
Memory
Comparator, Multiplier
Multiplexer based design method
midterm result (pdf)
- Edge Triggered Flip Flop (pdf)
- FF Timing (pdf)
Until 2013.07
Number Systems
- Binary Numbers (A.pdf)
- Hexadecimal Numbers (B.pdf)
- Numbers in C programs (C.pdf)
- Codes (pdf)
- Helpful Wikipedia Pages (pdf)
Combinational Circuits
Sequential Circuits
- Latches and Flip-flops (3A.pdf)
- FSM (Finite State Machine) (3B.pdf)
- SR Latch Forbidden State (3C.pdf)
- Flip-flop Timing (3D.pdf)
- Metastability (3E.pdf)
See also
"The necessities in Computer Design"
"The necessities in Computer Architecture"